Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis Christian Pilato, Gianluca Palermo, Antonino Tumeo, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi

High Level Synthesis “ High-Level Synthesis means going from an algorithmic level specification of a behaviour of a digital system to a register level structure that implements that behavior”. McFarland, et al., Proc. IEEE, February 1990. Behavioral specification Design constraints Resource Library Datapath & Controller Objectives Scheduling Allocation Binding Controller Synthesis High-Level Synthesis tool

“ High-Level Synthesis means going from an algorithmic level specification of a behaviour of a digital system to a register level structure that implements that behavior”. McFarland, et al., Proc. IEEE, February 1990.

High Level Synthesis Operation Scheduling Provides the cycle steps in which operations start their execution Resource Allocation Assigns operations and values to hardware components, interconnects them Controller Synthesis Provides the logic to issue datapath operations, based on the control flow Develop polynomial-time algorithms to optimally solve each task? We wish! Unfortunately, these problems are NP-complete

Operation Scheduling

Provides the cycle steps in which operations start their execution

Resource Allocation

Assigns operations and values to hardware components, interconnects them

Controller Synthesis

Provides the logic to issue datapath operations, based on the control flow

Develop polynomial-time algorithms to optimally solve each task?

We wish! Unfortunately, these problems are NP-complete

Motivations All the sub-tasks are NP-complete: no efficient algorithms Interconnection have to be considered: up to 80% of final area All the tasks are closely interdependent Most of the information is available only at the end of the syntesis Guidelines Heuristics approaches with feedback information Genetic algorithms, reducing to single-objective (weighted average) is not efficient NSGA-II

All the sub-tasks are NP-complete: no efficient algorithms

Interconnection have to be considered: up to 80% of final area

All the tasks are closely interdependent

Most of the information is available only at the end of the syntesis

Guidelines

Heuristics approaches with feedback information

Genetic algorithms, reducing to single-objective (weighted average) is not efficient

NSGA-II

The Proposed Methodology Fitness is computed using a full synthesis flow Individuals encode information to perform an entire synthesis cycle

Chromosome encoding Encodes all the information needed for synthesis computations Allocation Binding Represents the mapping between the operations to be performed and the functional unit where it will be executed. Partially controls final area occupation Influences Scheduling, Register Allocation and Interconnection Allocation Second part identified the completion algorithms Scheduling (SchedA), Register Allocation (RegA) and Interconnection Optimization (ConnA)‏ Allocationand binding Completion steps

Encodes all the information needed for synthesis computations

Allocation Binding

Represents the mapping between the operations to be performed and the functional unit where it will be executed.

Partially controls final area occupation

Influences Scheduling, Register Allocation and Interconnection Allocation

Second part identified the completion algorithms

Scheduling (SchedA), Register Allocation (RegA) and Interconnection Optimization (ConnA)‏

Completion Algorithms Scheduling (SchedA)‏ Integer Linear Programming List Based Register Allocation (RegA)‏ Left-edge algorithm Sequential vertex coloring Heuristic clique-covering Interconnection Optimization (ConnA)‏ Port swapping among inputs of a functional unit (if the operation is commutative)‏

Scheduling (SchedA)‏

Integer Linear Programming

List Based

Register Allocation (RegA)‏

Left-edge algorithm

Sequential vertex coloring

Heuristic clique-covering

Interconnection Optimization (ConnA)‏

Port swapping among inputs of a functional unit (if the operation is commutative)‏

Cost function The fitness function has two components area and time Time(x)‏ Estimation of the worst case execution time of solution x Computed as the longest path in the scheduled CDG+DFG Area(x)‏ Estimation of the area occupied by solution x Preferred an estimation rather than real values because Logic Synthesis performed with FPGA tools is slow Computed using a modified, already existing, area model.*

The fitness function has two components area and time

Time(x)‏

Estimation of the worst case execution time of solution x

Computed as the longest path in the scheduled CDG+DFG

Area(x)‏

Estimation of the area occupied by solution x

Preferred an estimation rather than real values because Logic Synthesis performed with FPGA tools is slow

Computed using a modified, already existing, area model.*

Problem independent elements Initial population Randomly generated Seeded by interesting candidates Ranking and Selection Solution sorted in different levels according to fitness values Ranking selection emphasize good solution points Accelerated using fast-non-dominated-sort of NSGA-II

Initial population

Randomly generated

Seeded by interesting candidates

Ranking and Selection

Solution sorted in different levels according to fitness values

Ranking selection emphasize good solution points

Accelerated using fast-non-dominated-sort of NSGA-II

The Genetic Algorithm Elitist NSGA-II applies a crowded-comparison operator Uniform crossover Applied to the 80% of the population Mix solution bindings Mix genes that represent completion algorithms Mutation Applied to the 10% of the population Each gene is modified with P=0.01% Alleles are mutated to admissible values Operation: new binding Algorithm: another algorithm is choosed to perform the corresponding step

Elitist

NSGA-II applies a crowded-comparison operator

Uniform crossover

Applied to the 80% of the population

Mix solution bindings

Mix genes that represent completion algorithms

Mutation

Applied to the 10% of the population

Each gene is modified with P=0.01%

Alleles are mutated to admissible values

Operation: new binding

Algorithm: another algorithm is choosed to perform the corresponding step

The Goal: Reduce Execution Time! Even if logic synthesis is not performed, and area of the final circuit is extimated through a model, execution time for each evaluation can reach several seconds Large examples can take hours to perform the exploration Use fitness inheritance to reduce the number of evaluations Substitute evaluations with inherited estimations Two approaches Estimations based on all the individuals evaluated from the beginning of the algorithm (ancestors)‏ Estimations based only on the individuals evaluated in the latest generation (parents)‏

Even if logic synthesis is not performed, and area of the final circuit is extimated through a model, execution time for each evaluation can reach several seconds

Large examples can take hours to perform the exploration

Use fitness inheritance to reduce the number of evaluations

Substitute evaluations with inherited estimations

Two approaches

Estimations based on all the individuals evaluated from the beginning of the algorithm (ancestors)‏

Estimations based only on the individuals evaluated in the latest generation (parents)‏

Fitness Inheritance Model Two types of inheritance Based on ancestors Based on parents Distance metric: Consider only near individuals: Weighted average on different objectives: Delta function Normalized distance that represents diversity Analogy with N-dim hypersphere remembers Physics equations, with where value 1 is considered as infinite distance (individual is too different, so it has no contribution to fitness)

Two types of inheritance

Based on ancestors

Based on parents

Test Problems & Experimental Settings Typical high level synthesis benchmarks 2D-DCT, RGB-to-YUV from the JPEG compression algorithm Most computationally intensive phases RGB to YUV can be unrolled: factor x2 and x4 EWF: fifth order elliptic wave filter Population size: 1000 individuals, evolving up to max 200 generations Target: Xilinx Field Programmable Gate Arrays Searching for the best area-performance trade-offs for the specific device and architecture

Typical high level synthesis benchmarks

2D-DCT, RGB-to-YUV from the JPEG compression algorithm

Most computationally intensive phases

RGB to YUV can be unrolled: factor x2 and x4

EWF: fifth order elliptic wave filter

Population size: 1000 individuals, evolving up to max 200 generations

Target: Xilinx Field Programmable Gate Arrays

Searching for the best area-performance trade-offs for the specific device and architecture

EWF (Pareto)‏

DCT (Pareto)‏

RGBtoYUVx4 (Pareto solutions with and without inheritance)‏

Overall execution time/chromosome size

Fitness evaluation time generation by generation (EWF)‏

Fitness evaluation time generation by generation (RGBtoYUVx4)‏

Inheritance benefits Number of fitness function evaluations ( p=0,557 )‏ Execution time for fitness and overall execution

Number of fitness function evaluations ( p=0,557 )‏

Execution time for fitness and overall execution

Conclusions High level synthesis based on NSGA-II and fitness inheritance The use of fitness inheritance No substantial decrease in the overall quality 25% reduction of the execution time Future work Population sizing Scalability

High level synthesis based on NSGA-II and fitness inheritance

The use of fitness inheritance

No substantial decrease in the overall quality

25% reduction of the execution time

Future work

Population sizing

Scalability