Day3 Open

Loading...

Flash Player 9 (or above) is needed to view presentations.
We have detected that you do not have it on your computer. To install it, go here.

0 comments

Post a comment

    Post a comment
    Embed Video
    Edit your comment Cancel

    Favorites, Groups & Events

    Day3 Open - Presentation Transcript

    1. Day3 Day2 Review ● ● Combinational Logic ● Verilog HDL Basic, Combinational Logic ● HDL coding ● ModelSim simulation, waveform display ● Q: When & Why do I need simulation?? Day3 Topics ● ● 順序控制的邏輯實現 ( 組合邏輯) ● 實驗板介紹 , Quartus 介紹 , ● Lab: 組合邏輯 LED 模擬 ● 順序控制的邏輯實現 ( 循序邏輯) ● Lab: 自保回路 (R-S Latch) 電路實驗 ● Lab: 計時電路 (TIMER) 電路實驗
    2. HDL Coding Techniques, RTL Code Example ● http://www.xilinx.com/itp/3_1i/data/fise/xst/chap02/xst0200 ●
    SlideShare Zeitgeist 2009

    + ph5077ph5077 Nominate

    custom

    138 views, 0 favs, 0 embeds more stats

    More info about this document

    © All Rights Reserved

    Go to text version

    • Total Views 138
      • 138 on SlideShare
      • 0 from embeds
    • Comments 0
    • Favorites 0
    • Downloads 2
    Most viewed embeds

    more

    All embeds

    less

    Flagged as inappropriate Flag as inappropriate
    Flag as inappropriate

    Select your reason for flagging this presentation as inappropriate. If needed, use the feedback form to let us know more details.

    Cancel
    File a copyright complaint
    Having problems? Go to our helpdesk?

    Categories