邏輯設計與 CPLD 應用
2009, Mar
Ron Liu

Agenda of Day1
Course Introduction

Course Objectives
目標
Digital Logic Basic Concept
●
● Understanding of FPGA/CPLD device
● Verilog HDL Simulation and Verification by ModelSim
● Verilog HDL for synthesis
● Altera design flow in Quartus
● Design a project with 『 GFEC MAX II Starter Kit 』

Course Flow
Introduction
Coding for Synthesis
FPGA/CPLD
Introduction Quartus
Boolean Algebra
Verilog HDL Post Simulation
Basic
Introduction GFEC
Introduction
Starter Kit
ModelSim
FSM Design
Combination Logic
Project
Sequential Logic

Course Schedule
Day1: 3/2
Day2: 3/9
Day3: 3/16
Day4: 3/23
Day5: 3/30
上課時間為 8:10~11:50, 13:10~16:40

Tools: What we need
Windows PC
●
Verilog HDL Simulator:
●
Modelsim, to compile and execute HDL for
simulation, debugging, verification
Device/Board: GFEC MAX II Starter Kit, IO Board
●
Synthesizer/Fitter/Porgrammer: Quartus/Altera
●

Reference Material, books
[Verliog 語言]
Verilog數位電路設計-範例寶典，(基礎篇) 儒林 鄭羽伸，2006/09
●
Verilog 硬體描述語言數位電路-設計實務，鄭信源，儒林，2007/07
●
Verilog FPGA晶片設計(附範例光碟片)(修訂版) 林灶生，全華科技，2008/11
●
[FPGA/CPLD/ASIC 硬體架構]
FPGA 和 CPLDs 設計實務，何正弘譯，全華科技
●
FPGA系統設計，鄭泰源、鍾隆宇，全華科技，2006/08
●
系統晶片設計 使用Quartus II，廖裕評 陸瑞強 編著，全華科技
●
[ASIC, PLD, HDL]
Application-Specific Integrated Circuits, Michael John, Sebastian
●
Smith, Addison Wesley
on-line book http://www.edacafe.com/books/ASIC/ASICs.php

Reference Material, Tool, Web
茂綸 starter Kit]
『GFEC MAX II Starter Kit, 使用說明書』,
●
CD:\\User Guide\\MAXII_SG_V2.pdf
『MAX II Device Handbook』，CD:\\Altera_handbook\\max2_mii5v1.pdf
●
\\MAX _II_Training_tutorial\\Quartus_II_Tutorial.ppt
●
[Altera] [
Altera DOC QuartusII Handbook Vol2, 3
●
Altera on-line training,
●
http://www.altera.com/education/training/curriculum/cpld/trn-cpld.html
[ModelSim]
Tools on-line help
●
[Other]
http://en.wikipedia.org/
●