EDF based scheduling for periodic tasks (deadlines <= period)
The scheduler is capable of creating tasks based on ( , p, e, D) parameters.
1 uSec granularity for all timing parameters ( , p, e, D)
Aperiodic tasks are scheduled using static priority based preemptive scheduling.
The scheduler can also keep track of the current CPU utilization.
Design Priority Queue based on the next DEADLINE Ready Q Wait Q I Aperiodic Q Priority Queue based on the next RELEASE Time Priority Queue based on task PRIORITY Timer 0 Res. Block Q Priority Queue based on Deadline / PRIORITY Resource Timer 1
Implemented on C6713 DSK
TMS320C6713 DSP Processor
VLIW Architecture (with 8 instructions / cycle)
Tested for all parameters ( , p, e, D)
Keeps track of Deadline miss & TBE counts for every thread
Also keeps track of thread wise execution time upto 1 s res.
About 2400 SLOCs of source code (1000 lines assembly)
Things to do
Overall CPU utilization to be maintained
Test aperiodic tasks with resources
Fix few bugs
Test with some real benchmarks
P12: MAC Protocol Implementation on Atmel AVR for Underwater Communication
by Shaolin Peng
CSC 714 Real Time Computer Systems
Aloha Protocol Atmega168 MACA Protocol Small & Sparse Network Small Packet Size Development Platform: STK500 AVR Studio
P1: Debugging Instrument
Set up UART communication with the HyperTerminal on PC
Connect two boards using wire as a start
Wait only after sending, not after receiving
P3: Flexible Length Packet Receiving
Receive the first two bytes, decode and decide
P4: CRC Consideration
4 bits -> 8 bits ( x^ 8 + x^ 2 + x + 1)
Problem List 2
P5: Random Number Generator
ADC or Timer Counter
P6: No response problem
Set maximum r etr ies number
P7: Hardware Limitation
Compile different files using different optimization levels
Experimental Set u p Lake Raleigh Throughput= Successfully received packets Total packets sent out
Compare with MACA
During the testing time, Aloha received almost twice data than MACA
P13: Power-Aware DVFS on PowerPC 405LP: Front Bus Scaling
Mohamed Nishar Kamaruddin
Previous work with the IBM 405LP board showed that Feedback-DVS of the processor voltage and frequency produces considerable power savings.
Our work is to study the frequency scaling for the memory subsystem to achieve power savings. We also study the feasibility of integrating this with the existing feedback DVS-EDF scheduling schemes.
Development up to present
Experimented with different operating points including those with same processor frequency but with different memory subsystem frequencies. This was done on a number of applications.
Changes to data acquisition programs and sample applications to record the power savings of the memory subsystem.
Integration of PLB frequency scaling into the various existing feedback DVS-EDF scheduling schemes.
Frequency scaling of the memory subsystem was found to produce significant power savings. Reducing the FSB freq from 100MHz to 50 MHz for a tight noop looped application produced nearly 34% energy savings.
Fitting this into the PID Feedback scheduling - we changed all operating points to use half of their original PLB frequencies. Energy savings now: 1.38%.
This is because the various operating points defined in the PID feedback scheduling code already scale PLB frequency along with processor frequency.
For memory intensive operation, energy savings: 1.1%