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My Report on adders


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  • 2. TABLE OF CONTENTS Page No.1)Introduction 42)Types of adders 42.1)1 bit adder 4 2.11)Half adder/subs tractor 5 2.111)Design 5 2.112) Pros and Cons 5 2.113)Verilog Code 5 2.12)Full adder 6 2.121)Design(adder) and sub tractor 6 2.122) Pros and Cons 7 2.123)Verilog Code 72.2)Ripple Carry adder 7 2.21)Design(adder and sub tractor) 8 2.22) static adder circuit 9 2.23) Pros and cons 9 2.24)Some interpretation about carry 10 2.25)Pros and cons 10 2.26) Manchester carry chain implementation 10 2.27) Pros and Cons 11 2.28)Verilog Code 122.3)Carry look ahead adder 13 2.31)Design 13 2.32) Pros and Cons 16 2.33)Verilog Code 162.4) Carry select/skip adder 19 2.41)Design 19 2.42) Pros and Cons 21 2.43)Verilog Code 212.6)Carry save adder 23 2.61)Design 23 2 2.62) Pros and Cons 23 2.63)Verilog Code 23
  • 3. 2.7)Binary tree adder 24 2.71)Group PG logic 24 2.72)Design 24 2.73)Pros and Cons 253) Comparison between adders and conclusion 264) Bibliography 26LIST OF FIGURES Page No.1)Fig1:-half 1 bit adder 42)Fig2:- full 1 bit adder 43)Fig3:-half adder design 54)Fig4:-full adder design 65)Fig5:-adder with sub tractor 66)Fig6:-ripple carry adder 87)Fig7:-adder and sub tractor(ripple) 88)Fig8:- static adder circuit(cmos) 99)Fig9:- Manchester carry chain 1110)Fig10:- Manchester circuit with pass transistor 1111)Fig11:- rtl diagram ripple carry adder circuit 1312)Fig12:-propagate and generate adder design 1413)Fig13:-carry look ahead block diagram 1414)Fig14:-carry look ahead design circuit 15 315)Fig15:-CLA rtl diagram 18
  • 4. 16)Fig16:-carry skip adder block diagram 1917)Fig17:-carry skip adder circuit(Manchester) 2018)Fig18:- carry skip adder critical path 2019)Fig19:- carry skip adder rtl 2220)Fig20:-carry save adder 2321)Fig21:-binary tree functioning 241)Introduction :- In digital electronics adder is a digital circuit that performsaddition of numbers, these can be classified into 1 bit adders and multi bit adders.Further 1bit adders are categorized in half adders and full adders. These are notonly used in ALU but also in memory for calculating addresses, table indices andmany more.2)Types of adders :-There are several type of adders as mentioned further below2.1) 1 bit adder:- Consider 2 binary variables a and b, which can have 4combinations when adding i.e. 0+0=0, 0+1=1,1+0=1,1+1=10 , here the last resultis binary 10,which can of course can not exceed of 1 bit, here concept of carryoutcomes into the picture. 4 Fig1 Fig2
  • 5. 2.11)Half adder:- A simple 1 bit adder, with 2 binary inputs is known as halfadder. Its sum and carryout expression can be given as2.111)Design A B sum CoutSum= a XOR b 0 0 0 0Carryout= a AND b 0 1 1 0 1 0 1 0 1 1 0 1 Fig 32.112)Pros and Cons:-half adder is useful for adding two 1 bit numbersonly.Delay generated is 1 unit AND-OR delay. carry is available earlier than sum.2.113)Verilog code:- module half adder(input a, input b ,output sum, output carry){ assign sum=a^b; assign carry =a&b;end module} 5
  • 6. 2.12)Full adder:- When 3 single bits are added A b cin sum coutin a row, adder known as a full adder. Sum and 0 0 0 0 0carry out expression can be given as below 0 0 1 1 02.121)Design :- 0 1 0 1 0Sum =a XOR b 0 1 1 0 1Carry out=a AND b + b AND c + a AND c 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Fig 4 6 Fig 5
  • 7. The above figure shows how an adder and sub tractor can be implemented in thesame module, for adder ci=0,and for sub tractor ci=1,binv is selected ,thuscomputing 2’s complement and adding to the ai input.2.122)Pro and Cons :-when implementing adder and sub tractor both in singlemodule, cin should be high, which states that, only half adder/sub tractor can beimplemented by this. Delay generated is 2 unit AND-OR delay for both the sumand carry.2.123)Verilog code:- module fulladder(input a, input b, input cin, output sum, output cout){ assign sum=a^b^cin; assign cout=a&b+b&c+a&c; end module}2.2)Ripple Carry adder:- now when n bit adders are if made using 1 bit adders(n1 bit adders, where for 1 bit addition fulladders and halfadder is used(half adder for1st stage, as often carry in at for 1st stage remains zero and fulladders for remainingof the stages)we can say carry is rippled through stages. This is known as carryripple adder. 7
  • 8. 2.21)Design:- Fig 6The above figure is a carry ripple adder for 4 bit addition and the below figureshows how a subs tractor can be represented as n bit rippled subs tractor. For substractor operation ci=1, 2nd input bi is complemented, soSubtraction=ai-bi=ai+bi‘+1 8 Fig 7
  • 9. 2.22)Static adder circuit :- The carry and sum expression for the full adder can beagain written asCarry ‘(ai+bi+ci) Fig 8The above figure is a static cmos representation of full adder.2.23)Pros and Cons:-It used 28 transistor for the implementation of full adder, 9also Cout is available in complimented form, which again need to be invertedusing cmos inverter to get the Cout in non complemented form.
  • 10. 2.24)Some important interpretation about carry:- From the full adder truthtable we can easily interpret , carry out is killed or deleted when both of the inputsto the fulladder are zero, irrespective of carry in whether it is 1 or 0.The 2ndobservation is carry which is feed by the previous stage propagates to the nextstage when either of the inputs to the full adder at present stage is 1(high).Theanother observation states carry is generated at present stage and will be feed tonext stage when both of the inputs to the full adders are high. Hence in theexpression “, 1st term tells about carry generation at thepresent stage, and 2nd term states about carry propagation to the next stage(look weused XOR gate there in the design of full adder, in place of or gate in 2nd termhere, which gives is the original carryout expression, just to avoid use of extra ORgate in design, as it does effect either XOR gate or OR gate is used for carry outsince the only difference caused between 2 gates is for when both of the inputs arehigh ,that even is compensated, because we consider carry generation by 1st term inabove expression to rise carry out high.2.25)Pros and cons:-however 1 OR gate for propagation computation is used forease of access, and to minimize the delay in n bit adder. It induce more hardwarecompared to the original n bit full adder implementation.2.26)Manchester carry chain implementation:- Using cmos the carrypropagation and generation condition is achieved. when pi(propagate) signal ishigh for particular stage(here i stands for n stages in ripple carry adder, i<=n).carryin(ci) is passed to cout, otherwise either carry is generated if Gi signal is high orcarry is deleted if di signal is high(di=ai’.bi’).Now need of delete signal can be 10
  • 11. avoid when using precharge transistor ᴓ signal is used. Fig 10In the above figure initially ᴓ=1,it pre -charges and for the kth stage(0<k<n) carryis either propagated ,generated based upon pi and gi signal respectively, otherwisecarry is killed.2.27)Pro and cons:-Use of Manchester carry chain for propagation and generationof c out, reduced complexity and avoids the need for more multiplexers in 11hardware implementation.
  • 12. 2.28)Verilog Code:- module fulladd(a ,b, carryin, sum, carryout); input a, b, carryin; /* add these bits*/ output sum, carryout; /* results */ assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */ endmodule module nbitfulladd(a,b,carryin,sum,carryout); input[7:0] a, b; /* add these bits */ input carryin; /* carry in*/ output [7:0] sum; /* result */ output carryout; wire [7:1] carry; /* transfers the carry between bits */ fulladd a0(a[0],b[0],carryin,sum[0],carry[1]); fulladd a1(a[1],b[1],carry[1],sum[1],carry[2]); fulladd a2(a[2],b[2],carry[2],sum[2],carry[3]); fulladd a3(a[3],b[3],carry[3],sum[3],carryout); endmodule 12
  • 13. Fig 112.3)Carry look ahead adder:- As discussed in ripple carry adder, the significantdelay produced due to ripple operation is a trade off. this can be minimized whencarry in to all stages are computed initially itself, as it will minimize the wait forcarry at every stage in a n bit adder, hence sum and carryout expression can be rewritten as2.31)Design:-Sum=ai XOR bi XOR CiCarry out=Gi+Pi.Ci, where Pi=ai XOR bi and 13
  • 14. Fig 12Now further delay due to XOR gate can be mimized by 1 unit, if Pi=ai+bi is usedand sum computation is accomplished using XOR gate,hence inclusion of one ORgate. 14 Fig 13
  • 15. Fig 14For the above figure sum and carry expressions can be written as 15Co=Go+PoCin
  • 16. C1=G1+P1CoC2=G2+P2C1C3=G3+P3C2C3=G3+P3(G2+P2(G1+P1(Go+PoCin)))C3=G3+P3G2+P3G2G1+P3P2P1G0+P3P2P1PoCin2.32)Pros and Cons:- Delay generated in whole n bit adder here is 5 unit, 1 unitAND or OR delay from the 1st stage.2 unit delay AND+OR in 2nd stage and 2 unitAND+OR delay, in 3rd stage of sum computation using XOR gates.Carries are computed for all the stages ,as long as inputs adder,but complexity ofhardware increases,here architecture may be easier compared to ripple carry adderbut no. of fan ins to to gates,and also wire length for inputs to reachout for as the no of bits goes on increasing the benefits of carry look aheadadder diminishes, however it is better than ripple carry adder upto12 bits additionoperation.2.33)Verilog Code:- module sum(a,b,carryin,result); input a, b, carryin; /* add these bits*/ output result; /* sum */ assign result = a ^ b ^ carryin; /* compute the sum */ 16 endmodule
  • 17. module carry_block(a,b,carryin,carry); input [3:0] a, b; /* add these bits*/ input carryin; /* carry into the block */ output [3:0] carry; /* carries for each bit in the block */ wire [3:0] g, p; /* generate and propagate */ assign g[0] = a[0] & b[0]; /* generate 0 */ assign p[0] = a[0] ^ b[0]; /* propagate 0 */ assign g[1] = a[1] & b[1]; /* generate 1 */ assign p[1] = a[1] ^ b[1]; /* propagate 1 */ assign g[2] = a[2] & b[2]; /* generate 2 */ assign p[2] = a[2] ^ b[2]; /* propagate 2 */ assign g[3] = a[3] & b[3]; /* generate 3 */ assign p[3] = a[3] ^ b[3]; /* propagate 3 */ assign carry[0] = g[0] | (p[0] & carryin); assign carry[1] = g[1] | p[1] & (g[0] | (p[0] & carryin)); assign carry[2] = g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin))); assign carry[3] = g[3] | p[3] & (g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin))));endmodule 17module carry_lookahead_adder(a,b,carryin,sum,carryout); input [3:0] a, b; /* add these together */
  • 18. input carryin;output [3:0] sum; /* result */output carryout;wire [4:1] carry; /* intermediate carries *//* build the carry-lookahead units */carry_block b0(a[3:0],b[3:0],carryin,carry[4:1]);/* build the sum */sum a0(a[0],b[0],carryin,sum[0]);sum a1(a[1],b[1],carry[1],sum[1]);sum a2(a[2],b[2],carry[2],sum[2]);sum a3(a[3],b[3],carry[3],sum[3]);endmodule 18 Fig 15
  • 19. 2.4)Carry skip/select adder:- In binary system, carry either can be 0 or 1.onlytwo possibility of value provides feasibility for choosing between two. So if thereis a mechanism to select carry, or better say, skipping carry through several stages,then delay minimization can be better obtained.The expression for C3 for 4 bit adder, contains term P3P2P1PoCin, all the signalsare computed at initial stage and are available to user, the term signifies if there is acarry generation at 1st stage, and is propagated till last stage, the worst case delaycan be avoided if propagated carry is selected at initial stage itself, and skippedthrough remaining stages.2.41)Design:- Fig 16When computing BP=P1P2P3Po,carry is selected from 1st stage, for n bitadders,we can divide n bits into stages of m bits, where carry is rippled through 1st 19m bits, and then it is skipped, in this manner,delay can be minimized.
  • 20. Fig 17The above figure shows Manchester carry select implementation, here either carryis generated or propagated in chain, implemented using nmos. Fig 18Also from the above figure we interpret till carry is selected either 0 or 1, by themultiplexer, computation for selection of carry from the next stage is already 20available.
  • 21. 2.42)Pros and Cons:-complexity may increase due to multiplexer operation,however multiplexers can be implemented by simple cmos inverter by selection ofproper inputs to mux. Critical path is shown in gray color.2.43)Verilog Code:- module fulladd_p(a,b,carryin,sum,carryout,p); input a, b, carryin; /* add these bits*/ output sum, carryout, p; /* results including propagate */ assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */ assign p = a | b; endmodule module carryskip(a,b,carryin,sum,carryout); input [7:0] a, b; /* add these bits */ input carryin; /* carry in*/ output [7:0] sum; /* result */ output carryout; wire [8:1] carry; /* transfers the carry between bits */ wire [7:0] p; /* propagate for each bit */ wire cs4; /* final carry for first group */ 21 fulladd_p a0(a[0],b[0],carryin,sum[0],carry[1],p[0]);
  • 22. fulladd_p a1(a[1],b[1],carry[1],sum[1],carry[2],p[1]); fulladd_p a2(a[2],b[2],carry[2],sum[2],carry[3],p[2]); fulladd_p a3(a[3],b[3],carry[3],sum[3],carry[4],p[3]); assign cs4 = carry[4] | (p[0] & p[1] & p[2] & p[3] & carryin); fulladd_p a4(a[4],b[4],cs4, sum[4],carry[5],p[4]); fulladd_p a5(a[5],b[5],cs4, sum[5],carry[6],p[5]); fulladd_p a6(a[6],b[6],cs4, sum[6],carry[7],p[6]); fulladd_p a7(a[7],b[7],cs4, sum[7],carry[8],p[7]); assign carryout = carry[8] | (p[4] & p[5] & p[6] & p[7] & cs4);endmodule 22
  • 23. Fig 192.5)Carry save adder:-when n bit adder is implemented, still carry is rippled tothe next stage, of same row, even though inputs to the lower next stage is ready,but kept in wait state, until the sum and carry output didn’t come from the abovestage. This induces delay, now it can be optimized, if carry out is passed diagonallyto the lower next stage,instead of rippling to the next stage of same row. Carrycomputation is not performed, but it is saved upto last row ,where the results areobtained finally, in the last bottom row, carry is rippled however, but itsignificantly reduce the amount of delay occurred due to rippling operation.2.51)Design:-2.52)Pros and Cons:- This adder is used in array multiplier ,delay is reducedsignificantly compared to ripple carry adder, for n*n multiplier delay elapsed when 23ripple carry adders are used in 2n,where as if carry save adders are used worst casedelay is n+3 units. carry save adders are used in binary tree adders also.
  • 24. 2.6)Binary tree adder:-Understanding binary tree adder requires concepts ofgroup PG logic ,which is explained below.2.61)Group PG logic:- The sum and carry expression for full adder in terms ofpropagate and generate signal are written asSum=ai XOR bi XOR CiCarry out=Gi+Pi.Ci, where Pi=ai XOR bi and for n bit adder carry out for nth stage(let here n=4) is given asC3=G3+P3G2+P3G2G1+P3P2P1G0+P3P2P1PoCinWe can write P=PoP1P2P3 and G= G3+P3G2+P3G2G1+P3P2P1G0Hence C3=G+PCin2.62)This concept is used in tree adder shown below 24 Fig 20
  • 25. 2.63)Pros and Cons:-Architecture is easy when group PG logic is used butcomplexity during implementation increases.3)Comparison among adders and conclusions:- All the adders for 1bit additionuses full adder operation,also for most of the adders,performance in terms of powerand delay is similar upto 4 bits. Carry look ahead adder reduces the delaycompared to ripple carry adder but as the adder size increases complexity increasesalso,fan in to the gates increases.Delay of the circuit depends upon,how many gatesare connected in series and delay of a gate depends upon no of fan ins, so the laterterm dominates as adder size increases in carry look ahead adder. In static adderimplementation using cmos, if inverted inputs are applied then need of cmosinverter is vanished and less no. of transistors are required.For the carry selectadder, significant amount of time can be utilized if bit size carry selection areprogressively increased.4)Bibliography :-1) cmos vlsi design book by neil weste2) cmos vlsi design book by k l kishore3) 25