Upcoming SlideShare
×

Thanks for flagging this SlideShare!

Oops! An error has occurred.

×
Saving this for later? Get the SlideShare app to save on your phone or tablet. Read anywhere, anytime – even offline.
Standard text messaging rates apply

5,356
views

Published on

4 Likes
Statistics
Notes
• Full Name
Comment goes here.

Are you sure you want to Yes No
• Be the first to comment

Views
Total Views
5,356
On Slideshare
0
From Embeds
0
Number of Embeds
2
Actions
Shares
0
482
0
Likes
4
Embeds 0
No embeds

No notes for slide

### Transcript

• 1. “A Comparative Study On Various Adders” A REPORT Submitted by PEEYUSH PASHINE(2011H140033H) M.E. (EMBEDDED SYSTEMS)BIRLA INSTITUTE OF TECHNOLOGY AND SCINCE PILANI- HYDERABAD 1
• 5. 2.11)Half adder:- A simple 1 bit adder, with 2 binary inputs is known as halfadder. Its sum and carryout expression can be given as2.111)Design A B sum CoutSum= a XOR b 0 0 0 0Carryout= a AND b 0 1 1 0 1 0 1 0 1 1 0 1 Fig 32.112)Pros and Cons:-half adder is useful for adding two 1 bit numbersonly.Delay generated is 1 unit AND-OR delay. carry is available earlier than sum.2.113)Verilog code:- module half adder(input a, input b ,output sum, output carry){ assign sum=a^b; assign carry =a&b;end module} 5
• 6. 2.12)Full adder:- When 3 single bits are added A b cin sum coutin a row, adder known as a full adder. Sum and 0 0 0 0 0carry out expression can be given as below 0 0 1 1 02.121)Design :- 0 1 0 1 0Sum =a XOR b 0 1 1 0 1Carry out=a AND b + b AND c + a AND c 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Fig 4 6 Fig 5
• 8. 2.21)Design:- Fig 6The above figure is a carry ripple adder for 4 bit addition and the below figureshows how a subs tractor can be represented as n bit rippled subs tractor. For substractor operation ci=1, 2nd input bi is complemented, soSubtraction=ai-bi=ai+bi‘+1 8 Fig 7
• 9. 2.22)Static adder circuit :- The carry and sum expression for the full adder can beagain written asCarry out=ai.bi+(ai+bi)ciSum= ai.bi.ci+Cout ‘(ai+bi+ci) Fig 8The above figure is a static cmos representation of full adder.2.23)Pros and Cons:-It used 28 transistor for the implementation of full adder, 9also Cout is available in complimented form, which again need to be invertedusing cmos inverter to get the Cout in non complemented form.
• 11. avoid when using precharge transistor ᴓ signal is used. Fig 10In the above figure initially ᴓ=1,it pre -charges and for the kth stage(0<k<n) carryis either propagated ,generated based upon pi and gi signal respectively, otherwisecarry is killed.2.27)Pro and cons:-Use of Manchester carry chain for propagation and generationof c out, reduced complexity and avoids the need for more multiplexers in 11hardware implementation.
• 12. 2.28)Verilog Code:- module fulladd(a ,b, carryin, sum, carryout); input a, b, carryin; /* add these bits*/ output sum, carryout; /* results */ assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */ endmodule module nbitfulladd(a,b,carryin,sum,carryout); input[7:0] a, b; /* add these bits */ input carryin; /* carry in*/ output [7:0] sum; /* result */ output carryout; wire [7:1] carry; /* transfers the carry between bits */ fulladd a0(a[0],b[0],carryin,sum[0],carry[1]); fulladd a1(a[1],b[1],carry[1],sum[1],carry[2]); fulladd a2(a[2],b[2],carry[2],sum[2],carry[3]); fulladd a3(a[3],b[3],carry[3],sum[3],carryout); endmodule 12
• 13. Fig 112.3)Carry look ahead adder:- As discussed in ripple carry adder, the significantdelay produced due to ripple operation is a trade off. this can be minimized whencarry in to all stages are computed initially itself, as it will minimize the wait forcarry at every stage in a n bit adder, hence sum and carryout expression can be rewritten as2.31)Design:-Sum=ai XOR bi XOR CiCarry out=Gi+Pi.Ci, where Pi=ai XOR bi and Gi=ai.bi. 13
• 14. Fig 12Now further delay due to XOR gate can be mimized by 1 unit, if Pi=ai+bi is usedand sum computation is accomplished using XOR gate,hence inclusion of one ORgate. 14 Fig 13
• 15. Fig 14For the above figure sum and carry expressions can be written as 15Co=Go+PoCin
• 16. C1=G1+P1CoC2=G2+P2C1C3=G3+P3C2C3=G3+P3(G2+P2(G1+P1(Go+PoCin)))C3=G3+P3G2+P3G2G1+P3P2P1G0+P3P2P1PoCin2.32)Pros and Cons:- Delay generated in whole n bit adder here is 5 unit, 1 unitAND or OR delay from the 1st stage.2 unit delay AND+OR in 2nd stage and 2 unitAND+OR delay, in 3rd stage of sum computation using XOR gates.Carries are computed for all the stages ,as long as inputs adder,but complexity ofhardware increases,here architecture may be easier compared to ripple carry adderbut no. of fan ins to to gates,and also wire length for inputs to reachout for gatesincreases.so as the no of bits goes on increasing the benefits of carry look aheadadder diminishes, however it is better than ripple carry adder upto12 bits additionoperation.2.33)Verilog Code:- module sum(a,b,carryin,result); input a, b, carryin; /* add these bits*/ output result; /* sum */ assign result = a ^ b ^ carryin; /* compute the sum */ 16 endmodule
• 17. module carry_block(a,b,carryin,carry); input [3:0] a, b; /* add these bits*/ input carryin; /* carry into the block */ output [3:0] carry; /* carries for each bit in the block */ wire [3:0] g, p; /* generate and propagate */ assign g[0] = a[0] & b[0]; /* generate 0 */ assign p[0] = a[0] ^ b[0]; /* propagate 0 */ assign g[1] = a[1] & b[1]; /* generate 1 */ assign p[1] = a[1] ^ b[1]; /* propagate 1 */ assign g[2] = a[2] & b[2]; /* generate 2 */ assign p[2] = a[2] ^ b[2]; /* propagate 2 */ assign g[3] = a[3] & b[3]; /* generate 3 */ assign p[3] = a[3] ^ b[3]; /* propagate 3 */ assign carry[0] = g[0] | (p[0] & carryin); assign carry[1] = g[1] | p[1] & (g[0] | (p[0] & carryin)); assign carry[2] = g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin))); assign carry[3] = g[3] | p[3] & (g[2] | p[2] & (g[1] | p[1] & (g[0] | (p[0] & carryin))));endmodule 17module carry_lookahead_adder(a,b,carryin,sum,carryout); input [3:0] a, b; /* add these together */
• 18. input carryin;output [3:0] sum; /* result */output carryout;wire [4:1] carry; /* intermediate carries *//* build the carry-lookahead units */carry_block b0(a[3:0],b[3:0],carryin,carry[4:1]);/* build the sum */sum a0(a[0],b[0],carryin,sum[0]);sum a1(a[1],b[1],carry[1],sum[1]);sum a2(a[2],b[2],carry[2],sum[2]);sum a3(a[3],b[3],carry[3],sum[3]);endmodule 18 Fig 15
• 19. 2.4)Carry skip/select adder:- In binary system, carry either can be 0 or 1.onlytwo possibility of value provides feasibility for choosing between two. So if thereis a mechanism to select carry, or better say, skipping carry through several stages,then delay minimization can be better obtained.The expression for C3 for 4 bit adder, contains term P3P2P1PoCin, all the signalsare computed at initial stage and are available to user, the term signifies if there is acarry generation at 1st stage, and is propagated till last stage, the worst case delaycan be avoided if propagated carry is selected at initial stage itself, and skippedthrough remaining stages.2.41)Design:- Fig 16When computing BP=P1P2P3Po,carry is selected from 1st stage, for n bitadders,we can divide n bits into stages of m bits, where carry is rippled through 1st 19m bits, and then it is skipped, in this manner,delay can be minimized.
• 20. Fig 17The above figure shows Manchester carry select implementation, here either carryis generated or propagated in chain, implemented using nmos. Fig 18Also from the above figure we interpret till carry is selected either 0 or 1, by themultiplexer, computation for selection of carry from the next stage is already 20available.
• 21. 2.42)Pros and Cons:-complexity may increase due to multiplexer operation,however multiplexers can be implemented by simple cmos inverter by selection ofproper inputs to mux. Critical path is shown in gray color.2.43)Verilog Code:- module fulladd_p(a,b,carryin,sum,carryout,p); input a, b, carryin; /* add these bits*/ output sum, carryout, p; /* results including propagate */ assign {carryout, sum} = a + b + carryin; /* compute the sum and carry */ assign p = a | b; endmodule module carryskip(a,b,carryin,sum,carryout); input [7:0] a, b; /* add these bits */ input carryin; /* carry in*/ output [7:0] sum; /* result */ output carryout; wire [8:1] carry; /* transfers the carry between bits */ wire [7:0] p; /* propagate for each bit */ wire cs4; /* final carry for first group */ 21 fulladd_p a0(a[0],b[0],carryin,sum[0],carry[1],p[0]);
• 22. fulladd_p a1(a[1],b[1],carry[1],sum[1],carry[2],p[1]); fulladd_p a2(a[2],b[2],carry[2],sum[2],carry[3],p[2]); fulladd_p a3(a[3],b[3],carry[3],sum[3],carry[4],p[3]); assign cs4 = carry[4] | (p[0] & p[1] & p[2] & p[3] & carryin); fulladd_p a4(a[4],b[4],cs4, sum[4],carry[5],p[4]); fulladd_p a5(a[5],b[5],cs4, sum[5],carry[6],p[5]); fulladd_p a6(a[6],b[6],cs4, sum[6],carry[7],p[6]); fulladd_p a7(a[7],b[7],cs4, sum[7],carry[8],p[7]); assign carryout = carry[8] | (p[4] & p[5] & p[6] & p[7] & cs4);endmodule 22
• 23. Fig 192.5)Carry save adder:-when n bit adder is implemented, still carry is rippled tothe next stage, of same row, even though inputs to the lower next stage is ready,but kept in wait state, until the sum and carry output didn’t come from the abovestage. This induces delay, now it can be optimized, if carry out is passed diagonallyto the lower next stage,instead of rippling to the next stage of same row. Carrycomputation is not performed, but it is saved upto last row ,where the results areobtained finally, in the last bottom row, carry is rippled however, but itsignificantly reduce the amount of delay occurred due to rippling operation.2.51)Design:-2.52)Pros and Cons:- This adder is used in array multiplier ,delay is reducedsignificantly compared to ripple carry adder, for n*n multiplier delay elapsed when 23ripple carry adders are used in 2n,where as if carry save adders are used worst casedelay is n+3 units. carry save adders are used in binary tree adders also.
• 24. 2.6)Binary tree adder:-Understanding binary tree adder requires concepts ofgroup PG logic ,which is explained below.2.61)Group PG logic:- The sum and carry expression for full adder in terms ofpropagate and generate signal are written asSum=ai XOR bi XOR CiCarry out=Gi+Pi.Ci, where Pi=ai XOR bi and Gi=ai.bi.Also for n bit adder carry out for nth stage(let here n=4) is given asC3=G3+P3G2+P3G2G1+P3P2P1G0+P3P2P1PoCinWe can write P=PoP1P2P3 and G= G3+P3G2+P3G2G1+P3P2P1G0Hence C3=G+PCin2.62)This concept is used in tree adder shown below 24 Fig 20