System-on-Chip Design, Embedded System Design Challenges

System-on-Chip Design Embedded System Design Challenges Pierre Boulet – DaRT project-team Master recherche informatique 2009–2010

Embedded System Design Challenges Deﬁnition and Signiﬁcance System-on-Chip Today Main Challenges on Design Some Answers Overview of the Course

Deﬁnition What is an embedded system? system set of components needed to perform a function hardware + software + ... embedded main function not computing usually not autonomous usually computer inside a system speciﬁc purpose submitted to constraints

Examples very small electronic tags smartcards microcontrollers washing machine, microwave oven, ... computer peripherals keyboard hard drive controller more complex controllers digital camera automotive air bags, ABS, ... ESB, engine control, ...

Examples – continued communications mobile phones network routers, modems software radio multimedia set-top boxes cable, satellite TV HDTV, DVD players video games radar, sonar

Market Signiﬁcance huge market global embedded systems market (2009): 88,144 M$ average annual growth rate (2009): 14 % embedded software global embedded systems market (2009): 3,448 M$ average annual growth rate (2009): 16 %

term Years,” and at three-year (node) intervals thereafter, called the “Long-term years” (2012, 2015, 2018), while Technology Trends retaining the previous 2001 ITRS long-term columns for ease of comparison and to retain the tracking of the three-year cycle nodes. 2003 ITRS Technology Trends - 1/2 Pitch 1000 DRAM 1/2 Pitch - Node Technology Node - DRAM Half-Pitch (nm) MPU M1 1/2 Pitch 100 hp90 2-year Node Cycle hp65 hp45 hp32 3-year Node Cycle hp22 10 1 1995 2000 2005 2010 2015 2020 Year 2003 ITRS Period: Near-term: 2003-2009; Long-term: 2010-2018 Figure 7 2003 ITRS—Half Pitch Trends

Generations 46 Overall Roadmap Technology Characteristics Table 1i High-Performance MPU and ASIC Product Generations and Chip Size Model—Near-term Years Year of Production 2003 2004 2005 2006 2007 2008 2009 Technology Node hp90 hp65 DRAM ½ Pitch (nm) 100 90 80 70 65 57 50 MPU/ASIC Metal 1 (M1) ½ Pitch (nm) 120 107 95 85 76 67 60 MPU/ASIC ½ Pitch (nm) (Un-contacted Poly) 107 90 80 70 65 57 50 MPU Printed Gate Length (nm) †† 65 53 45 40 35 32 28 MPU Physical Gate Length (nm) 45 37 32 28 25 22 20 Logic (Low-volume Microprocessor) High-performance ‡ Generation at production ** p03h -- p05h -- p07h -- p09h Functions per chip (million transistors) 439 553 697 878 1,106 1,393 1,756 2 Chip size at production (mm ) §§ 310 310 310 310 310 310 310 2 High-performance MPU Mtransistors/cm at production 142 178 225 283 357 449 566 (including on-chip SRAM) ‡ ASIC 2 ASIC usable Mtransistors/cm (auto layout) 142 178 225 283 357 449 566 2 ASIC max chip size at production (mm ) (maximum 572 572 572 572 572 572 572 lithographic field size) ASIC maximum functions per chip at production 810 1,020 1,286 1,620 2,041 2,571 3,239 (Mtransistors/chip) (fit in maximum lithographic field size)

Design Productivity Gap n Reuse er / day Moore’s Engineering Law Productivity Productivity Gap Design Reuse System Verification Logic Synthesis Behavioral Compilers Schematic Capture 1980 1990 2000 2010 e productivity gap he opportunity to define a Conclusion

System-on-Chip deﬁnition (nearly) complete embedded system on a single chip usualy includes programmable processors memory accelerating function units I/O software

Technology Integration 4 System Drivers Figure 9 First Integration of Technologies in SOC with Standard CMOS Process SOC MULTI-TECHNOLOGY The need to build heterogeneous systems on a single chip is driven by such considerations as cost, form-factor, connection speed/overhead, and reliability. Thus, process technologists seek to meld CMOS with MEMS, and other sensors. Process complexity is a major factor in the cost of SOC-MT applications, since more technologies assembled on a single chip requires more complex processing. The total cost of processing is difficult to predict for future new materials and combinations of processing steps. However, at present cost considerations limit the number of technologies on a given SOC: processes are increasingly modular (e.g., enabling a flash add-on to a standard low-power logic process), but the modules are not generally “stackable”. Figure 9 shows how first integrations of each technology within standard CMOS processes—not necessarily together with other technologies, and not necessarily in volume production—might

SoC Examples Canon Digic processor family image processor improved quality, power consumption, speed, cost STI Cell Sony+Toshiba+IBM aim at several TFlops at 65nm integration one PowerPC + 8 SIMD units TI OMAP platform dedicated to 2.5G and 3G mobile phones / PDA

STI Cell http: //www.blachford.info/computer/Cell/Cell0_v2.html

OMAP 9 Typical application using the OMAP1612 device TNETw1130 Compact NAND GPS Fast FLASH FLASH IrDA Emulator Pod FLASH JTAG/ High Speed WLAN EMIF/CF UART/IrDA I2C I 2C Peripheral Emulation a/b/g Debug Messaging I/F Keypad Keypad Mobile Serial DDR OMAP1612 GPIO GPIO LPG LED BRF6100 LPG LED Bluetooth™ Data UART TMS320C55x™ ARM926 DSP Voice PWT Buzzer MCSI Debugger EMT9 Shared Memory Controller/DMA CMOS Camera I/F Sensor Voice 2D Graphic Accelerator TCS4105 MCSI Memory Stick Memory Stick Card, TCS2100 MMC-SD MMC-SD Card TCS2010 Control Modem UART Timers, Interrupt Controller, RTC Memory Stick Memory Stick Card, Chipset MMC-SD MMC-SD Card Data HDQ/1Wire McBSP Frame Buffer/Internal SRAM (2 MBit) Battery 12 MHz Security: SHA-1/MD5 DES/3DES RNG Clock and 32 kHz LCD Reset Mgt. Reset µWire McBSP USB OTG Controller PWL TSC2301TLC320AIC23 Client Host Liquid LCD Audio CodecAudio Crystal Light Touch Screen Controller Codec Display Controller Audio Amplifier In/Out Audio ARM Peripherals Baseband Peripherals Shared ARM and DSP Peripherals Dedicated Ports

• Layout densities for memory and logic fabrics are the same as for the MPU driver, with eDRAM density assumed to be 3× SRAM density. Requirements for PDA SOC-LP • Maximum on-chip clock frequency is approximately 5–10% of the MPU clock frequency at each node. Peak power dissipation is limited to 0.1 W at 1000C, and standby power to 2.1 mW, due to battery life. Table 9 System Functional Requirements for the PDA SOC-LP Driver YEAR OF PRODUCTION 2003 2006 2009 2012 2015 2018 Process Technology (nm) 101 90 65 45 32 22 Supply Voltage (V) 1.2 1 0.8 0.6 0.5 0.4 Clock Frequency (MHz) 300 450 600 900 1200 1500 Application (maximum required Still Image Real Time Video Codec Real Time Interpretation performance) Processing (MPEG4/CIF) Application (other) Web Browser TV Telephone (1:1) TV Telephone (>3:1) Voice Recognition Electric Mailer Voice Recognition (Input) (Operation) Authentication (Crypto Scheduler Engine) Processing Performance (GOPS) 0.3 2 14 77 461 2458 Required Average Power (W) 0.1 0.1 0.1 0.1 0.1 0.1 Required Standby Power (mW) 2 2 2 2 2 2 Battery Capacity (Wh/Kg) 120 200 200 400 400 400 SOC TRENDS SOC presents Design, Test, PIDS and other areas with a number of technology challenges, such as development of reusable analog IP. The most daunting SOC challenges are: • design productivity improvement of > 100% per node, with needs including platform-based design7 and integration of programmable logic fabrics (Design),8 • management of power especially for low-power, wireless, multimedia applications (Design, PIDS), • system-level integration of heterogeneous technologies including MEMS and optoelectronics (PIDS, FEP, Design), and • development of SOC test methodology, with needs including test reusability and analog/digital BIST. Since SOC is aimed at low-cost and rapid system implementation, and since power is one of the grand challenges in

Technology Challenges for SoC Design design productivity increase main challenge need >100% increase per technology node management of power especially for low-power, wireless, multimedia applications system-level integration of heterogeneous technologies development of SoC test methodology

Design Productivity Growth Target Design Freedom 100% of Design Productivity Improvement 90% 12.00 80% 10.00 70% New Circuit Rat io Reuse Circuit Rat io Target Design Resour ce 60% 8.00 50% 6.00 40% 30% 4.00 20% 2.00 10% 0% - 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% M e mor y P e r c e n t a ge

Insufficient (42% Per Node) Design Produc Logic vs Memory with Different Rates of Productivity Improvement 100% 90% 90% 80% 80% 70% 70% 60% Logic Area Content (%) 60% 50% 50% Prod. 10% per node 40% Prod. 50% per node 40% Prod. 100% per node 30% 30% Prod. 200% per node 20% 20% 10% 10% 0% 0% 0% 10% 1999 2002 2005 2008 2011 2014 Year

SoC Design Cost Model 2 Design $ 1 0 0 ,0 0 0 , 0 0 0 , 0 0 0 IC Implementation tools Very Large Block Reuse ES Level Methodology Tall Thin Engineer Small Block Reuse Large Block Reuse Intelligent Testbench In house P&R $ 1 0 ,0 0 0 , 0 0 0 , 0 0 0 $ 1 ,0 0 0 , 0 0 0 , 0 0 0 Total Design Cost 6 2 9 ,7 6 9 , 2 7 3 $100,000,000 20 , 1 52 , 6 17 R T L M e t h o d o lo g y O n ly W it h A ll F u tu r e I m p r o v e m e n ts $10,000,000 198 5 1990 1995 2000 2005 2010 20 15 2020 Y ear Figure 13 Impact of Design Technology on SOC LP-PDA Implementation Cost This chapter first presents silicon complexity and system complexity challenges, followed by five crosscutting challenges (productivity, power, manufacturing integration, interference, and error tolerance) that permeate all DT areas. The bulk of the chapter then sets out detailed challenges according to a traditional landscape of DT areas (see Figure 14): design 1 process; system-level design; logical, circuit and physical design; design verification; and design test. These challenges are discussed at a level of detail that is actionable by management, R&D, and academia in the target supplier community,

Design Cost Problem economy will limit the semiconductor industry before the end of Moore’s law today design time 30% design 70% veriﬁcation/test

Complexity Challenge silicon complexity impact of process scaling and new materials and architectures previously ignorable phenomena now have impact system complexity reuse veriﬁcation and test cost-driven design optimization embedded software design reliable implementation platforms design process management together: superexponentially increasing complexity of the design process

Methodology Precepts ITRS exploit reuse evolve rapidly avoid iteration replace veriﬁcation by prevention improve predictability orthogonalize concerns expand scope unify

Reuse IP IP = Intellectual Property HW or SW block designed for reuse need of standards (VSIA) platform based SoC design organized method to reduce cost and risk by heavy reuse of HW and SW IPs steps in reuse block → IP → integration architecture

Raising the Abstraction Level ESL (Electronic System Level) from RTL to TLM or higher from VHDL to SystemC to UML HW/SW co-design need new tools consider the whole system large optimization potential combination of formal, semi-formal and non formal techniques

Figure 10 shows the “bottom-up” lower bound for total chip power at an operating temperature of 100°C, assuming that Other Problem: Power all logic is implemented with LOP or LSTP devices and operates as described in Footnote 25. We say that this is a lower bound since in practice some logic would need to be implemented with faster, higher-current devices. The figure suggests that SOC-LP power levels will exceed the low-power requirements of the PDA application, and further provides a Consumption breakdown of power contributions for each case. As expected, LOP power is primarily due to standby power dissipation while LSTP power is primarily due to dynamic power dissipation10. Total chip power using only LOP devices reaches 1.39 W in 2018, mostly due to a sharp rise in static power after 2012. Total chip power using only LSTP devices reaches Lower Bound for Fixed Chip Size 1.27 W in 2018; almost all of this is dynamic power. 1.60 Power Trend 1.40 - Dynamic Power LOP (W) 1.20 - Dynamic Power LSTP (W) 1.00 - Static Power LOP (W ) - Static Power LSTP (W) Power (W) 0.80 - Memory Power LOP (W) - Memory Power LSTP (W) 0.60 - Power for LOP Bottom-Up (W) 0.40 - Power for LSTP Bottom-Up (W ) 0.20 0.00 2003 2006 2009 2012 2015 2018 Year

Power Consumption power consumption model αCVdd 2 f + Ioff Vdd necessary improvement of power management (in 2016) reduction by 20 for dynamic power reduction by 800 for standby power one possible direction: exploit parallelism allows to decrease f and thus decrease Vdd

Summary challenge of SoC design more complex faster cheaper more reliable with lower power consumption how to handle the complexity?

References International Technology Roadmap for Semiconductors http://public.itrs.net/ HiPEAC (European Network of Excellence on High Performance and Embedded Architecture and Compilation) Roadmap http://wwww.hipeac.net/roadmap Winning the SoC Revolution Experiences in Real Design Edited by Grant Martin & Henry Chang Kluwer Academic Publishers

Course Outline Embedded System Design Challenges (Pierre Boulet), 21 sept Codesign (Jean-Luc Dekeyser), 5 oct DaRT (Jean-Luc Dekeyser), 12 oct Models of Computation (Pierre Boulet), 19 oct MARTE UML proﬁle (Pierre Boulet), 26 oct SystemC Simulation (Jean-Luc Dekeyser et Rabïe ben Atitallah), 2 nov Validation (Abdoulaye Gamatié), 9 nov Model Driven Engineering (Anne Étien), 16 nov Applications (Jean-Luc Dekeyser et Frédéric Guyomarc’h), 23 nov VHDL Synthezis (Philippe Marquet), 30 nov

Course Evaluation study of the research trends of some research teams choice of the team ﬁrst report refereeing ﬁnal report exam

System-on-Chip Design, Embedded System Design Challenges

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