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Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems
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Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems

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  • 1. Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems Paul Pop Sept. 29, 2006
  • 2. General purpose vs. special purpose Embedded system
  • 3. Embedded Systems
  • 4. Automotive Electronics
  • 5. Automotive Electronics, cont. 90% of innovations are based on embedded systems 8.9 Market ($billions) 10.5 13.1 14.1 15.8 17.4 19.3 21.0 0 200 400 600 800 1000 1200 1400 1998 1999 2000 2001 2002 2003 2004 2005
  • 6. Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems Paul Pop Sept. 29, 2006
  • 7. Architecture
  • 8. Heterogeneous Platform <ul><li>Hardware architecture </li></ul>... ... ... I/O Interface Comm. controller CPU RAM ROM ASIC <ul><li>Software architecture </li></ul>
  • 9. Sources of Heterogeneity <ul><li>Scheduling policies </li></ul><ul><li>Static cyclic scheduling </li></ul><ul><li>Fixed-priority preemptive scheduling </li></ul><ul><li>Earliest deadline first </li></ul><ul><li>Communication protocols </li></ul><ul><li>Controller area network </li></ul><ul><li>FlexRay </li></ul><ul><li>Time-triggered protocol </li></ul><ul><li>Fault-tolerance techniques </li></ul><ul><li>Replication (HW, SW) </li></ul><ul><li>Re-execution </li></ul><ul><li>Checkpointing </li></ul>
  • 10. Platform Example <ul><li>Distributed application </li></ul><ul><li>TTP Time Triggered Protocol </li></ul><ul><li>CAN Controller Area Network </li></ul><ul><li>FPS Fixed-Priority Preemptive Scheduling </li></ul><ul><li>SCS Static Cyclic Scheduling </li></ul>CAN TTP FPS SCS SCS SCS SCS FPS FPS Schedulable? Analysis approaches to answer this question If NOT? Optimization approaches for automatic implementation REX Re-Execution HWR Hardware Replication CHK Checkpointing REX CHK HWR
  • 11. Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems Paul Pop Sept. 29, 2006
  • 12. Embedded Software Development <ul><li>Design and build the target hardware </li></ul><ul><li>Develop the software independently </li></ul><ul><li>Integrate them and hope it works </li></ul>Does not work for complex projects
  • 13. System-Level Design <ul><li>Mapping and scheduling </li></ul><ul><li>Fault-tolerance/ scheduling policy assignment </li></ul><ul><li>Communication synthesis </li></ul><ul><li>Schedulability analysis </li></ul><ul><li>Communication delay analysis </li></ul><ul><li>Heterogeneous/mixed </li></ul><ul><li>Incremental design </li></ul><ul><li>Safety critical </li></ul><ul><li>Complex functionality </li></ul>Model of system implementation System platform model System-level design tasks Analysis Software synthesis Hardware synthesis Application model
  • 14. Mapping <ul><li>Given </li></ul><ul><ul><li>Application: set of interacting processes </li></ul></ul><ul><ul><li>Platform: set of nodes </li></ul></ul><ul><li>Assessment </li></ul><ul><ul><li>Optimal solutions even for large problem sizes </li></ul></ul>N 1 N 2 P 1 P 4 P 2 P 3 m 1 m 2 m 3 m 4 P 1 P 4 P 2 P 3 m 1 m 2 m 3 m 4 <ul><li>Determine </li></ul><ul><ul><li>Mapping of processes to nodes </li></ul></ul><ul><ul><ul><li>Such that the communication is minimized </li></ul></ul></ul>
  • 15. Mapping and Scheduling <ul><li>Given </li></ul><ul><ul><li>Application: set of interacting processes </li></ul></ul><ul><ul><li>Platform: set of nodes </li></ul></ul><ul><ul><li>Timing constraints: deadlines </li></ul></ul><ul><li>Determine </li></ul><ul><ul><li>Mapping of processes and messages </li></ul></ul><ul><ul><li>Schedule tables for processes and messages </li></ul></ul><ul><ul><ul><li>Such that the timing constraints are satisfied </li></ul></ul></ul>S 2 S 1 P 1 P 4 P 2 m 1 m 2 m 3 m 4 P 3 N 1 N 2 Bus Schedule table Deadline P 1 P 4 P 2 P 3 m 1 m 2 m 3 m 4 N 1 N 2
  • 16.  Assessment <ul><li>Scheduling is NP-complete even in simpler context </li></ul><ul><ul><li>D. Ullman, “NP-Complete Scheduling Problems”, Journal of Computer Systems Science, volume 10, pages 384–393, 1975. </li></ul></ul><ul><li>CP/MIP formulations </li></ul><ul><ul><li>Can’t obtain optimal solutions for large problem sizes </li></ul></ul><ul><li>Alternative: divide the problem </li></ul><ul><ul><li>Scheduling </li></ul></ul><ul><ul><ul><li>Heuristic: List scheduling </li></ul></ul></ul><ul><ul><li>Mapping </li></ul></ul><ul><ul><ul><li>Simulated annealing </li></ul></ul></ul><ul><ul><ul><li>Tabu-search </li></ul></ul></ul><ul><ul><ul><li>Problem-specific greedy algorithms </li></ul></ul></ul>
  • 17. Holistic Analysis and Optimization of Heterogeneous Fault-Tolerant Embedded Systems Paul Pop Sept. 29, 2006
  • 18. <ul><li>C. Constantinescu, Trends and Challenges in VLSI Circuit Reliability, IEEE Mirco, 23(4), 14-19, 2003 </li></ul>Permanent vs. Transient Faults Transient faults are increasing Permanent faults are decreasing
  • 19. Fault-Tolerant Mapping and Scheduling Messages: Schedule tables Messages: Fault-tolerant protocol Processes: Schedule tables ... TDMA bus: TTP Transient faults Processes: Re-execution and replication
  • 20. Example Problem, cont. <ul><li>Given </li></ul><ul><ul><li>Fault model </li></ul></ul><ul><ul><ul><li>Number of transient faults in the system period </li></ul></ul></ul><ul><ul><li>System architecture </li></ul></ul><ul><ul><li>Application </li></ul></ul><ul><ul><ul><li>WCETs, message sizes, periods, deadlines </li></ul></ul></ul><ul><li>Determine </li></ul><ul><ul><li>Schedulable and fault-tolerant design implementation </li></ul></ul><ul><ul><ul><li>Mapping of processes and messages </li></ul></ul></ul><ul><ul><ul><li>Schedule tables for processes and messages </li></ul></ul></ul><ul><ul><ul><li>Fault-tolerance policy assignment </li></ul></ul></ul>Application : set of process graphs Architecture : time-triggered system Fault-model : transient faults
  • 21. Fault-Tolerant Techniques P 1 P 1 P 1 Re-execution N 1 P 1 P 1 P 1 Replication N 1 N 2 N 3 P 1 P 1 N 1 N 2 P 1 Re-executed replicas 2
  • 22. Re-execution vs. Replication A 1 Replication is better Re-execution is better N 1 N 2 P 1 P 3 P 2 m 1 1 P 1 P 2 P 3 N 1 N 2 40 50 40 60 50 70 N 1 N 2 TTP P 1 P 2 S 1 S 2 P 3 Met N 1 N 2 TTP P 1 P 2 P 3 S 1 S 2 Missed P 1 N 1 N 2 TTP P 1 P 2 P 2 P 3 P 3 S 1 S 2 m 1 m 1 m 2 m 2 Deadline Met P 1 P 3 P 2 m 1 m 2 A 2 P 1 S 1 N 1 N 2 TTP P 1 S 2 P 2 P 2 P 3 P 3 Deadline Missed m 1 m 1
  • 23. Fault-Tolerant Policy Assignment P 1 N 1 N 2 TTP P 2 P 3 S 1 S 2 P 4 m 2 Missed P 1 P 2 P 3 N 1 N 2 40 50 60 60 80 80 P 4 40 50 1 N 1 N 2 P 1 P 4 P 2 P 3 m 1 m 2 m 3 P 1 N 1 N 2 TTP P 2 P 3 S 1 S 2 m 2 P 4 N 1 N 2 P 1 P 3 S 1 S 2 P 4 P 2 P 1 m 1 m 1 TTP m 2 m 2 P 2 m 3 m 3 P 3 P 4 Missed P 1 N 1 N 2 TTP P 2 P 3 S 1 S 2 m 2 P 4 No fault-tolerance: application crashes N 1 N 2 P 1 P 3 S 1 S 2 P 4 P 2 P 1 m 2 m 1 TTP Met Optimization of fault-tolerance policy assignment Deadline
  • 24. Optimization Strategy <ul><li>Design optimization: </li></ul><ul><ul><li>Fault-tolerance policy assignment </li></ul></ul><ul><ul><li>Mapping of processes and messages </li></ul></ul><ul><ul><li>Schedule tables </li></ul></ul><ul><li>Three tabu-search optimization algorithms: </li></ul><ul><ul><li>Mapping and Fault-Tolerance Policy assignment ( MRX ) </li></ul></ul><ul><ul><ul><li>Re-execution, replication or both </li></ul></ul></ul><ul><ul><li>Mapping and only Re-Execution ( MX ) </li></ul></ul><ul><ul><li>Mapping and only Replication ( MR ) </li></ul></ul>Tabu-search List scheduling
  • 25. Experimental Results 80 20 0 10 30 40 50 60 70 90 100 20 40 60 80 100 Mapping and policy assignment ( MRX ) Number of processes Avgerage % deviation from MRX Schedulability improvement under resource constraints 80 <ul><ul><li>Mapping and replication ( MR ) </li></ul></ul>20 <ul><ul><li>Mapping and re-execution ( MX ) </li></ul></ul><ul><li>Case study </li></ul><ul><ul><li>Vehicle cruise controller </li></ul></ul><ul><ul><li>MRX: schedulable fault-tolerant application with 65% overhead </li></ul></ul>
  • 26. Future Research <ul><li>Analysis and optimization of embedded systems </li></ul><ul><ul><li>Fault-tolerant systems </li></ul></ul><ul><ul><li>Mixed hard/soft systems </li></ul></ul><ul><li>System-level design of Systems-on-a-Chip </li></ul><ul><ul><li>Fault-tolerance and low power </li></ul></ul><ul><ul><li>Timing analysis </li></ul></ul><ul><li>Design of Labs-on-a-Chip </li></ul><ul><ul><li>Micro-fluidics </li></ul></ul>

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