CHAPTER - 1
The junction gate field-effect transistor (JFET or JUGFET) is the simplest type of field-effect
transistor. It can be used as an electronically-controlled switch or as a voltage-
controlledresistance. Electric charge flows through a semiconducting channel between "source"
and "drain" terminals. By applying a reverse bias voltage to a "gate" terminal, the channel is
"pinched", so that the electric current is impeded or switched off completely.
The field-effect transistor (FET) relies on an electric field to control the shape and hence
the conductivity of a channel of one type of charge carrier in a semiconductormaterial. FETs are
sometimes called unipolar transistors to contrast their single-carrier-type operation with the
dual-carrier-type operation of bipolar (junction) transistors (BJT). The concept of the FET
predates the BJT, though it was not physically implemented until after BJTs due to the
limitations of semiconductor materials and the relative ease of manufacturing BJTs compared to
FETs at the time.
The principle of field-effect transistors was first patented by Julius Edgar Lilienfeldin 1925 and
by Oskar Heil in 1934, but practical semi-conducting devices (the JFET, junction gate field-
effect transistor) were only developed much later after thetransistor effect was observed and
explained by the team of William Shockley at Bell Labs in 1947. The MOSFET (metal–oxide–
semiconductor field-effect transistor), which largely superseded the JFET and had a more
profound effect on electronic development, was first proposed by Dawon Kahng in 1960
However it was during the 1940s at Bell Laboratories that real progress towards the field effect
transistor or FET was made. At this time they set up a semiconductor research group that
investigated a number of areas pertaining to semiconductors, one of which was a device that
would modulate the current flowing in a semiconductor channel buy placing an electric field
close to it.
Unfortunately the idea for the field effect transistor did not work initially and even after repeated
attempts to discover the cause of the problem no progress was made. As a result this failure the
group investigating this device turned their sights in other directions and ultimately invented the
bipolar transistor in 1948.
After the discovery of the bipolar transistor much of the semiconductor research was focused on
improving this device, and the idea for the field effect transistor was not fully investigated for
One of the main reasons why the idea for the field effect transistor did not work initially was that
the materials could not be refined sufficiently. However as work progressed on
improvingsemiconductor materials for the bipolar transistor, this also enabled work to proceed
with the field effect transistor. This resulted in the successful implementation of the field effect
transistor or FET, and gained widespread acceptance during the 1960s when these devices
became more widely available.
Transistors play an integral part in our everyday lives. We may encounter billions of transistors
every day. Without these devices, modern computing would not be possible. Since their
inception, we have moved from somewhat large and bulky vacuum tube triodes, to transistors so
small that hundreds of them can be fit onto a single red blood cell. The importance of these
devices in our everyday lives is profound. Nearly every single digital device relies on transistors
in some way. In order to appreciate the importance of these devices, it is essential to understand
The JFET is a long channel of semiconductor material, doped to contain an abundance of
positive charge carriers or holes (p-type), or of negative carriers or electrons (n-type). Ohmic
contacts at each end form the source (S) and drain (D). A pn-junction is formed on one or both
sides of the channel, or surrounding it, using a region with doping opposite to that of the channel,
and biased using an ohmic gate contact (G).
1.2 WHY SHRINK TRANSISTORS?
While smaller transistors certainly allow for more processing power in a smaller area, the other
benefits may not be as obvious. Currently, the typical computer processor is only a couple of
square inches. In order to increase performance, more transistors are desirable. An obvious,
albeit ineffective solution to this problem is to simply make the chips larger.
However, the increased cost associated with producing larger chips is less desirable than fitting
transistors more efficiently on the chip. Also, the smaller the transistor, the quicker it can be
switched between states, as they are handling a smaller amount of charge. That is, there is a
direct relation between central processing unit (CPU) clock
1.3Basic JFET structure and circuit symbols:-
There are two types of field-effect transistors, the JunctionField-Effect Transistor (JFET) and the
―Metal-OxideSemiconductor‖ Field-Effect Transistor (MOSFET), orInsulatedGate Field-Effect
Transistor (IGFET). Theprinciples on which these devicesoperate (current controlledby an
electric field) are very similar — the primary differencebeing in the methods by which the
control element is made.This difference, however, results in a considerable differencein device
characteristics and necessitates variances in circuit design.
Fig1.3 Simple FET Structure
Basically a field effect transistor or FET consists of a section of silicon whose conductance is
controlled by an electric field. The section of silicon through which the current flows is called
the channel, and it consists of one type of silicon, either N-type or P-type.
The JFET gate is sometimes drawn in the middle of the channel (instead of at the drain or source
electrode as in these examples). This symmetry suggests that "drain" and "source" are
interchangeable, so the symbol should be used only for those JFETs where they are indeed
Officially, the style of the symbol should show the component inside a circle (representing the
envelope of a discrete device). This is true in both the US and Europe. The symbol is usually
drawn without the circle when drawing schematics of integrated circuits. More recently, the
symbol is often drawn without its circle even for discrete devices.
In every case the arrow head shows the polarity of the P-N junction formed between the channel
and gate. As with an ordinary diode, the arrow points from P to N, the direction of conventional
current when forward-biased. An English mnemonic is that the arrow of an N-channel device
Fig 1.3.1(A) n-channel JFET (B) p-channel JFET
All FETs have a gate, drain, and source terminal that correspond roughly to the base, collector,
and emitter of BJTs. Aside from the JFET, all FETs also have a fourth terminal called
the body, base, bulk, or substrate. This fourth terminal serves to biasthe transistor into operation;
it is rare to make non-trivial use of the body terminal in circuit designs, but its presence is
important when setting up the physical layout of an integrated circuit. The size of the gate,
length L in the diagram, is the distance between source and drain. The width is the extension of
the transistor, in the diagram perpendicular to the cross section. Typically the width is much
larger than the length of the gate. A gate length of 1 µm limits the upper frequency to about
5 GHz, 0.2 µm to about 30 GHz.
The names of the terminals refer to their functions. The gate terminal may be thought of as
controlling the opening and closing of a physical gate. This gate permits electrons to flow
through or blocks their passage by creating or eliminating a channel between the source and
drain. Electrons flow from the source terminal towards the drain terminal if influenced by an
applied voltage. The body simply refers to the bulk of the semiconductor in which the gate,
source and drain lie. Usually the body terminal is connected to the highest or lowest voltage
within the circuit, depending on type. The body terminal and the source terminal are sometimes
connected together since the source is also sometimes connected to the highest or lowest voltage
within the circuit, however there are several uses of FETs which do not have such a
configuration, such as transmission gates and cascadecircuits.
As it is only the electric field that controls the current flowing in the channel, the device is said to
be voltage operated and it has high input impedance, usually many mega ohms. This can be a
distinct advantage over the bipolar transistor that is current operated and has much lower input
The JFET is a long channel of semiconductor material, doped to contain an abundance of
positive charge carriers or holes (p-type), or of negative carriers or electrons (n-type). Ohmic
contacts at each end form the source (S) and drain (D). A pn-junction is formed on one or both
sides of the channel, or surrounding it, using a region with doping opposite to that of the channel,
and biased using an ohmic gate contact (G).
JFET operation is like that of a garden hose. The flow of water through a hose can be controlled
by squeezing it to reduce the cross section; the flow ofelectric charge through a JFET is
controlled by constricting the current-carrying channel. The current also depends on the electric
field between source and drain (analogous to the difference in pressure on either end of the
Fig.1.3.2 p-channel JFET
Construction of the conducting channel is accomplished using the field effect: a voltage between
the gate and source is applied to reverse bias the gate-source pn-junction, thereby widening
the depletion layer of this junction (see top figure), encroaching upon the conducting channel and
restricting its cross-sectional area. The depletion layer is so-called because it is depleted of
mobile carriers and so is electrically non-conducting for practical purposes.
1.4Types of JFET:-
A transistor is a linear semiconductor device that controls current with the application of a lower-
power electrical signal. Transistors may be roughly grouped into two major divisions: bipolar
and field-effect. In the last chapter we studied bipolar transistors, which utilize a small current to
control a large current. In this chapter, we'll introduce the general concept of the field-effect
transistor -- a device utilizing a small voltage to control current -- and then focus on one
particular type: the junction field-effect transistor. In the next chapter we'll explore another type
of field-effect transistor, the insulated gate variety.
1.4.1 N-Channel JFET:-
All field-effect transistors are unipolar rather than bipolar devices. That is, the main current
through them is comprised either of electrons through an N-type semiconductor or holes through
a P-type semiconductor. This becomes more evident when a physical diagram of the device is
Fig 1.4 n-channel JFET
1.4.2 P-Channel JFET
In a junction field-effect transistor, or JFET, the controlled current passes from source to drain or
from drain to source as the case may be. The controlling voltage is applied between the gate and
source. Note how the current does not have to cross through a PN junction on its way between
source and drain: the path (called achannel) is an uninterrupted block of semiconductor material.
In the image just shown, this channel is an N-type semiconductor. P-type channel JFETs are also
Fig 1.4.a p-channel JFET
1.5 Basics of FET:
JFETs are known as depletion mode devices because the channel conducts with zero biasvoltage
applied (i.e. the depletion region has zero width). Applying a reverse biasincreases the width of
the depletion region which in turn reduces the conduction of thechannel. This is the basis for
making an amplifier. The channel conduction resembles are resistor for low voltage drops
(ohmic region) and becomes a constant current for highervoltage drops (saturation region). The
mathematical models we use are based on thesaturation region and will provide incorrect results
if used in the ohmic region. Themodel for a field effect transistor is a voltage controlled current
source. Many JFETs areso symmetrical in their construction that it makes little if any difference
if the source anddrain terminals are swapped.
Fig.1.5 JFET Structure
Fig1.5.a I-V Characteristics and output plot of a JFET n-channel
There are two channel types of JFETs. One type is n-channel and the other type is pchannel.Both
types operate exactly the same way but the terminal voltages and currents are inverted. The main
feature of JFETs is extremely high input resistance –usually at least severalhundred mega ohms.
This feature enables the power gain of a JFET amplifier to be huge.
1.6 Development of analytic equations for JFET bias condition:
The following discussion is about n-channel JFETs. P-channel JFETs operate the sameway
except that the polarity of the terminal voltages and currents is inverted. There aretwoparameters
that describe the operation of a JFET:IDSSis the drain saturation current at VGS= 0.VP is the
gate-source voltage, VGS, that causes the channel conduction to drop to zero(actually, the drain
current does not go all the way to zero but ceases to decreasebelow a very small current).IDSS
and VP have a rough proportional relationship.
A high IDSS generally has a highermagnitude VP. However, because the relationship is
dependent on the manufacturinggeometry of the JFET there is not a singular proportionality
constant. The interpretationof this is that for the spread of IDSS and VP provided on the data
sheet for a specific partthat low values of one parameter tend to correlate with low values of the
other parameter with the same holdingtrue for higher values. Some data sheets show a typical
plot of thisrelationship.
The drain current is zero when VGS = VP and is IDSS when VGS = 0. The relationship inthe
saturation region follows a square law as shown in Equation . For normal operation,VGSis biased
to be somewhere between VP and 0. Equation gives the approximatedrain current, ID, for a given
bias point. This approximation is generally good to withinabout ten percent and is theaccepted
equation for all JFET calculations.
ID = IDSS *sqrt [1 - (VGS/VP)]
Equation is valid only if the JFET is operating such that VGS is between 0 and VP andthat VDS is
greater than (VGS - VP) , i.e. the saturation region. Note that the drain current,ID, will be between
0 and IDSS. Figure 2 illustrates an example transfer function for aJFET that has an IDSS of 12
mAand a VP of -6 volts. The drain current will be less if thetransistor is operating in the ohmic
region. Although the transfer curve continues into thepositive bias region we do not normally
operate the JFET there except for very small signals discussion is for n-channel amplifiers.
Fig 1.6 Transfer Curve of a Typical JFET showing ID versus VGS
Wenormally operatethe JFET in the saturation region to the right of the dotted parabola curve
that separatesthe ohmic region from the saturation region. Note that that the dotted curve is
thesolution to VDS = (VGS –VP). In the ohmic region the device acts similarly to
avoltagecontrolled resistor and in the saturation region the device acts as a voltage
controlledcurrent source. The slight tilt of the lines in the saturation region is an extension of
themodel that includes the effective shunt resistance of the current source. That model is
notdiscussed here. All of the mathematics developed later assumes these lines are
perfectlyhorizontal. It should be noted that for VDS near zero volts (within plus or minus a
fewtenths of a volt at most) the channel acts as a voltage variable resistor that is linear
Fig.1.6.aFET Family Curves
This useful is desirable to have the solution to every possible permutation of known.
Voltage equation for FET is
VGS = VP * [1 -
Fig.1.6.bNormalized FET plot
VGS/VP = 1 –sqrt(ID/IDSS)
1.7 Development of gain equations for the JFET:-
Since the JFET is a voltage controlled current source, the gain is the change in draincurrent
divided by the change in gate voltage. This is called the transconductance gain(abbreviated as
gm) of the JFET and has units of conductance which is measured inSiemens. The gain value is
very low (typically between 0.0001 and 0.02 –but rememberthat what matters is power gain and
that is very high for a JFET) and is often expressed inmS.
The gain is found by taking the derivative of Equation 1 with respect to VGS.gm = |2The absolute
value is used because gm is always positive. This is done because signinformation is lost when
terms are squared as in Equation 1. The ratio, IDSS/VP, willalways be negative since VP is
negative for n-channel JFETS and IDSS is negative for pchannelJFET’S.Note from Equation 3
that gm is a linear function of VGS. When VGS is equal to VP (i.e. IDs zero) then gm is zero. When
VGS is equal to zero (i.e. ID = IDSS) then gm is at themaximum value. The maximum value of gm is
known as gmoand is obtained bysettingVGS to zero.
gmo= |2 * (IDSS/VP)|
At this point it should seem obvious that if high gain is desired then the JFET should bebiased as
close as practical to IDSS. gives us the ultimate gain possible. Equation gives us the gm if VGS
isknown. For some problems, ID is known instead.Although VGS can be calculated if ID is
known,it is convenient to have an equation thatdirectly gives us gm when ID is known.
gm = |2 * sqrt(ID * IDSS) /
gm= gmo* sqrt(ID/IDSS)
All three ways of computing gm give exactly the same answer. The one to use depends onwhat
the knowns at the moment are. It must be remembered that all of these equationsassume the
JFET is operating in the saturation region. They do not apply in the ohmicregion. The user must
always take care in using these equations. According to the NationalSemiconductor FET
Handbook (1977), that factor can range from about 1.1 to 2.5 but istypically near 2. Keep in
mind that we use a model of a JFET based on a simplifiedquadratic equation.
gm/gmo= 1 –VGS/VP
Fig 1.7.a Comparing ―Exact‖ versus Approximate JFET Models
1.8 Material Required:
The silicon-compatible material system encompasses, in addition to silicon itself, ahost of
materials commonlyused in the semiconductor integrated circuit industry.Normally deposited as
thin films, they include silicon oxides, silicon nitrides, andsilicon carbides, metals such as
aluminum, titanium, tungsten, and copper, andpolymers such as photoresist and polyimide.
Silicon is one of very few materials that is economically manufactured in singlecrystalsubstrates.
This crystalline nature provides significant electrical andmechanical advantages. The precise
modulation of silicon’s electrical conductivityusing impurity doping lies at the very core of the
operation of electronic semiconductordevices. Mechanically, silicon is an elastic and robust
material whosecharacteristics have been very well studied and documented.
Thetremendous wealth of information accumulated on silicon and its compounds overthe last
few decades has made it possible to innovate and explore new areas of applicationextending
beyond the manufacturing of electronic integrated circuits. Itbecomes evident that silicon is a
suitable material platform on which electronic, mechanical, thermal, optical, and even fluid-flow
functions can be integrated.
Ultrapure, electronic-grade silicon wafers available for the integrated circuit industryare common
today in MEMS. The relatively low cost of these substrates.Silicon as an element exists
withthree different microstructures: crystalline, polycrystalline, or amorphous. Polycrystalline,
orsimply ―polysilicon,‖ and amorphoussilicon are usually deposited as thin films with
typicalthicknesses below 5μm. Crystalline silicon substrates are commercially available
ascircular wafers with100-mm (4-in) and 150-mm (6-in) diameters.
Larger-diameter (200-mmand300-mm) wafers, used by the integrated circuit industry, are
currently economicallyunjustified for MEMS. Standard 100-mm wafers are nominally 525 μm
thick, and150-mm wafers are typically 650 μm thick. Double-side-polished wafers
commonlyused formicromachining on both sides of the wafer are approximately 100 μm
thinnerthan standard thickness substrates.
Visualization of crystallographic planes is key to understanding the dependenceof material
properties on crystal orientation and the effects of plane-selective etch solutions.Polysilicon is
animportant material in the integrated circuit industry and hasbeen extensively studied. Adetailed
description of its electrical properties is foundin. Polysilicon is an equally important and
attractive material for MEMS. Ithas been successfully used to make micromechanical structures
and to integrateelectrical interconnects, thermocouples, p-n junction diodes, and many other
electricaldevices with micromechanical structures.
The most notable example is theacceleration sensor available from Analog Devices, Inc., of
Norwood, Massachusetts, for automotive airbag safety systems. Surface micromachining based
on polysiliconis today a well-establishedtechnology for forming thin (a few micrometers)and
planar devices.The mechanical properties of polycrystalline and amorphous silicon vary
withdeposition conditions, but, by and large, they are similar to that of single crystal silicon.
Both normally haverelatively high levels of intrinsic stress.Beam structures made of
polycrystalline or amorphous silicon that have not beensubjected to acareful stress annealing step
can curl under the effect of intrinsicstress.
Silicon is a very good thermal conductor with a thermal conductivity greater thanthat of many
metals and approximately 100 times larger than that of glass. In complexintegrated systems, the
silicon substrate can be used as an efficient heat sink.This feature will be revisited when we
review thermal-based sensors and actuators.Unfortunately, silicon is not an active optical
material—silicon-based lasers donot exist. Because of the particular interactions between the
crystal atoms and theconduction electrons, silicon is effective only in detecting light; emission of
lightis very difficult to achieve. At infrared wavelengths above 1.1 μm,
Silicon istransparent, but at wavelengths shorter than 0.4 μm (in the blue and ultraviolet
portionsof the spectrum), it reflects over 60% of the incident light. Theattenuation depth of light
in silicon is 2.7 μm at 633nm (red) and 0.2 μm at 436 nm(blue-violet). The slight attenuation of
red light relative to other colors is what givesthin silicon membranes their translucent reddish tin
.Silicon is also well known to retain its mechanical integrity at temperatures up toabout 700°C.
At higher temperatures, silicon starts to soften and plastic deformationcan occur under load.
While the mechanical and thermal properties of polysiliconare similar to those of single crystal
silicon, polysilicon experiences slowstress annealing effects at temperatures above 250°C,
making its operation at elevatedtemperatures subject to long-term instabilities, drift, and
The surface of silicon oxidizes immediately upon exposure to the oxygen in air(referred to as
native oxide). The oxide thickness self-limits at a few nanometers atroom temperature.
CONSTRUCTION AND WORKING OF JFET:
2.1 Construction of JFET:
The construction of JFETs can be theoretically quite simple, but in reality difficult, requiring
very pure materials and clean room techniques. JFETs are made in different forms, some
being made as discrete (single) components and others, using planar technology as integrated
2.1.1 Diffusion JFET Construction:
Fig. 2.1.1 shows the (theoretically) simplest form of construction for a Junction FET (JFET)
using diffusion techniques. It uses a small slab of N type semiconductor into which are
infused two P type areas to form the Gate. Current (electrons) flows through the device from
source to drain along the N type silicon channel. As only one type of charge carrier
(electrons) carry current in N channel JFETs, these transistors are also called "Unipolar"
Fig. 2.1 JFET Planar Construction
2.1.2 Planar JFET Construction:
Fig.2.1 shows the cross section of a N channel planar Junction FET (JFET) The load current
flows through the device from source to drain along a channel made of N type silicon. In the
planar device the second part of the gate is formed by the P type substrate.
P channel JFETs are also available and the principle of operation is the same as the N
channel type described here, but polarities of the voltages are of course reversed, and the
charge carriers are holes
Fig 2.1.a p type Substrate
Fig 2.1.b JFET
2.2 JFET Operation:
Consider an n-channel JFET and refer to Fig.2.1 (a). (Note that to simplify matters, we will not
show the electrical connection between the gate terminals; it is assumed, however, that the two
terminals labelled G are joined together.) With gs
V = 0, the application of a voltage vDScauses
current to flow from the drain to the source. When a negative gs
V is applied, the depletion region
of the gate–channel junction widens and the channel becomes correspondingly narrower; thus the
channel resistance increases and the current iD(for a given vDS) decreases. Because vDSis small,
the channel is almost of uniform width. The JFET is simply operating as a resistance whose
value is controlled by gs
V . If we keep increasing gs
V in the negative direction, a value is reached
at which the depletion region occupies the entire channel. At this value of gs
V the channel is
completely depleted of charge carriers (electrons); the channel has in effect disappeared. This
value of gs
V is therefore the threshold voltage of the device, Vt, which is obviously negative for
an n-channel JFET. For JFETs the threshold voltage is called the pinch-off voltage and isdenoted
Consider next the situation depicted in Fig. 2.1(b). Here gs
V is held constant at a value greater
(that is, less negative) than VP, and vDSis increased. Since gs
V appears as a voltage drop across
the length of the channel, the voltage increases as we move along the channel from source to
drain. It follows that the reverse-bias voltage between gate and channel varies at different points
along the channel and is highest at the drain end. Thus the channel acquires a tapered shape and
the iD −vDScharacteristic becomes nonlinear. When the reverse bias at the drain end, vGD, falls
below the pinch-off voltage VP, the channel is pinched off at the drain end and the drain current
saturates. The remainder of the description of JFET operation follows closely that given for the
The description above clearly indicates that the JFET is a depletion-type device. Its
characteristics should therefore be similar to those of the depletion-type MOSFET. This is true
with a very important exception: While it is possible to operate the depletion-type MOSFET in
the enhancement mode (by simply applying a positive vGSif the device is n channel) this is
impossible in the JFET case. If we attempt to apply a positive vGS, the gate–channel pnjunction
becomes forward biased and the gate ceases to control the channel. Thus the maximum vGSis
limited to 0 V, though it is possible to go as high as 0.3 V or so since a pnjunction remains
essentially cut off at such a small forward voltage.
Fig.2.2 P type Substrate
In the N channel device, the N channel is sandwiched between two P type regions (the gate and
the substrate) that are connected together electrically to form the gate. The N type channel is FI
Fig 2.2.a JFET
connected to the source and drain terminals via more heavily doped N+ type regions. The drain
ic connected to a positive supply, and the source to zero volts. N+ type silicon has a lower
resistivity than N type. This gives it a lower resistance, increasing conduction and reducing the
effect of placing standard N type silicon next to the aluminum connector, which because
aluminum is a tri−valent material, having three valence electrons whilst silicon has four, would
tend to create an unwanted junction, similar in effect to a PN junction at this point.
The P type gate is at 0V and is therefore negatively biased compared to the channel, which has a
potential gradient on it, as one end is connected to 0 volts (the source), and the other end to a
positive voltage (the drain). Any point on the channel (apart from the extreme end near the
source terminal) must therefore be more positive than the gate. Therefore the two PN junctions
formed between the N type channel and the P type areas of the gate and the substrate are both
reverse biased, and so have a depletion layer that extends into the channel as shown in Fig. 2.1.
The shape of the depletion layer is not symmetrical, as can be seen from Fig. 2.1. It is generally
thicker towards the drain end of the channel, because the voltage on the drain is more positive
than that on the source due to voltage gradient that exists along the channel. This causes a larger
potential across the junctions nearer the drain, and so a thickening of the depletion layer. The
effect becomes more marked when the voltage between drain and source is greater than about
1volt or so.
A schematic representation of an n channel JFET is shown in Figure. An n-type channel is
formed between two p-type layers which are connected to the gate. Majority carrier electrons
flow from the source and exit the drain, forming the drain current. The pn junction is reverse
biased during normal operation, and this widens the depletion layers which extend into the n
channel only (since the doping of the p regions is much larger than that of the n channel). As the
depletion layers widen, the channel narrows, restricting current flow.
2.2.2JFET Operation above "Pinch Off":-
Fig 2.2.2 Operation of JFET with p-substrate
When a voltage is applied between drain and source (VDS) current flows and the silicon channel
acts rather like a conventional resistor. Now if VDS is increased (with VGS held at zero volts)
towards what is called the pinch off value VP, the drain current ID also at first, increases. The
transistor is working in the "ohmic region" as shown in Fig. 2.2.2.
However as drain source voltage VDS increases, the depletion layers at the gate junctions are also
becoming thicker and so narrowing the N type channel available for conduction. There comes a
point, known as "pinch off" where the conducting channel has become narrow enough to cancel
out the effect of current increasing with the applied voltage VDS as shown in fig 2.2. Above this
point there is little further increase in drain current and the transistor is said to operating in
"saturation mode". With the JFET biased in this way, a small change in VGS can be used to
control the current through the source−drain channel from its maximum (saturated) value to zero
This type of operation is shown in the fairly flat top to the output characteristics shown in fig 2.3.
Notice that each curve is drawn for a particular value of negative voltage between gate and
source, and that when sufficient reverse bias is applied to the gate (e.g. more than −2.5V, the
lowest value on the graph) the drain current ceases completely.
Figure 2.2.2.a:n-channel JFET structure
When Vgs>>Vds there is little voltage drop along the length of the channel, and the depletion
regions are parallel,. As vGS is increased negatively, they eventually touch reducing iD to zero.
The value of vGS at which this occurs is called the pinch-offvoltage,Vp (or vGS(off)). The
application of an additional voltage between the gate and the source in reverse bias condition
causes the depletion region to become more evenly distributed throughout the channel. This
further increases the channel resistance and reduces the amount of channel current with a given
drain voltage. Continuing to increase the gate voltage to the pinchoff point will reduce the drain
current to a very low value, effectively zero.
Connecting the gate to the source and applying a voltage between the drain and source also
produces the formation of a depletion region at the PN junction. The depletion region is then
concentrated at the drain end of the channel, as shown in Figure. Once again, increasing the
voltage causes the depletion region to spread farther into the channel. This results in a
corresponding increase in channel resistance due to the reduction in the cross sectional area of
the channel. The voltage at which the two depletion regions just touch in the middle of the
channel is called the drain saturation voltage. Operation of the JFET at voltages below and above
the drain saturation voltage are referred to the linear (or resistive) and saturation regions,
respectively. When operated in the saturated region, changes in voltage cause little change in
channel net current. The amount of current which will flow in the channel of a JFET operating in
this manner is called the drain saturation current. The JFET is normally operated in the saturated
region when used as an amplifier.
The current–voltage characteristics of the JFET are identical to those of the depletion-mode
MOSFET except that for the JFET the maximum vGSallowed is normally 0 V.
Fig2.3 Physical operation of n-channel JFET (a) For small vDSthe channel is uniform and thedevice
functions as a resistance whose value is controlled by vGS.(b)Increasing vDScauses the
channel toacquire a tapered shape and eventually pinch-off occurs. Note that, though not
shown, the two gate regionsare electrically connected.
Furthermore, the JFET is specified in terms of the pinch-off voltage VP (equal to Vtof the
MOSFET) and the drain-to-source current with the gate shorted to the source, IDSS, which
corresponds to for the MOSFET. With these substitutions, the n-channel JFET characteristics can
be described as follows:
Cut off: Vgs<Vp, Id=0
Triode region: 0,p gs ds gs p
V V V V V
2 1 GS DS DS
P P P
V V V
V V V
Saturation (pinch-off) region: 0,p gs ds gs p
V V V V V
D DSS DS
i I V
Recalling that for an n-channel device, VP is negative, we see that operation in the pinch-off
region is obtained when the drain voltage is greater than the gate voltage by at least VP.
Since the gate–channel junction is always reverse-biased, only a leakage current flows through
the gate terminal. we know that such a current is of the order of 9
10 A. Although iGis very
small, and is assumed zero in almost all applications, it should be noted that the gate current in a
JFET is many orders of magnitude greater than the gatecurrent in a MOSFET. Of course the
latter is so tiny because of the insulated gate structure. Another complication arises in the JFET
because of the strong dependence of gate leakage current on temperature—approximately
doubling for every 10 C rise in temperature, just as in the case of a reverse-biased diode .
2.4The JFET Small-Signal Model
The JFET small-signal model is identical to that of the MOSFET show in figure Here, gmis
Fig 2.4 Small signal model
or alternatively by
2 dss D
whereVGS and ID are the dc bias quantities, and
Small-signal modeling is a common analysis technique in electrical engineering which is used to
approximate the behavior of nonlinear devices with linear equations. This linearization is formed
about the DC bias point of the device.
DIFFERENT TYPE OF FET:
3.1 GALLIUM ARSENIDE (GaAs) DEVICES—THE MESFET:
Gallium arsenide (GaAs), a compound semiconductor formed of gallium, which is in the third
column of the periodic table of elements,and arsenic, which is in the fifth column; thus GaAs is
known as a III-V semiconductor.
The major advantage that GaAs offers over silicon is that electrons travel much faster in n-type
GaAs than in silicon. This is a result of the fact that the electron drift mobilityμn(which is the
constant that relates the electron drift velocity to the electric field; velocity = μnE) is five to ten
times higher in GaAs than in silicon. Thus for the same input voltages, GaAs devices have
higher output currents, and thus higher gm, than the corresponding silicon devices. The larger
output currents enable faster charging and discharging of load and parasitic capacitances and
thus result in increased speeds of operation.
3.2 The Basic GaAs Devices:
Gallium arsenide devices have been used for some years in the design of discrete
componentamplifiers for microwave applications (in the 109 Hz or GHz frequency range). More
recently, GaAs has begun to be employed in the design of very-high-speed digital integrated
circuits and in analog ICs, such as op amp.
Although there are a number of GaAs technologies currently in various stages of
development,we shall study the most mature of these technologies. The active device available
inthis technologies an n-channel field effect transistor known as the metal
semiconductorFETorMESFET.Thetechnology also provides a type of diodeknown as the
Schottkybarrier Thestructure of these two basic devices is illustrated by their cross sections, The
GaAs circuit is formed on an undopedGaAs substrate. Since the conductivity ofundoped GaAs is
very low, the substrate is said to be semi-insulating. This turns out to be anadvantage for GaAs
technology as it simplifies the process of isolating the devices on thechip from one another, as
well as resulting in smaller parasitic capacitances between thedevices and the circuit ground.
Scotty-barrier diode consists of a metal–semiconductorjunction. The metal, referred to as the
Scotty-barrier metal to distinguish it from the differentkind of metal used to make a contact (see
Long and Bunter (1990) for a detailedexplanation of the difference), forms the anode of the
That heavily doped n-type GaAs (indicated by n) is used between the n region and the cathode
metal contact in order to keep the parasitic series resistance low. The gate of the MESFET is
formed by Schottky-barrier metal in direct contact with then-type GaAs that forms the channel
region. The channel length L is defined by the length ofthe gate electrode, and similarly for the
width W (in the direction perpendicular to the page).
To reduce the parasitic resistances between the drain and source contacts and the channel,The
two contacts are surrounded with heavily doped GaAs.Since the main reason for using GaAs
circuits is to achieve high speed/frequency ofoperation, the channel length is made as small as
possible. Also,usually all the transistors on the IC chip are made to have the same length, leaving
only thewidth W of each device to be specified by the circuit designer.Only n-channel MESFETs
are available in GaAs technology. This is because holes have relatively low drift mobility in
GaAs, making p-channel MESFETs unattractive. The lack ofcomplementary transistors is a
definite disadvantage of GaAs technology.
Fig 3.2 n-channel V-MOSFET
3.3 Device Operation:
The MESFET operates in a very similar manner to the JFET, with the Schottky metal playing the
role of the p-type gate of the JFET. Basically, a depletion region forms in the channel below the
gate surface, and the thickness of the depletion region is controlledby the gate voltage. This in
turn effects control over the channel dimensions andthus on the current that flows from drain to
source in response to an appliedVds. The lattervoltage causes the channel to have a tapered
shape, with pinch-off eventually occurring atthe drain end of the channel.
The most common GaAs MESFETs available are of the depletion type with a thresholdvoltage
Vt(or, equivalently, pinch-off voltage VP) in the range of −0.5 to −2.5 V. Thesecontrols the
drain-to-source current. Gate conduction, which is not possible in MOSFETs, isanother definite
disadvantage of the MESFET.
Although less common, enhancement-mode MESFETs are available in certain
technologies.These normally-off devices are obtained by arranging that the depletion region
existing atvGSextends through the entire channel depth, thus blocking the channel and causing Id.
To cause current to flow from drain to source the channel must be opened by applyingto the gate
a positive voltage of sufficient magnitude to reduce the thickness of thedepletion region below
that of the channel region. Typically, the threshold voltage Vtisbetween 0.1 and 0.3 V.The above
description of MESFET operation suggests that the iD−vDScharacteristicsshould saturate as is
the case in a silicon JFET. It has beenobserved, however,that the iD−vDScharacteristics ofGaAs
MESFETs saturate at lower values of vDSand,furthermore, that the saturation voltages vDSsatdo
not depend strongly on the value of vGS.This ―early saturation‖ phenomenon comes about
because the velocity of the electrons in thechannel does not remain proportional to the electric
field (which in turn is determined by vDSand L; E vDSL) as is the case in silicon; rather, the
electron velocity reaches a highpeak value and then saturates (that is, becomes constant
independent ofVds). The velocitysaturationeffect is even more pronounced in short-channel
devices (L ≤1 m),occurring atvalues of Vdslower than (vGS−Vt).
Finally, a few words about the operation of the Schottky-barrier diode. Forward currentis
conducted by the majority carriers (electrons) flowing into the Schottky-barrier metal (theanode).
Unlike the pn-junction diode, minority carriers play no role in the operation of the SBD. As a
result, the SBD does not exhibit minority-carrier storage effects, which giverise to the diffusion
capacitance of the pn-junction diode. Thus, the SBD has only one capacitive effect, that
associated with the depletion-layer capacitance Cj.devices can be operated with Vgsvalues
ranging from the negative Vtto positive values ashigh as a few tenths of a volt. However, as
Vgsreaches 0.7 V or so, the Schottky-barrierdiode between gate and channel conducts heavily
and the gate voltage no longer effective.
3.4 Organic field effect transistor:
In organic FET´s (OFET) the active layer is an organic material. Until now measured current
characteristics have been analyzed by using the most simple equation for the current. But the
design of the OFET is not common in electronics. As demonstrated by our 2D simulations of
Alogous silicon devices this design leads to several peculiarities. We developed analytical
models which incorporate these peculiarities and reproduce the simulated current characteristics
with less than 3 to 5%error. As first applications we fitted published current characteristics of
OFET´s and determined in this way material parameters. Zero field mobility μ0 is low and
indicate hopping transport. Large flat band voltages must origin from oxide/interface charges.
Satisfactory fits are possible only by assuming velocity saturation unknown till now for hopping
systems. The ratio vs/μ0 ~ 1.5104V/cm can be explained theoretically.
In recent years there is an increasing interest in thin film field effect transistors with anactive
layer made from an organic material, organic FET’s (OFET). Even an all polymertransistor has
been reported. Among the rather different organic materials especially oligo-and poly thiophens
seem to be promising. Till now OFET’s are essentially used to determine the mobility of the
organic materials by analyzing the current characteristics. But there are also reports on circuits
and ring oscillators and proposals for possible applications. In all investigations the current
characteristics have been analyzed only by using the most simple equation for the current
(symbols with the usual meaning)below UDS = UGS - Uth and constant above. According to
Brown the mobility determined by using this expression is expected to be erroneous by up to 50
percent. Thus, significant determination of transport properties from measured current
characteristics require better models. We developed such models on the base of 2D simulations
of analogous silicon devices. Fitting these models to published measured current characteristics.
we determined several material parameters of the organic layers. Theoretical models
arepresented to understand the results which are partly rather unexpected.
3.5 Analytical model based on 2D simulations of the analogous silicon device:
The design of the OFET’s is not common in electronics. The layer sequence chosenfrom
technological reasons is as follows: n+-substrate (as gate)/oxide/active p-layer(organic). In some
cases instead of a gate-substrate one has used a substrate covered by ametallic orgraphitic gate
(followed again by the insulator and the active layer).
Fig.3.5 The OFET design
The organic OFETdesignlayer has a floating potential as e.g. the SOIFET or the new vertical
MOSFET.Further, theOFET’s operate in depletion or accumulation (till now it seems tobe
difficult to achieveinversion) and therefore the layer should be sufficiently thin.Such transistors
show severalpeculiarities. This has been shown by 2D simulations ofanalogous Si-devices for
which, of course, the material parameters are known. Thefollowing properties are especially
(a) Since the OFET operates indepletion and accumulation depending on the gatevoltage the
surface potential can beshifted by more than twice the bulk potential (e.g. morethan 0.8V in Si
with 1017doping, in the wide-gap organics more than 1.5..2V) and thereforethis is a serious
(b) The operation of thedevicedependssensitivelyon the ratio of layer thickness and depletion
length, which is smaller intheorganics than in Si due to the smaller dielectric constant.
(c) In both depletion and accumulation transverse field reduces the mobility but there is no
transverse field at thetransition from depletion to accumulation (flat band voltage). This
peculiarity results in ahump in the transfer characteristics.
(d) If one has accumulation at source and due to a highdrain voltage depletion at drain than at
some position between source and drain there is no transverse field. Thus, there is no
monotonous decrease of the mobility due to the increasing.
Fig3.5.1 simple OFET design
Lateral field from source to drain. Evidently, none of these peculiarities is described by the
simple with constant values for μ and Uth . On the other hand, since for the organics little is
known till now on the transport properties (compared to Si and other inorganic semiconductors)
it is important to have an analytical model which allows determining these properties by fitting
the model to the experimental characteristics.
Based on the results of the 2D simulations we developed such analytical models of different
complexity (depending on operation conditions and layer thickness) which describe the
peculiarities (a) to (d). The analytical models have been tested in the following manner: Using
the material parameters of the 2D simulations in the analytical model the littererproduces the
current with an error less than 3 to 5 percent. Further, fitting the analytical model to the 2D
simulations results in material parameters which coincide within 5 to 10 %with those in the 2D
simulations. A modification of the model accounts for the existence of polarons and bipolarons
in some conducting polymers.
3.6 Metal oxide field effect transistor:
The metal-oxide semiconductor field-effect transistor (MOSFET)is without doubt the most
commercially successful solid-state device. It is the primary component in high-density VLSI
chips, including microprocessors and memories. A second type of FET, the junction field-
effecttransistor(JFET),is based on a pnjunction structure and finds application particularly in
analog and RF circuit design.
P-channel MOS (PMOS) transistorswere the first MOS devices to be successfully fabricated in
large-scale integrated (LSI) circuits. Early microprocessor chips used PMOS technology .Greater
performance was later obtained with the commercial introduction of n-channel MOS
(NMOS)technology, using both enhancement-mode and ion-implanted depletion-mode devices.
CHARACTERISTICS OF THE MOS CAPACITOR:
The MOS capacitor is used to induce charge at the interface between the semiconductor and
oxide. The top electrode of the MOS capacitor is formed of a low-resistivity material, typically
aluminum or heavily doped polysilicon (polycrystalline silicon). We refer to this electrode as the
gate (G)for reasons that become apparent shortly. A thin insulating layer, typically silicon
dioxide, isolates the gate from the substrate or body—the semiconductor region that acts as the
second electrode of the capacitor. Silicon dioxide is a stable, high-quality electrical insulator
readily formed by thermal oxidation of the silicon substrate. The ability to form this stable high
quality insulator is one of the basic reasons that silicon is the dominant semiconductor material
today. The semiconductor region may be n- or p-type,
The semiconductor forming the bottom electrode of the capacitor has a substantial resistivity and
a limited supply of holes and electrons. Because the semiconductor can therefore be depleted of
carriers, the capacitance of this structure is a nonlinear function of voltage. the conditions in the
region of the substrate immediately below the gate electrode for three different bias conditions:
accumulation, depletion, and inversion.
4.1 Accumulation Region:
The situation for a large negative bias on the gate with respect to the substrate is depicted in
Fig.(a). The large negative charge on the metallic gate is balanced by positively charged holes
attracted to the silicon-silicon dioxide interface directly below the gate. For the bias condition
shown, the hole density at the surface exceeds that which is present in the original p-type
substrate, and the surface is said to be operating in the accumulation regionor just in
accumulation.This majority carrier accumulation layer is extremely shallow, effectively existing
as a charge sheet directly below the gate.
4.2 Depletion Region:
The situation as the gate voltage is slowly increased. First, holes are repelled fromthe surface.
Eventually, the hole density near the surface is reduced below the majority-carrierlevel set by the
substrate doping level, as depicted in Fig. 4.2(b). This condition is called depletionand the
region, the depletion region. The region beneath the metal electrode is depleted of free carrier
carriers in much the same way as the depletion region that exists near the metallurgical junction
of the pnjunction diode. In Fig. 4.2(b), positive charge on the gate electrode is balanced by the
negative charge of the ionized acceptor atoms in the depletion layer. Fig 4.bjf
Fig 4.1 MOS Capacitor Structure with p-type Silicon
Fig 4.2 MOS Capacitor operating in (a) Accumulation (b) Depletion (c) Inversion parameter Vtn
4.3 Inversion Region:
As the voltage on the top electrode increases further, electrons are attracted to the surface. At a
particular voltage level, which we will shortly define as the threshold voltage,the electron density
at the surface exceeds the hole density. At this voltage, the surface has inverted from the p-type
polarity of the original substrate to an n-type inversion layer,or inversion region,directly
underneath the top plate as indicated in Fig. (c). this inversion region is an extremely shallow
layer, existing as a charge sheet directly below the gate.
In the MOS capacitor, the high densityof electrons in the inversion layer is supplied by the
electron–hole generation process within the depletion layer. The positive charge on the gate is
balanced by the combination of negative charge in the inversion layer plus negative ionic
acceptor charge in the depletion layer. The voltage at which the surface inversion layer just
forms plays an extremely important role in field-effect transistors and is called the threshold
voltageVT N. depicts the variation of the capacitance of the NMOS structure with gate voltage
.At voltages well below threshold, the surface is in accumulation, corresponding toFig.(a),and
the capacitance is high and determined by the oxide thickness.As the gate voltage increases, the
surface depletion layer forms as in Fig.(b), the effective separation of the capacitor plates
increases, and the capacitance decreases steadily.
The total capacitance can be modeled as the series combination of the fixed oxide capacitance
Cox and the voltage dependent depletion-layer.
4.4 THE NMOS TRANSISTOR:
A MOSFET is formed by adding two heavily doped n-type (n+)diffusions to the cross section of
Fig., resulting in the structure in Fig. 4.4. The diffusions provide a supply of electrons thatcan
readily move under the gate as well as terminals that can be used to apply a voltage and causea
current in the transistor.
Figure shows a planar view, cross section, and circuit symbol of an n-channel MOSFET,usually
called an NMOS transistor,or NMOSFET. The central region of the MOSFET is theMOS
capacitor discussed in Sec. 4.1, and the top electrode of the capacitor is called the gateof the
MOSFET. The two heavily doped n-type regions (n+ regions), called the source (S)anddrain
(D),are formed in the p-type substrate aligned with the edge of the gate. The source anddrain
provide a supply of carriers so that the inversion layer can rapidly form in response to thegate
The substrate of the NMOS transistor represents a fourth device terminal and isreferred to
synonymously as the substrate terminal,or the body terminal (B).The terminal voltages and
currents for the NMOS device are also defined in Fig. 4.4(b).The draincurrent ID, source current
IS, gate current IG, and body current IBare all defined, withthe positive direction of each current
indicated for an NMOS transistor. The important terminalvoltages are the gate-source voltage
VGS= VG−VSthe drain-source voltage VDS=VD−VS, andthe source-bulk voltage VSB= VS−VB.
These voltages are all positive during normal operationof the NMOSFET.
Fig 4.4 NMOS transistor
The source and drain regions form pnjunctions with the substrate. These two junctions are kept
reverse-biased at all times to provide isolation between the junctions and the substrate as well as
between adjacent MOS transistors. Thus, the bulk voltage must be less than or equal to the
voltages applied to the source and drain terminals to ensure that these pnjunctions are properly
The semiconductor region between the source and drain regions directly below the gate is called
the channel regionof the FET, and two dimensions of critical import are defined in Fig. L
represents the channel length,which is measured in the direction of current in the channel. Wis
the channel width, which is measured perpendicular to the direction.
CHAPTER - 5
APPLICATION OF JFET
The Junction Field Effect Transistor (JFET) exhibitscharacteristics which often make it more
suited toa particular application than the bipolar transistor.
Some of these applications are:
High input impedance amplifiers
Constant current sources
Analogue switches or gates
Voltage controlled resistors
An N-channel JFET has a low bias current when its gate is biased negative to the
source.However, this requires either that the gate voltage be biased negative with respect to the
source voltage or that source voltage be biased positive with respect to the gate voltage. For ac
amplifier designs, gate biasing can be made self-biased by using an RC network at the source to
hold the positive voltage for a period longer than the time period of the inputpulse/frequency
In the design described here, the JFET source is constantly biased. Hence, its frequency response
is excellent from dc to 10 MHz. This improvement is due to stable diode biasing. Diode biasing
exhibits only a 2mV/°C drop in voltage with increasing temperature from 0°C to 100°C. This is
5.1 Basic JFET amplifier configurations:-
There are three basic JFET circuits: the commonsource, the common gate, and the common
drain. Each circuit configuration describesa two port network having an input and an output.The
transfer function of each is also determined by the input and output voltages or currents of the
circuit.The most common configuration for the JFET as anamplifier is the common source
circuit. For an Nchanneldevice the circuit would be biased.
The Junction Field Effect Transistor (JFET)exhibits characteristics which often make itmore
suited to a particular application than thebipolar transistor. Some of these applications are:
High Input Impedance
Amplifier Low-Noise Amplifier
Constant Current Source
Analog Switch or Gate
Voltage Controlled Resistor
In this application note, these applications, alongwith a few others, will be discussed. Only
thebasics will be shown without going into too muchtechnical detail.
Fig. 5.1 JFET Amplifier Circuit Configurations
The most common configuration for the JFET as an amplifier is the common source circuit. For
an N-channel device the circuit would be biased .
Since the N-Channel JFET is a depletion mode device and is normally on, a gate voltage which
has a negative polarity with respect to the source is required to modulate or control the drain
current. This negative voltage can be provided by a single positive power supply using the self
biasing method shown in Figure 5.1.b. This is accomplished by the voltage which is dropped
across the source resistor, Rs, according to the current flowing through it. The gate-to-source
voltage is then defined as:
VGS = ID x RS
Fig. 5.1.b Common Source Amplifier Using VGS Self-Biasing Method
The circuit of Figure 5.1.b also defines a basic single stage JFET amplifier. The source resistor
value is determined by selecting the bias point for the circuit from the characteristic curves of the
JFET being used. The value of the drain resistor is then chosen from the required gain of the
amplifier and the value of the drain current which was previously selected in determining the
gate voltage. The value of this resistor must also allow the circuit to have sufficient dynamic
range, or voltage swing, required by the following stage. The following stage could be anything
from another identical circuit to a loud speaker for an audio system. The voltage gain of this
circuit is then defined as:
AV = (gm x Zl) / (1 + gm x RS)
where AV= the voltage gain
gm = the forward transconductance or gain of the JFET
Zl = the equivalent load impedance
RS = the value of the source resistor
The effect of the source resistor on the gain of the circuit can be removed at higher frequencies
by connecting a capacitor across the source resistor. This then results in an amplifier which has a
AV = gm x Zl
but only at frequencies above that defined by the resistor-capacitor network in the source circuit.
This frequency is defined as:
flo = 1 / (2¹ x RS x CS)
whereflo = the low frequency corner
¹ = the constant 3.1418
RS = the value of the source resistor in ohms
CS = the value of the source capacitor in farads
This circuit also has a high input impedance, generally equal to the value of the input impedance
of the JFET.
5.2 A Low-Noise Amplifier
A minor change to the circuit of Figure 5.2 describes a basic single stage low-noise JFET
amplifier. Figure shows that this change only incorporates a resistor from the gate to Vss. This
resistor supplies a path for the gate leakage current in an AC coupled circuit. Its value is chosen
by the required input impedance of the amplifier and its desired low-noise characteristics. The
noise components of this amplifier are the thermal noise of the drain and gate resistors plus the
noise components of the JFET. The noise contribution of the JFET is from the shot noise of the
gate leakage current, the thermal noise of the channel resistance, and the frequency noise of the
channel. These noise characteristics are generally lower than those found in bipolar transistors if
the JFET is properly selected for the application. The voltage gain of the circuit is again defined
by Equation .
Fig.5.2Low-Noise JFET Single Stage Amplifier with Source By-Pass Capacitor, CS
5.3 The JFET Differential Amplifier
Another application of the JFET is the differential amplifier. This configuration is shown in
Figure 5. The differential amplifier requires that the two transistors be closely matched
electrically and physically located near each other for thermal stability. Either input and either
output can be used or both inputs and only one output and conversely only one input and both
outputs can be used. For the configuration shown the source resistor is chosen to determine the
gate to source bias voltage, remembering that the current will be twice that of each of the JFET
drain currents. The value of the drain resistors is chosen to provide a suitable dynamic range at
the output. The gain of this circuit is defined by:
AV = 2x (gmx Rl) / (1 + gm x RS )
where all the terms in the equation have previously been defined. This circuit configuration is
very useful as a highinput impedance stage to be connected to the inputof a low cost operational
amplifier, such as thepopular 741 Op-Amp
Fig .5.3The Matched Pair JFET Differential Amplifier
5.4 The JFET Constant Current Source
A constant current source using a JFET is shown in Figure 5.4. This circuit configuration has
many useful applications ranging from charging circuits for integrators or timers to replacing the
source resistor in the differential amplifier shown in Figure 5.3.
The current provided by the constant current source of Figure 5.4 is defined as
ID = IDSS [ 1 - ( VGS / Vp) ] 2
where ID = the drain current or magnitude of current sourced
IDSS = the drain saturation current of theJFETVGS = ID x RS
Vp = the JFET pinch-off voltage
2 = the squared value of the term in brackets.
It can be readily seen that the use of this circuit inthe source circuit of the differential amplifier
of Figure 5 would improve the circuit voltage gain as well as reduce the amplifier noise and
enhance the CMRR of the amplifier.
Fig 5.4 JFET Constant Current Source
5.5 The JFET Analog Switch
Figures 5.5, 5.5.a, and 5.5.b show three different applications for the JFET to be used as an
analog switch or gate. Figures 5.5 and 5.5.a both demonstrate methods for realizing
programmable gain amplifiers, while Figure 5.5.b shows an analog multiplexer circuit using
JFETs and a common op-amp integrated circuit. It can be seen from Figure 5.5 that the gain of
the stage can be changed by switching in any combination of feedback resistors R1 through Rn.
The JFET in series with the input resistor should be of the same type as those in the feedback
paths and is used for thermal stability of the circuit gain. The transfer function of the circuit of
Figure 5.5 is approximated by:
Vo / Vi = 1 / [(1 / R1) + (1 / R2) + .... +(1 / Rn ) ] / Ri
R1 through Rn= the feedback resistors
Ri= the input resistors
Vo= the output voltage
Vi= the input voltage
Note that only those feedback resistors which are switched into the circuit are to be included in
the the transfer function equation.
Fig5.5 Programmable Gain Amplifier
The circuit of Figure 8 shows another method to realize a programmable gain amplifier using a
common op-amp, four resistors, and only two JFETs. The gain of this circuit can also be changed
by switching in the desired resistors by turning off the appropriate JFET thus switching in the
parallel resistor. The transfer function of this circuit is approximated by:
Vo/ Vi = (R3 + R4) / (R1 + R2)
Fig.5.5.a Programmable Gain Amplifier with 4 Resistors and 2 JFETs
It should be noted that only those resistors which are switched into the circuit are to be included
in the transfer function equation. Figure 9 shows a circuit in which the JFETs are acting as
analog switches to multiplex several input signal sources to a single output source. The transfer
function of this circuit is then approximated by:
Vo / Vi = Rf / Rn
Rf = the feedback resistor
Rn = any one of the input resistors
Further examination of this circuit shows that it can also be used as a programmable summing
amplifier by switching in any combination of input signals. The transfer function is then
Vo / Vi = (Rf / R1) + (Rf / R2) + .... + (Rf /Rn)
Again in this application only those resistors which are switched into the circuit are to be
included in the transfer function equation.
Fig.5.5.b Analog Multiplexer Circuit which can also be used as a Programmable Summing
5.6 The JFET Voltage Controlled Resistor
Another common application for the JFET is as a voltage controlled resistor. The JFET action in
normal operation simply changes the cross sectional dimensions of the channel. When the JFET
is biased in the resistive or linear region as shown in Figure 10, a change in gate voltage and the
corresponding change in channel dimensions simply changes the drain to source resistance of the
Fig.5.6 JFET Family of Characteristic Curves of ID vs. VDS and VGS
Figure 5.6 depicts a JFET being used as a voltage controlled resistor (VCR). The resistance is
determined from the bias point conditions selected from the curves of Figure 5.6.
The resistance is then defined as
RDS = VDS / IDS
RDS = the drain to source resistance
VDS = Vo or the output voltage
IDS = the drain current
It can readily be seen from the curves of Figure 10 that any change in the input voltage (Vi) or
the gate to source voltage will cause a corresponding change in the drain current. Equation
indicates that there is a corresponding change in the drain to source resistance (RDS). Therefore,
the resistance is controlled by the voltage applied to the gate, resulting in a voltage controlled
This application note describes several useful junction field effect transistor circuit
configurations. The high input impedance and low-noise circuits are often used as input stages to
voltage measurement instruments such as oscilloscopes and digital voltmeters. The differential
amplifier is a very widely used circuit in applications where the difference between two voltages
is to be measured, such as the input stage of an operational amplifier. The use of JFETs in this
application provides high input impedance and low input leakage current. Constant current
sources have many uses such as setting bias conditions for many other circuits in a system and as
charging circuits for integrators and timing circuits. The analog switch is most often used in an
analog multiplexer and in sample and hold circuits. Voltage controlled resistors are normally
found in automatic gain control circuits and voltage controlled tuning circuits.
Therefore it is clearly seen that many applications for Junction Field Effect Transistors exist.
Those discussed in this application note have many variations, refinements, and other uses. It
should be noted that these applications were described in the simplest detail and additional study
of the particular application should be considered before using any of the circuits presented.
5.7 Superior JFET biasing improves amplifier performance
An N-channel JFET has a low bias current when its gate is biased negative to the source.
However, this requires either that the gate voltage be biased negative with respect to the source
voltage or that source voltage be biased positive with respect to the gate voltage. For ac amplifier
designs, gate biasing can be made self-biased by using an RC network at the source to hold the
positive voltage for a period longer than the time period of the input pulse/frequency source. In
the design described here, the JFET source is constantly biased. Hence, its frequency response is
excellent from dc to 10 MHz. This improvement is due to stable diode biasing. Diode biasing
exhibits only a 2mV/°C drop in voltage with increasing temperature from 0°C to 100°C.
This is excellent stability. In this example of a pulsed amplifier design, the signal source has
been biased by a 1Gohm resistance to ground, and the JFET source is biased using a fast diode, a
1N4148, at a source-drain current of about 5mA. The gate is maintained at ground potential so
that no bias voltage is injected into the input dc circuit. This scheme makes the gate remain at
zero voltage unless a signal to be amplified changes it. This technique is illustrated in the figure,
where the input impedance of the circuit is maintained at 1Gohm, unless it’s shunted by the
impedance of the signal source.
The JFET’s output current is kept significantly high at 5mA to let the JFET drain voltage remain
at its midoperating point, about 5 V. This enables the JFET to work for both positive and
negative input signals.
In this circuit, a J309 or IFN152 JFET is the most suitable device, with an input bias current of
about 100pA. The amplifier delivers a good signal response to about 10 MHz. A 2N4117A JFET
would reduce the input bias current but also reduce the high-frequency response considerably.
This circuit makes an excellent input-stage amplifier for oscilloscopes, where input impedance
isn’t greater than 1Mohm. The amplifier improves the input stage to 1Gohm. The circuit ismost
suitable for piezoelectric detectors, photodiode-based radiation detector.
Fig.5.7 Circuit operation of MOS transistor
This improvement is due to stable diode biasing. Diode biasing exhibits only a 2mV/°C drop in
voltage with increasing temperature from 0°C to 100°C. This is excellent stability. In this
example of a pulsed amplifier design, the signal source has been biased by a 1Gohm resistance to
ground, and the JFET source is biased using a fast diode, a 1N4148, at a source-drain current of
Advantages and Disadvantages
Following are the Advantages of JFET over BJT:
1. Operation of JFET depends upon the flow of majority carriers only i.e. electrons in n-type and
holes in p-type semiconductor. Because of this JFET is said to be Unipolar device. Unlike this
BJT depends on the follow of both the types of carriers and is a bipolar device.
2. Normally JFETs are extremely immune to any type of radiations which is not so for BJTs.
3. JFET have a high value of input resistance (normally of the order of Meg-ohms), this provides
a good isolation between the input and output ts.
4. Circuits based on JFET are supposed to be less noisy in their functionality as compared to
5. JFET exhibits no offset voltage at zero drain current and hence functions as an excellent
6. In comparison to BJTs JFETs are highly Thermally Stable.
7.FETs generate a lower noise level than the Bipolar Junction Transistor (BJT).
8.FETs are more stable than BJT with temperature.
9.The high input impedance of FET allows them to withhold loads long enough to allow its
usage as storage elements.
10.They are devices controlled by voltage with a very high input impedance (107
1) FETs have a poor frequency response due to its high input capacitance.
2) FETs have a very poor linearity, and generally they are less linear than BJT.
3) FETs can be damaged due to the static electricity.
6.3 Conclusion and Future work
Future and Emerging Technologies (FET) is the basic research engine fueling the Information
and Communication Technologies (ICT) programme. It provides a unique combination of high-
risk, long-term, multidisciplinary and collaborative, frontier research with the structuring of more
mature ideas and communities.
Thus, it is able to convert novel proofs of concepts into mainstream research and innovation and
ultimately industrial applications and systems. FET supported research goes beyond the
conventional boundaries of ICT and ventures into uncharted territories, increasingly relying on
fresh synergies, cross-pollination and convergence with different scientific disciplines (for
instance, biology, chemistry, nano- and molecular science, neuro- and cognitive science,
ethology, social science, economics) and with the arts and humanities.
FET-Proactive initiatives constitute clusters of interacting and collaborating projects. In most
cases a coordination action is in charge of organising and facilitating the collaboration and
performing joint tasks, such as compiling research roadmaps, organising joint events
(workshops, conferences, summer schools,..), editing joint publications, maintaining the web
portal of the initiative, and organising international co-operation.
In FP7 (2007-2012) in Call 1 – Call 8, FET Proactive supported 24 Integrated Projects (IP), 60
targeted research projects (STREP) and 23 Coordination and Support actions (CA, CSA, SA) for
a total funding of 377M€. From Call 9, 5 Integrated Projects (IP), 16 targeted research projects
(STREP) and 5 Coordination and Support actions (CA, SA) are currently under negotiation.