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  • 1. MIXED SIGNAL ASIC DESIGN ISSUES AND METHODOLOGIES Jay A. Kuhn, Robert V. Alessi Seattle Silicon Corporation 3075 112th Avenue N . E . Bellevue. WA 98004 Abstract This tutorial presents a broad overview of the major design limited to what is available. A great pexzntage of the increasedissues related to creating mixed analoddigital application specific demand for ASICs, however, is coming from companies that dointegated circuits (ASICs). The tutorial discusses this subject not have a foundry. For these companies, there is a broad rangefrom the perspective of a potential customer or designer by out- of processes to chose from. The technical requirements forlining the design decisions, limitations, trade-offs and require- operating voltage, component tolerances, and the amount of ana-ments he or she will face during the course of a mixed signal log and digital circuits to be integrated will affect the range ofASlC project. The major technical issues are identified as pro- process options available and hence the cost of the chip.cess selection, module selection and creation, simulation, and There are four factors that can limit the operating voltage ofmixed signal placement and routing. The major aspects of these a CMOS circuit. First, parasitic transistors or conduction pathsissues are discussed and common methodologies, as well as new can be created when high voltage on a conductor inverts the sub-research for meeting design requirements, are illustrated. Exam- strate under the field oxide. Second, high voltages on a MOSplcs illustrating the design technique using Seattle Silicons transistor can cause reach-through, the extension of the drainChipCrafter/MAXm product are presented. depletion region to the source, effectively creating a short circuit. Third, impact ionization at the pinch-off region of NMOS transistors results in stray substrate currents and reduced output1. Introduction conductance. Fourth, high voltage across gate oxides can result The need to increase the complexity and reduce the cost of in breakdown or "punch-through of the oxide. Decreasing theelectronic systems has greatly accelerated the demand for com- depth of the field oxide, the spacing of the drain to source, or thebining discrete components into application specific integrated thickness of the gate oxide will lower the voltage at which thesecircuits (ASICs). As more digital circuitry is integrated, the ana- effects will occur. As a result the maximum allowed operatinglog components of a system are more likely to represent a voltage must be reduced as the feature size of the process isbottle-neck in the path to size and cost reduction for a system. decreased.This trend has generated a steadily increasing demand for com-bining analog circuitry on the same chip as digital functions.With the increased demand for mixed signal ASICs, comes acorresponding demand for software tools and design methodolo-gies that increase the productivity of analog ASIC designers and 7u 50 vreduces the amount of IC design knowledge required fordesigners without extensive integrated circuit expertise. I 5u 18-3Ov The purpose of this tutorial is to present an overview of 3u 7-18~techniques and methodologies used to design a mixed signalASIC. A typical mixed signal ASIC project will need to address 2u 5-12~issues in the following four basic categories: selecting a process,selecting or creating modules, simulating the design, and theplacement and routing of modules. This tutorial will discuss the I 1.2u I 5-10~ Iaspects of these issues that are unique to analog design or mixed I 1.ou 5vsignal design. The majority of digital ASICs created today use CMOS Fig. 1 CMOS Operating Voltage V.S. Feature Sizes.process technology due to the ease of fabrication, low powerconsumption and relative speed. When discussing mixed signal Figure 1 illustrates the common operating voltages found indesign the assumption in this paper is that the process used is an informal survey of a number of foundries. High voltageCMOS or possibly BiCMOS. Since BiCMOS processes are typi- operation, greater than 18V, is possible but commonly only incally more complex and more expensive than CMOS it will processes with feature sizes greater than 5 microns. This makessuffice to say that the use of BiCMOS is for applications that all but the most rudimentary digital functions impractical. Somedemand the increased analog accuracy, drive capability or digital 3 micron processes are capable of maximum operating voltagesspeed offered by such a process. up to 18 volts. At this feature size a moderate amount of digital capability is possible. Ten volt maximum operation is more2. Process Selection common in 3 micron geometries. The first issue that needs to be resolved in an ASIC project At 2 micron feature sizes, the voltage for a minimum sizedis the selection of a CMOS process for the chip implementation. transistor is usually limited to 5 volts. Analog circuits can func-Selecting a process requires consideration of qualifying a foundry tion at higher voltages if channel lengths are made larger thanas a vendor, the economics of a process for the chip, and the minimum to prevent reach-through. Also, circuit techniquestechnical requirements of the system. If the company designing which limit the maximum voltage that appears on the drain ofthe chip has its own foundry, then the process selection may be NMOS transistors may be used in the design of modules to miti-CH1234-5/89/0000-T4-1.1$01 .OO 0 1989 IEEE T4-1.1
  • 2. gate impact ionization [l]. If a p-well process is selected, the smaller 2-poly capacitors in applications not explicitly requiringsupply for the analog cells may be run at +/- 5 volts while the the added accuracy.digital cells operate at 0 and 5 volts. Additional cells may be In summary, requirements for 2-poly processes and operat-added to the library to interface with with theses voltage levels. ing voltages greater than 5 volts will be a large factor in deter- For geometries below 2 microns, the field and gate oxides mining potential processes for an ASIC. If a system can beare thin enough that higher voltages can either turn on parasitic designed without these requirements, the ASIC cost may betransistors in the substrate or punch through the gate oxides. reduced, particularly if the amount of digital circuitry is large.Special processing techniques are required to achieve higheroperating voltages below 2 microns [2]. 3. Modules Operation of analog circuits at 5 volts does not necessarilymean severe performance limitations. The success of many The next major task in an analog ASIC project, mixed sig-telecommunication circuits, low impedance buffer driving cir- nal or not, is to acquire a set of analog modules or primitive ele-cuits, and consumer electronics for camera and digital audio, ments that can be interconnected to imulement the functionsattest to the high performance that can be obtained with 5 volt required by the system. The definition of "acquire" and "analog module" can be very broad depending on the methodology beingCMOS circuits [3,4,5]. used. To "acquire" can mean building custom modules, using a One consideration with the reduced supply levels of 5 volt vendors modules or finding software tools that will generateoperation is a reduction of the dynamic range of analog circuitry. some modules automatically. In some cases, the module mayThis is a valid concern if the incoming signals to the chip need simply be single transistor and in others it may be an entire ADCto be attenuated to fit within the reduced power supply range. converter, or even an entire data acquisition system.When small signals are processed, dynamic range is usually lim-itTd by the noise of the first few stages of signal processing. This There are numerous tools and methodologies in variousnoise is independent of the supply voltage. When dynamic range stages of development designed to increase the ability of an ASIC designer to obtain analog modules. We can categorizeis important, differential circuitry can effectively double the these methodologies as full custom design, standard cell libraries,available signal amplitude and increase rejection of power supply parameterized standard cells or module generators, layout syn-noise. thesis and circuit synthesis. Each of these methodologies offer Frequently, voltage requirements are related to system varying degrees of cost and flexibility for creating or obtaining a imposed considerations such as available supply voltages, input module. The table in figure 2 lists the relative merits of each signal ranges, and system concepts that were constructed around methodology. higher voltage parts. Many designers would like to convert existing analog systems implemented with 30V bipolar parts into an ASIC, but find the effort in overcoming the inertia built intoexisting circuit design methodologies a significant hindrance. Ifsystems can 6 designed around 5 volt analog parts, more I Methodology Flexi- bility cost Ioptions exist for using higher performance, high density Full Custom High Highprocesses that may yield the lowest cost solutions. A second decision which must be made in process selection Standard Cellsis whether or not a 2nd layer polysilicon process would be Module Generators Medium Medium I 1 Irequired to build large or precision capacitors. Like high voltagerequirements, a 2-poly requirement may restrict the availableprocesses for implementing the ASIC. Though there are no phy- Layout & Circuit High Mediumsical barriers to implementing 2-poly in small geometry Synthesisprocesses, it does add complexity, and therefore these processesrequire more time to mature. Typically the 2-poly processbecomes available one to two years after a basic 1-poly process Fig. 2 Hierarchy Of Module Design Methodologies.is made commercially available. If the ASIC is intended to beaggressive in its digital capabilities, the 2-poly requirement may Full custom design is the most costly but most flexiblerule out the use of the more advanced digital processes. design methodology. Layouts as well as circuit designs must be There are many classes of analog circuits that do not expli- developed from scratch. There are very few companies contem-citly require the precision capacitors that 2-poly offers. In 2- plating their first mixed signal ASIC that can afford the expertisemetal processes, capacitors can be built with poly-metal-metal2 to implement full custom designs.sandwiches that are from one-half to one-fifth as area efficient as To overcome this, most vendors of ASIC services havea similar 2-poly capacitor. These capacitors are suitable for cir- developed sets of predefined libraries of analog modules [6,7,8].cuits such as opamp compensation, sample and holds, auto-zero Often these library elements were developed for full custom pro-and chopper circuits. Many application areas such as power mon- jects. The vender will attempt to capitalize on this design invest-itoring, security sensing circuits, motor controllers, power-on- ment by offering these cells to other potential users. The advan-reset circuits, slope A2D circuits and digital voltmeter circuits do tages to the user are two fold. The first is the elimination of thenot require precision capacitor matching. 2-poly capacitors are cost of full custom design. The second advantage is that themainly required in switched capacitor filters and some D2A and modules have typically been fabricated and their performance hasA2D architectures where precision matching is required for accu- been well characterized. The major drawback of standard cells israte transfer functions. the limited range of options available to the user. A design may A 2-poly process will typically cost 10.20% more than a require specifications outside those availble in the current library.standard process due to extra mask and processing steps. This Consequently, the vendor will either work with the designer tocost must be compared to the die area that is saved by using the customize existing cells or develop new cells. T4-1.2
  • 3. To overcome this standard cell limitation a layout metho- chip, including as much of the analog interface as possible,dology referred to as module generation, or parameterized stan- should be capable of being simulated independent of the analogdard cells, is often used. Instead of creating a manual layout of a portions of the design. This means that good design-for-cell, the layout is specified in a software program where the testability practices should be applied so that all analog interfacedimensions of primitive polygons or transistors are encoded in nodes are both controllable and observable from the digital por-fernis of design rules or specifications for the module [9]. If writ- tion of the chip. There are two reasons for this practice. First, theten correctly, the design rules and specifications for the dimen- analog and digital circuits are often designed by two differentsions of different transistors may be changed and a new layout project team members. The digital designer is faced with creatinggenerated quickly. Modules may vary in complexity from sim- test vectors to simulate the operation of the digital portion of theple transistors to entire A2D converters, and may also include circuit. If the circuit is tested by stimulating the digital sub-some synthesis algorithms to calculate layout parameters from blocks from analog interface nodes that are not directly accessi-higher level user specifications [10,11,12]. An analog ASIC ven- ble external to the chip, then most of these test vectors will notdor musf be willing to work with designers on customizing key be usable when the analog and digital blocks are combined in theanalog components. If the ASIC vendors library is implemented final chip. If, on the other hand, the majority of dgital circuitsas module generators the task of modifying a particular cell is are testable directly from the normal digital VO of the chip, thensimplified. In some cases module generators may be used by the most of the digital test vectors will be useful in final designdesigners, who can then build their own library. This works par- verification and for creating test vectors for silicon verification.ticularly well for simpler components such as resistors, capaci- Secondly, if there are problems with the circuits during fabrica-tors and transistors. tion, the ability to verify correct operation of the digital circuiuy The last two categories of design methodology are some- on the silicon, including the interface nodes, can aid in findingtimes confused with each other and with module generators as the fault.well. Layout synthesis is the process of generating a geometriclayout of an arbitrary net list of primitive transistors. It differsfrom module generators in that the module generator implementsone or a small number of predefined topologies. Layout syn-thesis is much more complex, and is still being researched. -i ISome very promising results are being seen [13,14,15]. Circuit synthesis is the process of translating a specificationfor a module or function into a net list of primitive components.Depending upon the application, the primitive components maybe transistors, opamps or filter sections. A sub-problem of syn-thesis is dimensioning, which is the calculation of the parametersof the primitive components [16]. Typical parameters would betransistor widths in an opamp or capacitor ratios in a filter. Thereis a considerable amount of research being conducted on circuitsynthesis in specific areas such as switched capacitor filters, dataconveners and opamp design [17,18,19,20]. The results areoften presented in combination with layout synthesis, cell genera-tors or placement and routing tools, sometimes making it difficultto identify the focus of the work. Typically any combination of VREF Icircuit or parameter sythesis combined with layout synthesis ormodule generation is refered to by the term "compiler". For companies seeking entry into the mixed signal ASICmarket, the most common solution to the problem of acquiringmodules is working with a vendor which provides a standard cellor parameterized standard cell library. The results of circuit syn-thesis programs are checked with SPICE-like programs to verifyperformance. For many designers this is not sufficient because itfails to satisfy many questions concerning fabricated perfor-mance, such as offset voltages, noise and DC gain, that current Fig. 3 A-D Interface Example.circuit analysis performs poorly on. A well characterized stan-dard cell library provides a good reference point for cells to becustomized with confidence in meeting critical performance Figure 3 illustrates how all analog interface points. can becharacteristics. made both controllable and observable. In figure 3a an analog circuit, illustrated by a switch and a comparator, is controlled4. Simulation Issues and observed from a digital control circuits. ,If the observed out- Simulation is verifying that the interconnection of com- put of the digital section is incorrect the problem may lie in theponents in a mixed signal design will function as intended. In a circuitry semng the switch or the comparator or in the digital cir-mixed signal design, simulation can be broken into three separate cuit processing the comparator output. Furthermore the test vec-operations: simulation of the digital portion of a chip, precision tors developed to test the digital control block will be uselesssimulation of the analog circuits and simulation of the entire sys- when combined with the analog circuits.tem. In figure 3b the circuit in 3a has been modified to include When designing and simulating the digital portion of a some digital testability circuitry. The switch connol line is fedmixed signal ASIC, special consideration should k given to the back into the test control block so its state may be read directlyanalog interface points. Specifically, all digital Jortions of the from the digital VO of the chip. A digital mux, inserted between T4-1.3
  • 4. the output of the comparator and the digital circuit, allows the paths can easily be verified by running digital test patternsoutput of the comparator to be emulated by setting the mux to through the analog paths.the test mode and supplying test patterns from the test controlsection. Typically these circuits are very easy to add to the digi-tal portion of a design. D V O P It is also worthwhile considering complementary techniques W i O Nfor the analog circuits on the chip. Critical analog signal pointsmay be multiplexed onto a common observing bus which is RVdd Tbrought out to a single pad. These techniques are more applica-tion specific since loading and crosstalk problems introduced by V2Pthe bus must be considered uniquely in each case. YEN VlO? Precision analog simulation is the process of verifying that VlONindividual analog circuit blocks meet a certain set of Se1 2specifications for that particular circuit. For example, it may be Osel 1 0necessary to verify the operation of a differential amplifier whenthe input is at one of several different common mode ranges andthe output is approaching either power rail. This performanceshould be verified at temperature extremes, minimum and max-imum power supply voltages and process variations. SPICE orsimilar circuit models for the strongest and weakest NMOS orPMOS transistors are typically available for a given process. Oneapproach to modeling process variations is to to simulate a cir-cuit with all four combinations of best and worst case SPICEmodels. This is referred to as a "four comer analysis". Addingtemperature variations produces an eight-comer analysis and Osel 2 0power supply variations produces a 16 comer analysis. Fig. 4 Analog Switches Muxing Signals. The four comer analysis is pessimistic since many of theprocess parameters contributing to transistor variations, such asoxide thickness, are correlated between NMOS and PMOStransistors. Advances in simulation techniques are required tomake more meaningful analog precision circuit simulations. Theemerging Monte Carlo simulation capability of circuit simulatorshelps automate the process of iterating multiple comer analysis.Other techniques, which model the correlations of NMOS withPMOS parameters and device variations with physical locationson a die, are needed to help model effects such as offset voltageand thermal gradieilts [21]. The third step in simulation is modeling the interaction of digital and analog components. Originally this step was done manually. Waveforms for the precision analog circuit analysis are compared manually to the digital patterns being read or gen-erated during the simulation of the digital circuits. Brute force is sometimes Used by including in the circuit simulation the transis- tor net list of as much of the digital circuitry as is necessary orpractical. Another technique that is very useful for many circuitsis the creation of digital equivalent models (DEMs) for analogcircuits that function in a digital simulation environment.Recently, commercial simulators have become available whichcan simulate analog and digital logic phenomena simultaneously. A digital equivalent model for an analog circuit models thebehavior of the circuit as if it were to be stimulated by discrete Fig. 5 Differental Amplifier.logic levels. For example, the initial die screening of a mixedsignal chip may be performed by a digital tester connected to a One of the output signal paths in figure 4 feeds thewafer probe. Most analog circuits will respond in a deterministic differential amplifier circuit illustrated in figure 5. The amplifierand predictable manner when stimulated by the digital tester. The uses an auto zeroing technique where the amplifier error voltagepurpose of the DEM is to model this expected behavior. By is sampled by CZ on one clock phase and then the voltage isusing DEMs, test vectors may be developed to verify functional- subtracted from the amplifier input on the second phase. Thoughity and continuity of many of the analog circuits. Dies that fail the opamp and switches have DEMs, they will not necessarilysuch tests may be discarded, saving expensive test time on a function when connected in this circuit. In this case, a DEM fordedicated analog tester. the entire circuit is created from standard logic primitives and is Figure 4 shows a series of analog switches muxing one of seen directly below the analog circuit schematic. The framesfour differential input channels to three different analog process- around the schematic sheets are used to indicate which schematicing channels. Since the analog switch has a DEM consisting of a is to be used for simulation and which is to be used to dnvedigital transmission gate, the complete connectivity of all signa placement and routing. To function correctly in the digital mode, T4-1.4
  • 5. rhe zero clock, Phiz, must be a logic 1 and the analog power P BEHAVIORAL MOWsupplies must be set to logic 1 and 0 (AVdd, AVss): If theseconditions are met then the allowed input states for Vpos andVneg of 1,0 or 0.1 will produce a 1 or 0 at the output, Vout.This technique can be applied through the entire analog signalpath, including the A2D converter, so the functionality of allanalog signal paths are verified. As the capabilities of true mixed mode analogjdigital simu-lation become available, it should not be assumed that they willreplace digital simulation and precision analog simulation, asdiscussed above, since digital circuits should be testable and thenumber of comers that should be examined in precision simula-tion is large. Important features for mixed signal simulation areperforming true circuit simulation with simultaneous digitalsimulation, behavioral models for analog subsystems and theability to model off-chip systems. ,- a- TRANSISTORM O D P Lcp- M 1 2 , , , ~ , , , , , , , , 8 , Fig. 6 Sigma-Delta converter. Figure 6 illustrates a sigma-delta A2D converter thatreceives its input from the differential opamp in figure 5. Thiscircuit represents a very tight interaction between analog anddigital components that is most easily simulated with mixedmode simulation tools. The digital block must generate non-overlapping clock signals for the sampling switches as well asselect the correct switches, depending upon the state of the com- Fig. 7 SaberTMOutputparator output. Using a tool such as SabegM from Analogy,behavioral models for the analog and digital circuits can be writ-ten and simulated. Later, the transistor level description for theanalog circuits can be substituted for the behavioral description.Figure 7 shows the results, from Saber, of the behavioral and fulltransistor level simulation of the circuit in figure 6.5. Analog Placement and Routing Once a set of modules has been interconnected and simu-lated, the mixed signal chip must be assembled in such a waythat the digital circuitry does not compromise the performance ofthe analog circuits. The primary consideration is preventing digi-tal and high level analog signals from coupling into noise sensi-tive analog circuits. Digital signals can couple into analog cir-cuits by one of four paths: signal coupling between digital andanalog nets routed in proximity, power supply coupling, substratecoupling [22] and analog switch coupling [23]. The fourth pathoccurs when digital power supply voltage noise, which is seenon the outputs of all digital gates, is coupled directly through thegate to channel capacitance of an analog switch controlling sensi-tive analog circuits. One design methodology, which is illustrated in figure 8and is used in Seattle Silicon’s ChipCrafter/MAX tool, addressesthe issues of signal coupling. An arbitrary net list of analog anddigital components may be entered into one or more schematics.After converting the schematic for placement and routing, all Fig. 8 ChipCrafter/MAXTMDesign Flow.analog components are separated from digital components. T4-1.5
  • 6. Separating analog and digital modules for placement and routingincreases noise isolation in two ways. First, this prevents theneed for routing the digital nets near the analog nets. The onlydigital nets that must be routed in the proximity of the analognets are the interface nets. Secondly, separating the analog anddigital power nets increases the resistance of the substrate con-nection between the analog and digital power supplies. Once theseparated analog components are placed and routed, the resultingblock is placed and routed with other blocks, analog or digital, toform the core of the chip. Typically the analog blocks communi-cate with pads via analog nets. Net weight attributes on theseanalog nets direct the final placement routines to position andorient the analog blocks such that the length of these nets areminimized. , J Phii Fig. 10 Analog Cell Placement. sensitivity routing regions are allocated above and below the row of components. As a result the high and low sensitivity nets are separated by the components in the center row. Switches are often the interface between digital control signals and the analog nets. Therefore, they are placed above and below the high and low sensitivity channels. The switches then serve to separate the digital nets from the two classes of analog nets. In a metal2 pro- cess the digital nets may be routed over the switch cells as illus- mrb.rmdc trated in figure 11. Thus switch area and clock routing area are combined to maximize the layout density. Switches have shield- Fig. 9 Analog Net Identification from Ports. ing built in as well as double buffers to minimize clock coupling. Space between the switches is filled with substrate contacts to For separated analog blocks a three step process of sensitive shield clock coupling into the substrate and to lower thenet identification, analog placement and analog routing is impedance of the coupling between the analog power supply andapplied. The process of identifying sensitive nets is illustrated the substrate.with a switched capacitor integrator in figure 9. The placementand routing tools recognize four classes of sensitivities, high,IOW, digital and neutral. The high sensitivity nets are associated - - U - 1-, - c - - - - I - I ll!lwith the virtual ground of an opamp. These are nets on whichcharge is transfered or stored and any noise coupling is indistin-guishable from signal. Low sensitivity nets are associated withthe output of opamps. These nets are always connected to acharge source or sink such as the output of an opamp. These netsare less sensitive to noise coupling due to their lower impedance.Capacitive coupling between the low and high sensitivity netsshould be avoided since this would appear as a capacitor valueerror. It is desirable to keep both classes of nets separate fromdigital nets. Neutral nets, such as power and ground, do notcarry signals. They are considered noise free and can be routednear either high or low nets. Fig. 11 Switch over-cell routing. Net sensitivity is derived from sensitivity properties on theports of all analog modules. In the first pass of a two pass algo-rithm, high, low and digital port sensitivity are transferred to thenets. Combination rules apply when two different types of ports Figure 12 illustrates a chip core that is implemented withdrive one net. For example, the output of an opamp directly driv- this layout methodology. There are actually two distinct analoging the sensitive input of a comparator results in a low sensitivity groups, the mux, diffamp and additional circuits from figures 3net. In the second iteration of the algorithm, sensitivities are pro- and 4 in one block, and the A2D from figure 6 along with apagated through the terminals with PASS properties on analog band-gap voltage reference in the other block. These circuitswitches in order to assign sensitivities to the remaining nets. blocks were separated, placed and routed, and then combinedThe designer may manually assign sensitivities in the schematic with digital timing, clock generation and 8 bit U 0 circuits tocapture environment as well. form the core of the chip. Digital nets can be seen running verti- cally over the switches between the rows of opamps and passive A number of methodologies have been developed to components. The ports on analog switches are configured suchseparate and route nets of different sensitivities [24-291. that the digital control signal may be routed without crossoversChipCrafter/MAX utilizes the methodology illustrated in figure in the digital over-switch channels. All analog nets are exported10. Analog modules such as opamps, capacitors and resistors are at the top of the core. In the upper right a number of power railsplaced adjacent to each other such that their ports face the can be seen. In addition to the digital Vdd and GND there areappropriate high or low sensitivity channels. High and low three analog power rails, I,Vdd, AVss and AGND. T4-1.6
  • 7. Fig. 12 Chip core showing analog and digital blocks.6 . Conclusion This tutorial presented a number of issues for implementing quickly maturing with some effective tools already in the market-mixed signal CMOS ASIC circuits. Process considerations place. Mixed-mode simulation is seen as an enhancement andcenter around the uadeoffs between system voltage and com- not a replacement for traditional methodologies of digitalponent requirements versus the cost and availability of different equivalent modeling and digital and precision analog simulation.processes. The use of standard cell libraries, which a vendor Finally, mixed signal methodologies need to combine digital andmay customize, continues to be the most common methodology analog blocks on the same chip. Solutions to this problem typi-for implementing analog functional blocks. As development of cally require separating analog and digital functions, identifyingcircuit synthesis, process simulation and modeling tools contin- and routing sensitive analog nets and supplying multiple, isolatedues, designers will have increased capability to specify custom power and ground lines.modules for analog design. Mixed-mode simulation tools are T4-1.7
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