E THE R LIN X P L U S3 C 5 0 5D EVE LOP E R I SRevision 3.03Com CorporationMay 2.1, 1986G U IDE
PREFACEThis document is intended for use by sophisticated softwareengineers who will either be writing application softwar...
TABLE OF CONTENTSCHAPTER 1 - HARDWARE EXTERNAL REFERENCE SPECIFICATION1.01.11.21.31.41.51.61.71.S1.91.101.111.121.131.141....
CHAPTER 3 - COMMAND INTERFACE SPECIFICATION3.0 Introduction3.1 Primary Command Block structure3.1.1 status Flag Usage for ...
CHAPTER 1HARDWARE EXTERNAL REFERENCE SPECIFICATION1.0 INTRODUCTIONThe EtherLink Plus, 3C505, is a high performance Etherne...
N8 tfhs88UJ6NO..,An stAtESI1291(DRAHI II 3941C ,: OPTIOtt :I RNt ,, I, ,--------- HOLDHOLD ACt:-INtCA -0259GETHEPNETCOPROC...
1.3 ADDRESS MAPS1.3.1 ADAPTER X/O MAPHEX Addresso100Byte/WordNA (see text)Low ByteDescription82586 CA102102102104180-18FFF...
1.4 80186 MICROPROCESSORThe 3C505 uses the Intel 80186 Microprocessor. This is a highlyintegrated 16 bit processor with 3 ...
~.6 NETWORK INTERFACEThe 3C505 network interface consists of the serial interfacethe Intel 82586 LAN controller, the SEEQ ...
The user can also connect the 3C505 to a thick Ethernetnetwork through an external transceiver such as the 3Com3CI02. If s...
Software must perform two functions for proper RAM operation:initialization and refresh. To refresh the RAM, 256 consecuti...
8 t1HZCPU CLOCK DIVI~ED BY 4, r88186TIHER 22.8 "HZDIUIDE I" seDHA REQUEST 66.7 XHZ(15 MICROSECONDS)88186DHA CHAHHEL 8,,CAS...
1.9 HOST-ADAPTER XNTERFACEThe Host and the Adapter communicate through two I/O mappedregisters: the Command Register and t...
TRANSFER I DIR I HRDY I ARDY I DESCRIPTION---------1-----1-------1-------1-------------------PIO I I 1 1 X 1 REGISTER NOT ...
In a PC, XT, or an 8 bit slot of an AT, the Data Register isconfigured as a 20 byte FIFO to the Host. The registerperforms...
Note: the Adapter and the Host may perform DMA transfersindependent of one another. That is, one may use polled I/Owhile t...
1.10 ADAPTER (80186) INTERRUPTSThe 80186 microprocessor in the 3C505 may be interrupted by bothinternal and external sourc...
Attention (NMI)When the ATTN bit is set in the Host Control Register,an NMI is generated in the 80186. This NMI is used as...
When installed in a PC, XT, or a-bit AT slot, interrupt channels3,4,5,6,7 or 9 should be used. In this situation, channel ...
LED 2The 3C505 firmware turns this LED on or off at approximatelya 1 HZ rate. It serves as a "heartbeat" signal and is avi...
CHAPTER 2HARDWARE INTERFACE SPECIFICATION2.0 INTRODUCTIONThe 3C505 Hardware Interface specification describes in detailthe...
2.1 COMMAND REGISTER+------+------+------+------+------+------+------+------+I CMD7 I CMD6 I CMDS I CMD4 I CMD3 I CMD2 I C...
2.3 HOST CONTROL REGrSTERThe Host Control Register (HCR) is an 8-bit register used by theHost to cause 3C505 hard or soft ...
DMAE DMA enableUsed in conjunction with the DIR bit, DMAE enables DMAtransfers to or from the Data Register. DMA requests ...
2.4 HOST STATUS REGISTERThe Host status Register (HSR) is an B-bit register used by theHost to determine causes of interru...
DIRDONEASF1ASF2ASF3Direction flaqThe DIR status bit is the current value of the DIR controlbit in the Host Control Registe...
2.5 HOST AUX DMA REGISTERThe Host Aux DMA Register is used to support demand mode DMAtransfers. This register is cleared u...
FLSHR586LED2LEDlASF1ASF2ASF3Flush Data RegisterSetting the FLSH bit flushes all data words from the DataRegister regardles...
2.7 ADAPTER STATUS REGISTERThe Adapter status Register (ASR) is an 8-bit register used bythe Adapter to determine causes o...
DI:R8/16SWTCDirection flaqThe DIR status bit specifies in which direction data isallowed to pass through the Data Register...
HSFlHSF2Host status Flags 1 and 2The HSF1 and HSF2 status bits are routed directly from theHost Control Register. They are...
CHAPTER 3COMMAND INTERFACE SPECIFICATION3.0 INTRODUCTIONThe 16K bytes of EPROM on the 3C505 Adapter contain firmware thats...
TABLE 1: PCB COMMAND CODE SUMMARYHOST -> 3C505 COMMANDS00:01: configure adapter memory02: configure 8258603: Ethernet addr...
3.1.1 STATUS FLAG USAGE FOR PCB TRANSFERThe Adapter uses a 64-byte circular buffer to store the hostbyte stream sent throu...
- output the remainder of the PCB similarly, reducing thetimeout period to SOOus. The Adapter remains in interruptcontext ...
3.2 PCB COMMANDS3.2.1 HOS~ TO 3C505 PCB FORMATS01H: Confiqure A~apter Memory. The Adapter allocates memoryfor the PCB comm...
03B: Ethernet Address. Requests Adapter to return the Ethernetaddress stored in its address PROM. The Adapter sends thePRO...
07H:OSH:Upload Data To Host. Operates as command code 05H,except that the Adapter uses PIO instead of DMA. Thedirection bi...
OBB: Load Multicast List. The Adapter will add the given listof multicast addresses to the 82586 multicast list. Azero len...
OFH: Sel~-Test. The Adapter will execute its self-test.Adapter, when done, responds with PCB 3FH.dbdbOFHo;command code;len...
3.2.2 3C505 TO HOST PCB FORMATS31H: Configure Adapter Response. After the Adapter has32H:33H:34H:3SH:initialized the PCB c...
38H: Packet Received Response. When the Adapter receives apacket and there is an outstanding Host request to receivea pack...
3CH: Clear Downloaded Program Response. To clear the down-loadable program memory, the Adapter reinitializesthe structures...
40H: set Address Response.address in the 82586,After the Adapter sets the Ethernetthis response is sent to the Host.dbdbdw...
3.3 SYSTEM ROM UTILITIESPrograms downloaded into the 3C505 Adapter can access the adapterresources directly or through a s...
02H: DMA Upload Request. The Adapter formats a uploadrequest PCB and sends it to the Host. If the request isacknowledged b...
ax - 5ax -= 6es:bxexdxDMA download orPIO downloadbuffer addressbuffer length in bytes to transfer (must be even)timeout in...
3.3.2 NETWORK I/O SUPPORT: INT 81BlH: Transmit Packet. To transmit a packet, this functionlinks the given packet buffer to...
3.3.3 CONFIGURATION/STATUS: INT 82H01H: confiqure A~apter .Memory. The Adapter allocatesmemory for the PCB command queue, ...
04H: set Ethernet Address. Use the supplied Ethernetaddress and issue an lA-setup command to the 82586coprocessor.ax = 4 f...
3.3.4 TIMER SUPPORT: INT 83BThe 3C505 Adapter maintains both a lOms and lSus double wordtime tick counter using two 16-bit...
3.3.5 DOWNLOAD PROGRAM SUPPORT: XNT 84HThe Adapter uses low memory for data, stack, packet buffers,and PCB command queue. ...
3.3.6 PCB COMMAND PROCESSOR: INT aSHThe adapter Command Register ISR (interrupt service routine)reads host PCBs and places...
3.3. PACKET PROCESSOR VECTOR: INT 86HThis software interrupt vector defines the address of thePacket Processor. The Packet...
03H: No Operationax - 3 NOPso that it has an opportunity to scan the receive commandqueue to check if any request has time...
APPENDIX A80186 PERIPHERAL CONTROL BLOCK PROGRAMMING·,reloc reg contumcs cont-lmcs-contmmcs-contmpcs-contpacs-conti·,equeq...
;: initialization of timer 1 registers; Hi res system Timertlcnt cent equ 0tlmaxra cont equ OffffhtOmaxrb-cont equ 0tOcntr...
APPENDIX BThis is an example of the parameters used to configure the Intel82586 LAN Coprocessor. Please refer to the "Inte...
The 3C505 EtherLinkEtherLink Plus card3C505.EXE, which canproblems on the 3C505.APPENDIX C3CSOS DIAGNOSTICDiagnostic Diske...
TEST 2Test 2 tests the interface between the Host and the Adapter usingDMA data transfers.TEST 3Test 3 performs a transmit...
FORMAT3C505 [-Ix][-Dx][-Bxxx](-#][-E][-T]PROGRAM PARAMETERSIx Test uses interrupt x, default (factory setting) isInterrupt...
RUNNING THE 3CSOS.EXE PROGRAMTo start the 3C505.EXE program, disconnect your PC from thenetwork, attach a loopback plug to...
3C501 / 3C505 DIAGNOSE PROGRAM DIFFERENCESThe 3C505.EXE diagnostic is modeled after the 3C501 version,3C501.EXE (or DIAGNO...
APPENDIX D3D DEBUGGER3D is a program for loading and debugging programs that run onthe 3C505 adapter. 3D runs on an IBM PC...
TILE AREAThe tile area is divided into a 21 by 4 array of tiles. Eachtile displays the name of a register or memory locati...
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
etherlink plus developers guide
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etherlink plus developers guide

  1. 1. E THE R LIN X P L U S3 C 5 0 5D EVE LOP E R I SRevision 3.03Com CorporationMay 2.1, 1986G U IDE
  2. 2. PREFACEThis document is intended for use by sophisticated softwareengineers who will either be writing application software thatwill talk to the 3C505, or software that will actually reside onthe card. The user is expected to have a strong background inmicrocomputer systems. It is recommended that the user browsethrough the Intel 80186 Data Sheet and the Intel Lan ComponentsUsers Manual before beginning (they are available throughIntel).The manual is divided into the following chapters:CH1~PTER 1CHAPTER 2CHAPTER 3APPENDIX AAPPENDIX BAPPENDIX CAPPENDIX EAPPENDIX FAPPENDIX GHARDWARE EXTERNAL REFERENCE SPECIFICATION (ERS)Provides a description of the 3C505 architecture,system resources and functional operation.HARDWARE INTERFACE SPECIFICATIONDescribes the programmable registers used tocontrol, configure, and communicate with the3C505.COMMAND INTERFACE SPECIFICATIONDescribes the function and use of the commandlevel interface software supplied with the card.80186 PERIPHERAL CONTROL BLOCK PROGRAMMINGProvides the values used in the 3C505 firmware toconfigure the 80186 internal resources.82586 CONFIGURATIONProvides the values used by the 3C505 firmware toconfigure the 82586.3CSOS DIAGNOSTICDescribes the operation of the 3C505 diagnosticutility program.3D DEBUGGERDescribes a host program that uses a special debugmode of the 3C505 to assist in debugging programsrunning on the card.3C50S DEVELOPERS SOFTWARE DISKETTEDescribes the contents of the disketteaccompanies the developers kit.REVISION 2.0 ROMthatDescribes changes made in Revision 2.0 ROM code.REVISION 3.0 ROMDescribes changes made in Revision 3.0 ROM code.
  3. 3. TABLE OF CONTENTSCHAPTER 1 - HARDWARE EXTERNAL REFERENCE SPECIFICATION1.01.11.21.31.41.51.61.71.S1.91.101.111.121.131.141.15IntroductionResourcesArchitectureAddress Maps1.3.1 Adapter I/O map1.3.2 Adapter memory map1.3.3 Host I/O map80186 Microprocessor82586 Ethernet CoprocessorNetwork Interface1.6.1 82586 Serial Interface1.6.2 8023 Manchester Converter1.6.3 TransceiverAdapter Firmware ROMAdapter RAMHost-Adapter Interface1.9.1 Command Register1.9.2 Data Register1~9.3 Data Register configuration1.9.4 DMA Transfers1.9.5 Status FlagsAdapter Interrupts1.10.1 Internal Interrupts1.10.2 External InterruptsHost InterruptsResetting the AdapterEthernet AddressLED IndicatorsHost ROMCHAPTER 2 - HARDWARE INTERFACE SPECIFICATION2.02.12.22.32.42.52.62.7IntroductionConunand RegisterData RegisterHost Control RegisterHost status RegisterHost Aux DMA RegisterAdapter Control RegisterAdapter status RegisterPage #1113333445555669991011121313131415151516171S181921232325
  4. 4. CHAPTER 3 - COMMAND INTERFACE SPECIFICATION3.0 Introduction3.1 Primary Command Block structure3.1.1 status Flag Usage for PCB Transfer3.1.2 Host to Adapter Request3.1.3 Adapter to Host Request or Response3.2 PCB Commands3.2.1 Host to 3C505 PCB Formats3.2.2 3C505 to Host PCB Formats3.3 System ROM Utilities3.3.1 Host I/O support: INT SOH3.3.2, Network I/O S~·;,>,:i"rt~ INT SlH3.3.3 Configuration/S ~lS. INT 82H3.3.4 Timer Support: INT 83H3.3.5 Download Program Support: INT 84H3.3.6 PCB Command Processor: INT 85H3.3.7 Packet Processor vector: INT 86H3.3.8 Idle Vector: INT 87H3.3.9 PCB Enqueue Vector: INT 8SHLIST OF FIGURESAPPENDIXAPPENDIXAPPENDIXAPPENDIXA~PENDI:XAPPENDIXAPPENDIXFiqure 1-1: 3C505 Elock DiagramFigure 1-2: DRAM RefreshA - 80186 PERIPHERAL CONTROL BLOCK PROGRAMMINGB - 82586 CONFIGURATIONC - 3CSOS DIAGNOSTICD - 3D DEBUGGERE 3C50S" DEVERLOPER S SOFTWARE DISKETTE F - REVISION 2.0 ROMG - REVISION 3.0 ROM2828303031323237414144454748495051512852545560656872
  5. 5. CHAPTER 1HARDWARE EXTERNAL REFERENCE SPECIFICATION1.0 INTRODUCTIONThe EtherLink Plus, 3C505, is a high performance Ethernetadapter for IBM PCs and compatibles. It consists of an 80186 16bit microprocessor, an 82586 Ethernet coprocessor, up to 512Kbytes of user RAM, a high speed 16 bit host interface, and ahighly integrated on-board transceiver. The 3C505 isparticularly well-suited for server and high performanceworkstation applications.1.1 RESOURCES• 8 Mhz 80186 16 bit microprocessor - no wait states* 82586 multi-packet buffer Ethernet coprocessor* 16K to 128K bytes EPROM• 128K to 512K bytes packet buffer/program memory* 8/16 bit host interface - PIO or DMA* 20 byte FIFO to maximize host/adapter data transfer* On-board "Thin Ethernet" transceiver/802.3 connector* 8K bytes host EPROM1.2 ARCHITECTUREThe 3C505 is a 16 bit microcomputer with a high performanceEthernet I/O channel and an IBM PC AT interface. The 16K bytesof on-board firmware contain software that supports,initialization, program download, and diagnostic software. The128K RAM, expandable to 512K, allows for protocol processing a.swell as offloading of application programs from the host PC. The82586 performs all Data Link functions, as well as powerful:network diagnostics. It performs all packet buffer managementfunctions and, in a typical environment, will not "drop" packets.The host interface supports high speed, 8 or 16 bit, DMAtransfers as well as programmed I/O. The interface is veryflexible, yet simple, allowing for easy programming. The 8 Mhzallows ample processing power, even on a heavily loaded network.1
  6. 6. N8 tfhs88UJ6NO..,An stAtESI1291(DRAHI II 3941C ,: OPTIOtt :I RNt ,, I, ,--------- HOLDHOLD ACt:-INtCA -0259GETHEPNETCOPROCESSOR16-120XEPROH~-------~ ETHERHF.TADDRESS9123t1ttNCHETERCOllEC"A REQXCUR7996ANDPOIIER SUPPLYIHT....................................................................._..............................· .· .· .~--~~.-- r---~.--~--~~--~ADAPTF.R UOSTDATACOHTROL COHTROL ADAPTERAHO ............ AHOREGISTDt COHttAHDS"MlUS STATUSFIFO REGISTERREGISTERS REl1lStERS 28 IYtES? • ..,ORDt082.3 COHHECTORnnH EnfERtfETCOHHECIDRHOSTCOt1HAtfOREGISTERj ~: •.•••••.•••••••••.••••.•..•! ..•••.... _ .................................................................~FIGURE 1-1OCSftS BLOCK 01 ncR,,"1~11ft,. REO9 OR 16 BIT DATA PAmHOST 1HTJ:RFACE~INTOXEPJOtr
  7. 7. 1.3 ADDRESS MAPS1.3.1 ADAPTER X/O MAPHEX Addresso100Byte/WordNA (see text)Low ByteDescription82586 CA102102102104180-18FFFOO-FFFFLow Byte ReadHigh Byte ReadHigh Byte writeWordAdapter Command RegisterAdapter Control RegisterAdapter status RegisterAdapter Control RegisterData RegisterLow ByteWo-:r:d1.3.2 ADAPTER MEMORY MAPHEX AddressOOOOO-lFFFF20000-3FFFF40000-5FFFF60000-7FFFFFCOOO-FFFFFEOOOO-FFFFFEthernet address (6 Bytes)Peripheral Control BlockDescription128K Bytes system RAM: Bank 1128K Bytes option RAM: Bank 2128K Bytes option RAM: Bank 3128K Bytes option RAM: Bank 416K Bytes system ROM *128K Bytes system ROM(If 27512s are installed)* Address lines A20-A23 of the 82586 are ignored and theInitialization Root is located at FFFF6 in system ROM.1.3.3 HOST Z/O MAPHEX Address (factory set) **Base address + 0 (300)Base address + 2 (302) ReadBase Address + 2 (302) writeBase address + 4 (304)Base address + 6 (306) ReadDescriptionHost Command RegisterHost status RegisterHost Control RegisterData Register ***Host Control Register** The address is given as an offset from the I/O baseaddress which is set using the I/O address jumpers onthe card. The factory set base address is 300H.*** Theslot(AT).Data Register is a byte wide register in an 8(PC, XT, or AT) and word wide in a 16 bit3bitslot
  8. 8. 1.4 80186 MICROPROCESSORThe 3C505 uses the Intel 80186 Microprocessor. This is a highlyintegrated 16 bit processor with 3 timers, 2 DMA channels, and aninterrupt controller on chip. The 80186 is software compatiblewith the 8086.The 80186 timing is generated by a 16Mhz crystal. An internaldivider generates an 8Mhz clock output which is used for systemtiming. All 80186 bus cycles are 4 clock cycles long, or 500nanoseconds, with a system memory bandwidth of 2 Megawords persecond. All DMA transfers require 2 bus cycles, or 1 microsecond.1.5 82586 ETHERNET COPROCESSORThe 82586 is a high performance, intelligent communicationsprocessor resRonsible for all network related tasks, includingframe reception and transmission, error logging, and diagnostics.The 82586 has two interfaces: a parallel system bus interface tocommunicate with the 80186 and to retrieve and store packet datain system RAM; and a serial interface to transmit and receivedata from the network. The serial interface is described insection 1.6, Network Interface. The 82586 bus interface operatesfrom the 8 Mhz system clock and all bus cycles are 500nanoseconds.The 80186 and the 82586 operate in a shared bus configurationusing the HOLD/HOLDA protocol. This configuration is described indetail in the Intel Lan Components Users Manual. In this mode,only one of the processors can use the system bus at a time. Allinterprocessor communications are via the system RAM. The 80186can initiate a transaction by asserting the CA (ChannelAttention) input to the 82586. A read or write to I/O location00 will cause an active transition on the CA input. The 82586initiates a transaction by asserting the 80186 INT1 input.The 82586 can require the bus to access system RAM. in threeinstances:1. To read or update the SCB (System Control Block).2. To transmit a packet.3. To receive a packet.When receiving or transmitting, the 82586 uses approximately 35%of the system bandwidth, or 715 KW/second. Thus programexecution and DMA transfers, although slowed, do not halt.The Adapter (80186) can reset the 82586 by asserting the R586 bitin the Adapter Control Register. The 82586 remains in the resetstate un.til this bit is cleared.4
  9. 9. ~.6 NETWORK INTERFACEThe 3C505 network interface consists of the serial interfacethe Intel 82586 LAN controller, the SEEQ 8023 ManchesterConverter, and an on-board transceiver using the AMDTransceiver IC.~.6.1 82586 SERIAL INTERFACEonCode7996The 82586 perfo~s all parallel to serial and serial toparallel convers~on during packet transmission andreception. During transmit, parallel data is retrieved fromthe Adapter RAM through the 82586 bus interface. The 82586serializes the data, inserts the preamble, source anddestination fields, appends a CRC field to the "packet", andoutputs the bit stream. The 82586 also performs the CSMA/CDlink management algorithm according to the IEEE 802.3standard. During reception, the 82586 strips off thepreamble and compares the destination address field with thestation address to see if the frame should be received. Ifso, the serial bit stream is converted into bytes and storedin the Adapter RAM.1.6.2 8023 MANCHESTER CONVERTERThe 8023 is responsible for the Manchester encoding anddecoding of the serial bit stream between the 82586 and thetransceiver. It also supplies the transmit and receiveclocks to the 82586 serial interface. A watchdog timer onthe IC prevents continuous transmission of more than 25milliseconds, thus limiting the maximum packet size toapproximately 3lk bytes.For diagnostic purposes, the 8023 can be placed in "loopbackmode" whereby the transmitted data is internally routed tothe receive section. This is useful for isolatingtransceiver problems. Enable loopback by clearing theLoopback bit in the Adapter Control Register. Refer to the3C505 Hardware Interface Specification, Chapter 2.~.6.3 TRANSCEIVERThe 3C505 onboard transceiver physically connects the 3C505to the "Thin Ethernet" coax cable. It performs thenecessary signal conditioning as well as collisiondetection.5
  10. 10. The user can also connect the 3C505 to a thick Ethernetnetwork through an external transceiver such as the 3Com3CI02. If so, the user must disable the onboard transceiverand enable the 15 pin connecter on the backplate of thecard. To do so, the transceiver select plug in the cardmust be moved from the BNC position to the DIX position.The EtherLink Plust Installation Guide, included with the3C505, illustrates this procedure.:1,,7 ADAPTER FIRMWARE ROMThe 3C505 contains 16K bytes of firmware contained in two 8Kx8,2764 type ROMs. These ROMs can be replac~d by 27128, 27256, or27512 ROMs for up to 128k bytes of firmware. The ROMs must havea maximum address access time of 250 nanoseconds or less.The 3C505 ROM firmware performs self-test, initialization andconfiguration, and DRAM refresh. It also provides, through acommand block interface, a set of functions which supportHost/Adapter I/O, network interfacing and execution ofdownloaded programs. Refer to the 3C505 Command InterfaceSpecification, Chapter 3, for more details.The system ROM is mapped to address space FCOOOH-FFFFFH (EOOOOH-FFFFFH if 128k bytes are used) and is accessible to both the 80186and 82586. The 82586 only accesses ROM following an 82586 resetto fetch the initialization root.1.8 ADAPTER RAMThe 3C505 contains 128K bytes of dynamic memory organized in a64K x 16 configuration. Three additional 128K banks can beinstalled for 256K, 384K, or 512K bytes of RAM memory. Each bankconsists of four 64K x 4 DRAMs. The first additional bank must beinstalled in socketed 10cations"-U31," U33, U35, and "037. Thesecond additional bank must be soldered into locations U40, U42,U44, and U46. The third additional bank must be soldered intolocations U41, U43, U45, and U47. These devices must have amaximum RAS access time of 150 nanoseconds and maximum CAS accesstime of 75 nanoseconds. In addition, these RAMs must support"CAS before RAS refresh", described below. These parts arecurrently available from Hitachi, NEC, Fujitsu, Intel, TexasInstruments, and Mitsubishi.The system RAM is accessible to the 80186 and 82586 and is usedfor both packet buffering and program storage. No physicalpartitioning or protection mechanism is used. The RAM is mappedinto the Adapter memory space 0-7FFFFH, with bank 1 occupying 0-IFFFFH, bank 2 occupying 20000-3FFFFH, bank 3 occupying 40000-5FFFFH, and bank 4 occupying 60000-7FFFFH.6
  11. 11. Software must perform two functions for proper RAM operation:initialization and refresh. To refresh the RAM, 256 consecutivelocations in each bank must be accessed every 4 milliseconds.Data loss will occur if refresh is not performed. Theinitialization procedure depends on the refresh technique used.To facilitate refresh, the 3C505 contains hardware which utilizesthe "CAS before RAS" refresh feature of the DRAMs. In this mode,the RAMs generate the refresh address internally after each CASbefore RAS cycle, and the internal address counter increments sothat the next CAS before RAS cycle will refresh the next address.A read or write to I/O location 80H will produce a CAS before RAScycle in all banks simultaneously. The 80186 PCSl PeripheralChip Select output is programmed for this range. NOTE: A CASbefore RAS cycle, read or write, does not corrupt RAM data.To increase reliability and to free the 80186 from involvement inRAM refresh, the 3C505 firmware uses 80186 Timer 2 and DY~Channel 0 to automatically generate refresh cycles. The timercauses a DMA cycle to occur every 30 microseconds. Each DMA cycleperforms an I/O read and write to location 80H. Thus each DMAcycle refreshes two memory locations. The DMA controller is notprogrammed to "stop on terminal count" so that refresh, onceinitialized, will continue without any CPU involvement. Usingthis technique, refresh consumes 3.3% of the memory bandwidth.The timer generated DMA will only produce one DMA cycle so thatburst mode refresh cannot be used.Upon power-up, the 80186 must wait 200 microseconds and thenperform 8 RAM "initialization" cycles. If CAS before RAS refreshis to be used, then 8 refresh cycles (a read or write to I/Olocation 80H) will initialize all RAM. If CAS before RAS refreshis not used, then 8 reads or writes to any location in each ofthe installed banks of memory will initialize the RAM.7
  12. 12. 8 t1HZCPU CLOCK DIVI~ED BY 4, r88186TIHER 22.8 "HZDIUIDE I" seDHA REQUEST 66.7 XHZ(15 MICROSECONDS)88186DHA CHAHHEL 8,,CAS BE~ORE RAS CAS !EFORE P.ASl REFRESH n REFRESH IREAD DUMMV 110 &.JRITE DUMM~ 110EACH DHA CYCLEFIGURE 1-23C5BS DRAM REFRESH8
  13. 13. 1.9 HOST-ADAPTER XNTERFACEThe Host and the Adapter communicate through two I/O mappedregisters: the Command Register and the Data Register. Inaddition, each side has a Control Register and a status Registerwhare are used for transfer handshaking and interfaceconfiguring. A detailed bit level description of these registersis found in the 3C505 Hardware Interface Specification, Chapter2. The interface requires 16 locations in the Host I/O addressspace. Jumpers are used to position the base address.1.9.1 COMMAND REGISTERThe Command Register is a full duplex byte-wide registerused to transfer commands and small amounts of data betweenthe Host and the Adapter. The register can be polled usingthe Command Register Empty (ACRE and HCRE) and CommandRegister Full (ACRF and HCRF) bits in the Host and Adapterstatus Registers. Alternately, the Command Register can beinterrupt driven, so that an interrupt is generated to theHost or Adapter when the opposing side has loaded a byteinto the Command Register. Refer to section 1.10 oninterrupts for more information.1.9.2 DATA REGISTERThe Data Register is a half duplex 20 byte FIFO designed forhigh speed bulk data transfers between the Host and theAdapter. The direction of the data transfer is controlled ~ythe DIR bit in the Host Control Register. If the DIR bit ~scleared (0), data transfer is from the Host to the Adapter,which is referred to as a data download. If the DIR bit isset (1), data transfer is from the Adapter to the Host andreferred to an upload. The state of the DIR bit can be readin both the Host and Adapter status Registers.The Data Register supports both polled I/O and DMA datatransfers. In polled operation, the state of the DataRegister can be determined by reading the Data Register Readybit (HRDY and ARDY) in the Host and Adapter status registers.The meaning of the Ready Bit is determined by its state andthe state of the DIR Bit.9
  14. 14. TRANSFER I DIR I HRDY I ARDY I DESCRIPTION---------1-----1-------1-------1-------------------PIO I I 1 1 X 1 REGISTER NOT FULLDOWNLOAD 1 0 1-------1-------1-------------------I 1 X 1 1 1REGISTER NOT EMPTY---------1-----1-------1-------1-------------------PIO I X I 1 I REGISTER NOT FULLUPLOAD I 1 1-------1-------1-------------------I 1 1 I X 1 REGISTER NOT EMPTY---------1-----1-------1-------1-------------------REGISTER NOT FULL ---> WRITE DATAREGISTER NOT EMPTY ....-> !<Lj:~D DATATo clear a stuck byte from the Data Register, or to ensurethat the register is in a known empty state, the FLSH(Flush) bit in the Host and Adapter Control Register isused. By setting and resetting the FLSH Bit, the DataRegister Ready Flag is forced to the empty state (the datain the FIFO is not actually cleared). Either the Host orthe Adapter can use this bit, regardless of the state of theDIR Bit.Careful attention should be paid in the use of the DIR bit.Incorrect and confusing results occur if the bit is not setcorrectly. The DIR must be in its correct state prior toenabling DMA transfers. When changing the state of the DIRbit from download to upload, the Host must make sure thatthe Adapter has actually completed the download, i.e., theFIFO is empty. One solution is to change the DIR bit only aspart of the command block sequence. The 3C505 firmwarechanges the DIR bit after the Adapter has accepted the firstword of a command block. This indicates that the Adapter hascompleted execution of the last command block.1.9.3 DATA REGISTER CONFIGURATIONTo the Adapter, the Data Register is always a 16 bit wideFIFO, 10 words deep. Only 16 bit data transfers arepermitted (AO and BHE are ignored). However, to the Host,the Data Register is configured as either an 8 bit FIFO, 20bytes deep, or a 16 bit FIFO, 10 words deep, depending onwhere it is installed. The register is automaticallyconfigured and no jumpers need be set. Also, the Adapterdoes not need to know whether it is installed in an 8 or a16 bit slot.The Data R7gister is configured as a 16 bit register wheninstalled 1n a 16 bit I/O slot of an AT. Only wordtransfers are permitted (AO and BHE are ignored) and only 16bit AT DMA channels (5,6,7) can be used.10
  15. 15. In a PC, XT, or an 8 bit slot of an AT, the Data Register isconfigured as a 20 byte FIFO to the Host. The registerperforms byte to word conversion so that the 80186 alwaysperforms word I/O to the Data Register and Adapterperformance is not reduced in 8 bit systems. The Host mustalways transfer an even number of bytes to the register; theAdapter Data Register Ready flag (ARDY) indicates thepresence of words, not bytes. An odd byte will get "stuck"in the register because the Adapter will not know of itspresence. In Adapter to Host transfers, word to byteconversion is performed. A byte cannot get stuck in thisdirection because the Host Data Registe~ Ready flag (HRDY)indicates the presence of bytes.~.9.4 DMA TRANSFERDMA transfers by the Host to and from the Data Register areenabled using the DMAE bit in the Host Control Register.Since the DMA channel floats when this bit is cleared,caution should be taken to ensure that this channel in thePC DMA controller is not enabled until the DMAE bit is set.When the DMAE bit is cleared, another I/O card may use thesame DMA channel.TRANSFER I DIR I HRDY I ARDY I DESCRIPTION---------1-----1-------1-------1-------------------------DMA I 1 1 I X I WRITE REQUEST TO HOSTDOWNLOAD 1 0 1-------1-------1-------------------------1 1 X 1 1 1 READ REQUEST TO ADAPTER---------1-----1-------1-------1-------------------------DMA 1 I X I 1 I WRITE REQUEST TO ADAPTERtJJ?WAD ,I 1 i ------- f ------- I -------------------------1 I 1 I X 1 READ REQUEST TO HOST---------1-----1-------1-------1-------------------------The 3C505 can be programmed to generate an interrupt to theHost after the last cycle of a Host DMA transfer using theTCEN bit in the Host Control Register. Refer to the sectionon interrupts for more information.~he Adapter performs DMA transfers to and from the DataRegister on 80186 DY~ Channell. Both the DMA ChannelEnable and the DMA DONE interrupt are controlled byprogramming registers internal to the 80186. The DY~Channel 1 input to the 80186 is never in a floating state.
  16. 16. Note: the Adapter and the Host may perform DMA transfersindependent of one another. That is, one may use polled I/Owhile the other performs DMA. There is little reason forthe Adapter to use polled I/O and the 3C505 firmware alwaysuses DMA.The 3C505 contains hardware to support Host "demand mode"DMA transfers in PCs where this mode is supported. If theBurst (BRST) bit in the Aux DMA Register is not set, the3C505 will transfer 9 bytes/words and then relinquish theDMA channel for one host CPU cycle. This will allow theHost to refresh its own system DRAM if necessary. The 3C505will then transfer another 9 bytes/words, and so on. If theBurst bit is set, this pause will not occur. The Burst bithas no effect if single cycle DMA is used. ThUS, if theDMAE bit is set, the DMA request inp~t to the host PC willgo inactive under the following conditions:1. The entire Host DMA transfer is completed2. The Data Register FIFO is temporarily full/emptydepending bn the transfer direction.3. The Burst bit is not set and 9 DMA transfers haveoccured since the last DMA pause.1.9.5 STATOS FLAGSThe Host and Adapter also communicate using general purposestatus Flags. The Adapter has three flags, ASF1, ASF2, andASF3, which are programmed by the Adapter Control Registerand directly observable by the Host status Register. TheHost has two status Flags, HSFl and HSF2, which areprogrammed by the Host Control Register and observablethrough the Adapter status Register. The status Flags areused for synchronization, command execution and completioncodes, and other assorted tasks. They are not decoded bythe hardware in any way.12
  17. 17. 1.10 ADAPTER (80186) INTERRUPTSThe 80186 microprocessor in the 3C505 may be interrupted by bothinternal and external sources.1.10.1 INTERNAL INTERRUPTSA brief description of how the 3C505 firmware usesinternal interrupts follows. These include Timer, DMA, andsoftware generated interrupts. Refer to the 80186 DataSheet for programming details.DMA Channel 1 Done InterruptThis is used to generate an interrupt after the lastcycle of a DMA transfer to or from the Data Register.Timer InterruptAn interrupt is generated every 10 millisecond fromTimer o. The interrupt is used for general purposecounting and timeouts.1.10.2 EXTERNAL INTERRUPTSThere are three sources of external interrupts to the 80186:Command Register Full (INT 0), 82586 Int (INT1), andAttention (NMI). Since each interrupt has a unique channel,there is no need for a corresponding status bit to indicatethe cause of the interrupt. Except for NMI, which cannot bedisabled, the interrupts are enabled or disabled by settingthe appropriate bit in the Interrupt Mask Register in the80186. These inputs never "float" so that these channelscan be enabled at any time. All channels are programmedpositive edge triggered.Command Register Full (INTO)I£ enabled, an interrupt will be generated to the 80186when the Host loads a byte in the command register.This condition is also reflected by the HCRF (HostCommand Register Full) bit in the adapter statusregister. The Command Register Full interrupt andstatus bit are cleared when the 80186 reads the bytefrom the Command Register82586 INT (INT1)This input is tied directly to the INT output on the82586. If enabled, the 80186 will be interrupted bythe 82586 after the SCB has been modified by the 82586 .. Refer to the 82586 data sheet for more information.13
  18. 18. Attention (NMI)When the ATTN bit is set in the Host Control Register,an NMI is generated in the 80186. This NMI is used asa "soft" reset to bring the adapter back to a knownstate after an interface error occurs. The NMI ispositive edge triggered and the ATTN bit must bebrought from low to high to force the NMI.1.11 HOST INTERRUPTSThe 3C505 can be programmed to interrupt the Host in twosituations: DMA complete and Command Register Full. Only one PCinterrupt channel is used.Host DMA DoneBy setting the TCEN (Terminal Count Enable) bit in the HostControl Register, an interrupt will be generated to the Hostafter the last cycle of a DMA transfer to or from the DataRegister. If the Command Register Full interrupt is alsoenabled, the Done bit in the host status register should beused to determine if a DMA Done was the source of theinterrupt. The DMA Done interrupt and Done status bit arecleared by disabling the DMA channel using the DMAE (DMAenable) bit in the Host Control Register.Command Register FullBy setting the CMDE (Command Enable) bit in the Host ControlRegister, an interrupt will be generated to the Host whenthe Adapter writes a byte in the Command Register. If theDMA Done interrupt is also enabled, the ACRF (AdapterCommand Register Full) bit in the Host status Registershould be used to determine the source of the inte~rupt.The Command Register Full interrupt and ACRF bit are clearedwhen the Host reads the byte from the Command Register.Care must be taken when enabling and disabling the 3C505interrupts. If both interrupt sources are disabled, theinterrupt channel is floated and can cause spurious interrupts ifthe PC PIC channel is not also disabled. To prevent this, alwaysturn the PIC channel off before disabling 3C505 interrupts, andenable 3C505 interrupts before enabling the PIC channel. Whenboth 3C505 interrupts are disabled, the interrupt channel can beused by another I/O card.14
  19. 19. When installed in a PC, XT, or a-bit AT slot, interrupt channels3,4,5,6,7 or 9 should be used. In this situation, channel 9 isequivalent to channel 2. In an a 16-bit AT slot, any interruptchannel can be used.1.12 RESETTING THE ADAPTERPower On ResetUpon power up, the 3C505 is put in reset state. Both the80186 and 82586 are reset, the Command and Data Registersstatus indicate empty, and both the Host and Adapter ControlRegisters are cleared.Adapter ResetThe Host can reset the adapter by simultaneously settingboth the ATTN bit and the FLSH bit in the Host ControlRegister. This reset is similar to the power on reset exceptthat the Host Control Register is not affected. The Adapterwill remain reset until the ATTN and FLSH bits are reset.Note: After either of the above "hard" resets, the adapterfirmware performs configuration and self-test routines whichseveral seconds. The completion of these tasks is indicatedtransition in the Host status Flags from state 3 to stateVisually, this is indicated by LED #1 turning off.1.13 ETHERNET ADDRESSlastby ao.The Adapter Ethernet station address resides in a PROM in theAdapter I/O space. The twelve digits are contained in the lowbyte of the six consecutive words starting at location 180H.1.14 LED INDICATORSThe Adapter contains two LEDs which are enabled by the LEDl andLED2 bits in the Adapter Control Register. The LEDs are activehigh so that setting the bit turns the LED on and clearing thebit turns the LED off.LED t1The 3C505 firmware turns this LED on during the self t.estand initialization following a hard reset. The LED isturned off at the conclusion of these routines. Applicationsoftware may call 3C505 firmware routines to use the LED fordebug and status indications.15
  20. 20. LED 2The 3C505 firmware turns this LED on or off at approximatelya 1 HZ rate. It serves as a "heartbeat" signal and is avisual indicator that the card is alive. If the LED shouldstop blinking, a software or hardware error has occurred. Itis not recommended that application software use this LED.CAUTION! When using 3C505 firmware, downloaded software mustcontrol the LEOs by calls to the firmware routines provided inROM. Otherwise incorrect operation will result.1. 15 :i}:~ST ROMA socket is provided on the card for an SK x S (2764) ROM whichresides in the Host memory space. This ROM can be used forapplications such as BIOS extensions. The maximum address accesstime for these devices must not be greater than ~50 nanoseconds.The ROM is only accessible to the Host. Note - The PC AT willexecute from 8 bit ROMs on I/O cards.The ROM can be mapped on any 8K boundary in the Host addressspace. The base address for the ROM is programmed using thememory address jumpers on the card. The 3C505 does not supportDMA access to this ROM. Incorrect data will be read.To enable the ROM, set the Enable jumper on the card must to theON (0) position. If no ROM is present, or to disable a ROM whichis present, place the jumper should in the off (1) position.16
  21. 21. CHAPTER 2HARDWARE INTERFACE SPECIFICATION2.0 INTRODUCTIONThe 3C505 Hardware Interface specification describes in detailthe 3C505 interface registers accessible by the PC host and the3C505 processor.Briefly, the Host and 3C505 communicate using four registers:Command, Data, status, and control. The Command Register is fullduplex and used for command block transfers. The Data Registeris a half duplex, 16-bit wide FIFO, and can-be used with a DMAchannel for efficient bulk data transfer. The Control Registerallows programmed configuration of the interface. The statusRegister contains interface state flags and programmable flags.The Host and Adapter access these registers in their I/O spacerelative to a base I/O address:CommandDatastatusControlControlAUX DMABase OffsetsI Host I Adapter I Access I-----------------------------------1I 0 I 0 I Read/Write II 4 I 4 I Read/Write II 2 I 3 I Read only II 6 I 3 I write only II 6 I 2 I Read only * II 2 I X I write only IThe Host base I/O address can be modified with jumpers, while theAdapter base address is fixed at 100 hex. Refer to section 1.3,Address Maps, for more detail.Refer to the 3C505 Hardware External Reference Specification inChapter 1 for a more detailed explanation of the hardwarearchitecture. And also refer to the 3C505 Command InterfaceSpecification in Chapter 3 for a description of how thisinterface can be programmed.* The Host and Adapter will read the contents of their own ControlRegisters.17
  22. 22. 2.1 COMMAND REGISTER+------+------+------+------+------+------+------+------+I CMD7 I CMD6 I CMDS I CMD4 I CMD3 I CMD2 I CMD1 I CMDO I+------+------+------+------+------+------+------+------+The Command Register (CMDR) is a bidirectional 8-bitregister used for passage of primary command blocks betweenHost and the 3C50S. Programmed and interrupt driven I/O canused to read/write this register; DMA is not supported.2.2 DATA REGISTER+------+------+------+------+------+------+-----~+------+I DR1S I DR14 I DR13 I •••• • ••• I DR2 I DR1 I DRO I+------+------+------+------+------+------+------+------+datathebeThe Data Register (DR) is a half duplex, 20 byte FIFO used forhigh speed data transfers. DMA or programmed I/O methods can beused to read/write this register; interrupt driven I/O is notsupported. . From an 8-bit Host, the Data Register appears as an8-bit wide register. Only an even number of bytes can betransferred. To the Adapter or to a 16-bit Host, the registerappears as a 16-bit wide register (10 words deep) and only wordtransfers are supported.18
  23. 23. 2.3 HOST CONTROL REGrSTERThe Host Control Register (HCR) is an 8-bit register used by theHost to cause 3C505 hard or soft resets, to control interrupt andDMA requests to the Host, and to provide synchronization controlsignals between the PC Host and 3C505 processors. The contentsof this register can be read back by the Host. This register iscleared upon power-up.+------+------+------+------+------+------+------+------+I ATTN I FLSH I DMAE I DIR I TCEN I CMDE I HSF2 I HSF1 I+------+------+------+------+------+------+------+------+ATTNFLSH****AttentionWhen the Host sets ATTN, a non-maskable interrupt (NMI) isgenerated to the Adapters 80186 processor. The HostControl and status Registers on the Adapter are notaffected. The interpretation of NMI is intended to be"soft reset", where the Adapter resets itself into an idlestate ready to accept commands.Flush Data ReqisterSetting the FLSH bit flushes all data words from the DataRegister regardless of the state of the DIR (direction)bit. The FIFO assumes an empty condition, although theactual data in the FIFO is unchanged. The Data Registerremains in this state until the FLSH bit is cleared.Reset a~apterWhen the Host simultaneously sets both ATTN and FLSH, theadapter hardware decodes it as a "hard reset". The DataRegister, Adapter status and Control Registers, and theHost Status Register are reset. A reset signal to theS0186 processor is generated which resets all 80186internal registers and transfers control to the powerupreset location. The 82586 is also reset. The Adapterwill stay in this reset state until the ATTN and FLSHbits are cleared.19
  24. 24. DMAE DMA enableUsed in conjunction with the DIR bit, DMAE enables DMAtransfers to or from the Data Register. DMA requests tothe Host can occur only if this bit is set. with the DMAEbit cleared, the DMA request output to the Host "floats"and another I/O card may use the channel.DiR Direction flagTCENCMDEHSFlHSF2The Host has exclusive control of the direction of thehalf-duplex Data Register. If DIR is clear, datatransfers are to the Adapter (download). If DIR is set,data transfp-s are to the Host (upload)~CAUTiONl After completing a download, the Host must makesure that the Adapter has completed its transfer (FIFOempty) before changing the DIR bit to the upload state.This c~n take 1 to 30 microseconds, depending on thenetwork activity occurring on the Adapter.Terminal Count interrupt enableTCEN enables an interrupt to the Host at the completion ofa DMA transfer to or from the Data Register.Command Register interrupt enableThe CMDE control bit allows the Host to be interruptedwhen the Adapter has written the Command Register. Whenneither TCEN nor CMDE are set, the Host should disable theinterrupt channel because the interrupt request line willfloat.Host status Flags 1 and 2The HSFl and HSF2 status bits are routed directly to theAdapter status Register. They are general purpose innature and can be used by Host and Adapter interfacedrivers to synchronize data transfer or pass commandcompletion .status.20
  25. 25. 2.4 HOST STATUS REGISTERThe Host status Register (HSR) is an B-bit register used by theHost to determine causes of interrupts, check status of both Dataand Command Register programmed I/O, and provide a way tosynchronize the Host and 3C505 processors.+------+------+------+------+------+------+------+------+I HRDY I HCRE I ACRF I DIR I DONE I ASFJ I ASF2 I ASF1 I+------+------+------+------+------+------+------+------+HRDYHCREACRFData Register readynotWhensetfortheThe HRDY bit indicates whether the Data Register isfull or not empty, depending on the Direction Flag.the Host is downloading data to the Adapter, HRDYmeans that the Data Register is not full, i.e., readymore data. When the Host is uploading data fromAdapter, HRDY set means that the Data Register isempty, i.e., input data is available.notHost Command Register emptyThe HCRE flag is used to handshake data transfer throughthe Command Register from the Host to the Adapter. Whenthe Host writes the Command Register, HCRE is clearedindicating the register is not empty. When the Adapterhas read the Co~~and Register, HCRE is set, indicatingthat the register is empty.Adapter Command Register fullThe ACRF flag is used to handshake data transfer throughthe Command Register from the Adapter to the Host. Whenthe Adapter writes the Command Register, ACRF is set,indicating the register is full. When the Host reads theCommand Register, ACRF is cleared, indicating that theregister is not full.21
  26. 26. DIRDONEASF1ASF2ASF3Direction flaqThe DIR status bit is the current value of the DIR controlbit in the Host Control Register. It specifies in whichdirection data is allowed to pass through the DataRegister. When DIR is clear, transfers are from the Hostto the Adapter (download). When DIR is set, transfers arefrom the the Adapter to the Host (upload). The DIR bitalso determines how HRDY should be interpreted.DMA doneThe DONE flag is set when a DMA transfer between the Hostand the Data Register is complete. An interrupt to theHost will also be generated if the TCEN bit in the HostCOt,trol Register is set. The DONE bi~ is cleared byclearing the DMAE bit in the Host Cont~ol Register.Adapter status Flags 1, 2 , 3The ASF1, 2 and 3 status bits are routed directly to theHost status Register from the Adapter Control Register.They are general purpose in nature and can be used by Hostand Adapter interface drivers to synchronize data transferor pass command completion status.CAUTION! These bits are set asynchronously with respectto the Host processor and it is possible to read thesebits while they are in transition. This is only a problemif the state of more than one flag is testedsimultaneously. For example, if the present state is ASFl~ ASF2 - 0 and you are testing for state ASF1=1 andASF2=O, you could actully read this state during a statetransition to ASFl = ASF2 =1, if the ASF2 flag changedstate slower than the ASF1 flag. The solution is to readthe Adapter status Register twice when checking the stateof more than one flag to insure that you have not read aflag in transition.22
  27. 27. 2.5 HOST AUX DMA REGISTERThe Host Aux DMA Register is used to support demand mode DMAtransfers. This register is cleared upon power-up.+-----+-------+-------+-------+-------+--------+-------+-------+I 0 I 0 I 0 I 0 I 0 I 0 I 0 I BRST I+-----+-------+-------+-------+-------+--------+-------+-------+BRST DMA BurstIf the Burst bit is not set, demand mode DMA transfers bythe· Host will pause every 9 transfers to allow the PC torefresh its dynamic RAMs. If the B~rst bit is set, nosuch pause will occur. This bit has no effect duringsingle cycle DMA transfers.CAUTION! Do not use demand mode DMA uploads in PCs or XT typePCs. Data errors will occur!2.6 ADAPTER CONTROL REGISTERThe Adapter Control Register (ACR) is an 8-bit register used bythe Adapter to reset the 82586, flush the Data Register, blinkthe LEDs, and set the state of synchronization flags between thePC Host and 3C505 processor. The contents of this register canbe read back by the Adapter. This register is cleared upon power-up.+------+------+------+------+------+------+------+------+I LPBK I FLSH I R586 I LED2 I LEDl I ASF3 I ASF2 I ASFl I+------+------+------+------+------+------+------+------+LPBK Loopback controlLPBK specifies a diagnostic mode in which transmitted datais not placed on the network, but is looped back into theAdapter. This controls loopback at the 8023 ManchesterCode Converter. If CLEAR, loopback mode is enabled.23
  28. 28. FLSHR586LED2LEDlASF1ASF2ASF3Flush Data RegisterSetting the FLSH bit flushes all data words from the DataRegister regardless of the state of the DIR (direction)bit. The FIFO assumes an empty condition, although theactual data in the FIFO is unchanged. The Data Registerremains in this state until the FLSH bit is cleared.Reset 82586When the Adapter sets R586, a hardware reset is applied tothe 82586 coprocessor chip. All major 82586 hardwarecomponents are reset to an inactive state and remain resetuntil R586 is cleared. The 82586 then waits for theChannel Attention signal before completing initialization.LED control bit 2LED2 determines the state of LED 2. Setting the bit turnsthe LED on, and clearing the bit turns the LED off.LED control bit 1LED1 determines the state of LED 1. Setting the bit turnsthe LED on, and clearing the bit turns the LED off.Adapter status Flags 1, 2 and 3The ASF1, 2 and 3 status bits are routed directly to theHost Status Register., They are general purpose in natureand can be used by Host and Adapter interface drivers tosynchronize data transfer or pass command completionstatus.24
  29. 29. 2.7 ADAPTER STATUS REGISTERThe Adapter status Register (ASR) is an 8-bit register used bythe Adapter to determine causes of interrupts, check status ofboth Data and Command Register programmed I/O, and provide a wayto synchronize the Host and 3C505 processors.+------+------+------+------+------+------+------+------+I ARDY I ACRE I HCRF I DIR I 8/16 I SWTC I HSF2 I HSF1 I+------+------+------+------+------+-----~+------+------+ARDYACREECRFData Register readyThe ARDY bit indicates whether the Data Register is notfull or not empty, depending on the Direction Flag. Whenthe Host is downloading data to the Adapter~ ARDY setmeans that the Data Register is not empty, ~.e., inputdata is available. When the Adapter is uploading data tothe Host, ARDY set means that the Data Register is notfull, i.e., ready to accept more data.Adapter Command Reqister emptyThe ACRE flag is used to handshake data transfer throughthe Command Register from the Adapter to the Host. Whenthe Adapter writes the Command Register, ACRE is cleared,indicating that the register is not empty. When the Hostreads the Command Register, ACRE is set, indicating thatthe register is empty.Host Command Register fullThe HCRF flag is used to handshake data transfer throughthe Command Register from the Host to the Adapter. Whenthe Host writes the Command Register, HCRF is set,indicating the register is full. When the Adapter readsthe COmInand Register, HCRF is cleared, indicating that theregister is not full.25
  30. 30. DI:R8/16SWTCDirection flaqThe DIR status bit specifies in which direction data isallowed to pass through the Data Register. The directionis settable only by the Host using the DIR bit in the HostControl Register. When DIR is clear, transfers are fromthe Host to the Adapter. When DIR is set, transfers arefrom the Adapter to the Host.,8/16 bitThe 8/16 bit flag indicates whether the Adapter isinstalled in an 8 or 16 bit expansion slot. If the 8/16bit is set, the Adapter is in a sixteen bit slot, i.e., p~IBM AT or AT-compatible.External switchThe SWTC flag in the Adapter status Register representsthe state of the TEST jumper on the Adapter. When theTEST jumper is set to one, the Revision 3.0 ROM code will:1. Ignore powerup memory test error. Memory errorsdetected during powerup normally prevent the Adapterfrom entering the main ROM idle loop. Ignoring errorsis useful when using ICE systems that need to modifythe NMI vector location in order to operate.2. Ignore ROM checksum error. During ROM development, itis convenient not to checksum since the code ischanging frequently.3. Install 3D interrupt vectors. The interrupt vectorsknown as "exceptions" (basically INT 0 to 7) and allunused interrupt vectors are made to point to the 3Dslave in the Revision 2.0 ROM. When an exceptionoccurs, 3D becomes active and attempts to communicatewith the 3D Debugger program.26
  31. 31. HSFlHSF2Host status Flags 1 and 2The HSF1 and HSF2 status bits are routed directly from theHost Control Register. They are general purpose in natureand can be used by Host and Adapter interface drivers tosynchronize data transfer or pass command completionstatus.CAUTION! These bits are set asynchronously with respect tothe 80186 and it is possible to read these bits while theyare in transition. This is only a problem if the state ofboth flags is tested simultaneously. For example, if thepresent state is HSF1 = HSF2 = 0 and we are testing forstate HSF1=1 and HSF2=0, we could actully read this stateduring a state transition to HSFl = HSf2 =1, if the HSF2flag changed state slower than the HSF1 flag. The solutionis to read the Host status Register twice when checkingthe state of both flags to insure that you have not read aflag in transition.27
  32. 32. CHAPTER 3COMMAND INTERFACE SPECIFICATION3.0 INTRODUCTIONThe 16K bytes of EPROM on the 3C505 Adapter contain firmware thatsupport the following:* Bootup initialization and diagnostics* Software memory refresh* Network I/O* Packet buffer control* Host I/O* System timer* Host PC primary command interfaceAfter Adapter bootup initialization, host-based applicationprograms or drivers can access the network or resources of theAdapter through the primary command block interface described insections 3.1 and 3.2. Programs downloaded into the Adapter canaccess the Adapter resources directly or through a set ofutilities described in section 3.3.3.1 PRIMARY COMMAND BLOCK STRUCTUREThe 3C505 firmware idles waiting for a Primary Command(PCB) from the PC Host. The PCB structure is expectedcommand/response sequences. The format of a PCB is:PCB command code (byte)PCB data length (byte)PCB data (variable length)BlockduringThe PCB is passed using programmed I/O through the CommandRegister. An example PCB might contain an 82586 configurationcommand, a length field that counts the number of bytes in thedata field, and a data field that has configuration data neededto set up the 82586 coprocessor.The maximum PCB size the Adapter can accept in this version ROMis 64 bytes. The PCB data length field does not include the PCBcommand code or the length field itself. The maximum data fieldis 62 bytes long. The valid PCB command codes are summarized inTable 1 and are explained in detail in section 3.2.28
  33. 33. TABLE 1: PCB COMMAND CODE SUMMARYHOST -> 3C505 COMMANDS00:01: configure adapter memory02: configure 8258603: Ethernet address04: download data to 3C50505: upload data to Host06: download data to 3C50507: upload data to Host08: receive packet09: transmit packetOa: network statisticsOb: load multicast listOc: clear downloaded programsOd: download programOe: execute programOf: self-test10: set Ethernet address11: adapter info12: reserved: I2f: reserved3CS05 -> HOSTconfigure adapter memoryconfigure 82586 responseaddress responsedownload data requestupload data requestn/an/a30:31:32:33:34:35:36:37:38:39:3a:31:> :3c:3d:3e:3f:40:41:42:receive packet completetransmit packet completenetwork statistics responseload multicast responseclear program responsedownload program responseexecute response..5f:self-test responseset address response .adapter info responsereservedIreserved29(set adapter buffer requirements)(set 82586 receive mode)(get adapter Ethernet address)(download using 3C505 DMA)(upload to Host using 3C505 DMA)(download using 3C505 PIO)(upload to Host using 3C505 PIO)(receive a packet)(transmit a packet)(includes 82586 error counts)(perform 82586 MC-setup command)(release download program memory)(download program to 3C505)(execute program in 3C505)(perform 3C505 self-test)(set Ethernet address in 82586)(get adapter information)(returns success or failure)(returns success or failure)(returns Ethernet address)(request DMA download to 3C505)(request DMA upload to Host)(receive packet request complete)(transmit packet request complete)(returns network statistics)(returns success or failure)(returns success or failure)(returns program id)(returns variable length data)(returns self-test results)(returns success or failure)(returns adapter information)
  34. 34. 3.1.1 STATUS FLAG USAGE FOR PCB TRANSFERThe Adapter uses a 64-byte circular buffer to store the hostbyte stream sent through the Command Register. Forprotection against stray bytes (from Host aborted PCBtransfers), the Adapter does not consider a PCB transfercomplete until the Host status Flags (HSF2 and HSFl) go tostate 11. Simultaneously, the TOTAL length of the PCBshould be in the Command Register so the true beginning ofPCB can be calculated. (This last total length is NOTincluded in the PCB data length field.) The Adapter usesits status flags (ASF2 and ASF1) similarly to signal "end ofPCB" when sending a PCB to the Host.The Adapter is always ready to read a PCB but it might notalways be able to accept it. To indicate the acceptance ofthe PCB, the Adapter uses status flag-state 01 after theHost signals end-of-PCB. To indicate rejection, the Adapteruses status flag state 10. When the Adapter sends a PCB tothe Host, it expects the Host to set its status flagssimilarly to signal acceptance or rejection.In summary, the Adapter uses and expects the Host to use thefollowing conventions:Adapter or Bost Status FlaqSF2oo11SFlo1o1UndefinedPCB acceptedPCB rejectedEnd of PCBThe state 11 is accompanied by the total length of the PCBjust transmitted. After a PCB is received, the state 01 or10 is used to signal acceptance or rejection of ·the PCB.3.1.2 BOST TO ADAPTER REQUESTThe following method is suggested to transmit a Host PCB tothe 3C505 Adapter:- Load the PCB command byte into the Command Register; thiswill interrupt the 3C505 Adapter, synchronizing it to the PCHost for the data transfer.- Poll the Command Register Empty (HCRE) flag inStatus Register. Abort the I/O if it does notwithin 40 ms.30the Hostgo empty
  35. 35. - output the remainder of the PCB similarly, reducing thetimeout period to SOOus. The Adapter remains in interruptcontext to read PCB data.- After the last actual PCB data byte is transferred, theHost must send one last byte signifying the TOTAL length ofthe PCB (excluding this byte). set the Host status flagsto state 11 before writing the length.- wait for adapter state 01 (accept) or 10 (reject). Assumea reject if a SOms timeout occurs.3.1.3 ADAPTER TO HOST REQUEST OR RESPONSEThe 3C505 Adapter to PC Host request is made when theAdapter needs to read or write a block of host memory. TheAdapter usually sends a response PCB after it has executed ahost request.The following method is used to transmit an adapter PCB tothe Host:- Load the PCB command byte into the Command Register; thisinterrupts the PC Host, synchronizing it to the Adapter forthe data transfer.- Poll the Command Register Empty (ACRE) flag in the Adapterstatus Register. Abort the I/O if it does not go emptywithin 20 ms.- Output the remainder of the PCB similarly,timeout to SOous. The Host should remaincontext to read PCB data.reducing thein interrupt- After the last actual PCB data byte is transferred, theAdapter sends one last byte signifying the TOTAL length ofthe PCB. The Adapter status Flags are set to state 11before writing the length.- The Adapter waits for Host status Flag state 01 (accept)or 10 (reject).31
  36. 36. 3.2 PCB COMMANDS3.2.1 HOS~ TO 3C505 PCB FORMATS01H: Confiqure A~apter Memory. The Adapter allocates memoryfor the PCB command queue, receive command queue,multicast address list, 82586 frame descriptors, receivebuffers, and download program data structures. Each PCBand receive command queue entry is large enough to bufferthe maximum size PCB of 64 bytes. A multicast list is keptin adapter memory to be loaded into the 82586 LANcoprocessor when in multicast mode. Receive and transmitbuffers of 1.6kb are alwp: is iJ.sei: tQ decrease buff,~rmanagement and DMA overhead. The number of transmi~buffers is fixed at one and is not confiqurable. If thiscommand is not issued, the Adapter uses the default valuesshown in parentheses below. The Host should expect theadapter response PCB31H to confirm execution.dbdbdwdwdwdwdwdw01OC??????;command code;length of data portion of PCB;# command queue entries (10);# receive queue entries (20);# multicast addresses (0);# frame descriptors (20);* receive buffers (20);# download programs (10)02H: Confiqure 82586. Instructs the Adapter to configure the82586 LAN coprocessor into the given receive mode. If thisconfigure command is not issued, the Adapter will use thedefault values shown in parentheses below. The Hostshould expect the adapter response PCB 32Hto confirmexecution.db 02 ;command codedb 02H ;length of data portion of PCBdw ? ;receive mode· bit 2,1,0: receive mode (000),000 = station only001 = plus broadcast· 010 = multicast,· 100 = promiscuous,· bit 4,3 loopback mode (00),· 00 = none (default),· 01 = 82586 internal loopback,· 10 = 82586 external loopback,32
  37. 37. 03B: Ethernet Address. Requests Adapter to return the Ethernetaddress stored in its address PROM. The Adapter sends thePROM address in PCB 33H.dbdb0300:command code;length of data portion of PCB04H: Download Data To 3CSOS. Requests the Adapter to DMAdownload data through the data register. The directionbit must be set to the download direction before issuingthe command. If the command is accepted, the Adapter setsup the DMA transfer and expects the Host to supply therequired number of bytes. There is no Adapter responsePCB for this command.db 04 ;command codedb 06 ;length of data portion of PCBdw ? ;data block byte length (must be even)dw ? ;Adapter destination offsetdw ? · " " segment,OSH: Upload Data To Host. Requests the Adapter to use itsDMA channel to upload data through the data register. Thedirection bit must be set to the upload direction beforeissuing this command. If the command is accepted, theAdapter sets up the DMA and expects the Host to read thegiven number of bytes. There is no adapter response PCBfor this command.db 05 icommand codedb 06 ;length of data portion of PCBdw ? idata block byte length (must be even)dw ? ;Adapter source offsetdw ? · " Itsegment,06H: Download Data To 3C50S. Operates as command code 04H,except that the Adapter uses programmed input/output (PIO)instead of DMA. The direction bit must be set to thedownload direction before issuing this command. There isno adapter response PCB for this command.db 06 icommand codedb 06 ilength of data portion of PCBdw ? ;data block byte length (must be even)dw ? ;Adapter destination offsetdw ? · " " segment,33
  38. 38. 07H:OSH:Upload Data To Host. Operates as command code 05H,except that the Adapter uses PIO instead of DMA. Thedirection bit must be set to the upload direction beforeissuing this command. There is no adapter response PCBfor this command.db 07 icommand codedb 06 i length of data portion of PCBdw ? idata block byte length (must be even)dw ? iAdapter source offsetdw ? ; II IIsegmentRecei~;;i(~ P~,cket. Pequests the Adapte,r, to rece:lre "Ethernet packet. The packet type of interest is d~finedpreviously by the Configure PCB 02H. _ When the receive iscomplete, the Adapter responds with PCB 3aH. The Hostshould set up to input the packet data and then accept theresponse. The Adapter will DMA upload the packet throughthe Data Register.dbdbdwdwdwdwOS08????icommand code;length of PCB data portion;offset of Host receive buffer;segment of Host receive bufferiHost receive buffer length in bytesitimeout in 10ms increments (zero isi no timeouti maximum is 32767 ticks)09H: Transmit Packet. Requests the Adapter to transmit apacket. If the PCB is accepted, the Host should DMAdownload the packet data through the Data Register. Whenthe transmit is complete, the Adapter responds with PCB39H.dbdbdwdwdw09H06???;command codeilength of PCB data portion;offset of Host transmit bufferisegment of Host transmit bufferipacket length in bytes (must be even)OAR: Network statistics. This command requests the Adapter tosend the cumulative 82586 error statistics and the packetcounters kept by the Adapter. The values are returnedthrough the command register in the Adapter response PCBwith command code 3AH. The Adapter clears all statisticsafter sending the response.dbdbOAH00icommand codeilength of PCB data portion34
  39. 39. OBB: Load Multicast List. The Adapter will add the given listof multicast addresses to the 82586 multicast list. Azero length list will cause the Adapter to clear allmulticast addresses and multiple PCBs can be issued tocreate lists greater than ten entries. The maximum numberof addresses in the PCB is ten. The response PCB 3BH willcontain command completion status.dbdbdbdbOBH6*n6 dupe?)6 dupe?);command code;length of PCB data portion;Multicast address 1;Multicast address n (10 maximum)OCH: . Clear Downloaded- ProqramEi. This command releases alladapter memory previously allocated to downloaded progams.The adapter response PCB 3CH will contain the number ofparagraphs of program memory available.dbdbOCHo;command code;length of PCB data portionODH: Download Proqram. Downloaded programs occupy adaptermemory not used for packet buffers or system overhead. Ifthis request is accepted, the Adapter will DMA downloadthe program. When done, the Adapter responds with PCB 3DHcontaining a "program id". The Adapter always providesparagraph alignment to each downloaded program. It issuggested that the Adapter be hard reset before a DownloadProgram sequence.dbdbdwODH02?icommand code;length of PCB data portion;program length in bytesOEB: Execute Proqram. The Adapter will pass control to theprogram defined by the program ide The first executablecode is assumed at offset zero relative to the beginningof the downloaded program. The calling sequence to thedownloaded program is described in section 3.3.5, function2. The Adapter, when done, responds with PCB 3EH.dbdbdwdbOEB02+n?n dupe?);command codeilength of PCB data portion;program id;variable length parameter list35
  40. 40. OFH: Sel~-Test. The Adapter will execute its self-test.Adapter, when done, responds with PCB 3FH.dbdbOFHo;command code;length of PCB data portionThe10H: set Ethernet Address. The Adapter will issue an lA-setupcommand to the 82586 coprocessor specifying an Ethernetstation address. If this command is not used, the addressfrom the Adapters Ethernet address PROM is used toconfigure the 82586.lOH66 dupe?);command code;length of PCB data portion;Ethernet address11H: Adapter Info. Requests the 3C505 Adapter to send generalinformation that describes the adapter configuration. TheAdapter, when done, responds with PCB 41H.dbdbllHo;command code;length of PCB data portion36
  41. 41. 3.2.2 3C505 TO HOST PCB FORMATS31H: Configure Adapter Response. After the Adapter has32H:33H:34H:3SH:initialized the PCB command queue and the multicastaddress storage area, it responds with status in this PCB.dbdbdw3lH02?; command;length of PCB data portion; status 0 = successfulConfigure 82586 Response. After the Adapter has initial-ized the 82586 coprocessor using parameters in the PCB 02Hcommand, it responds with status in this PCB.dbdbdw32H02?;command code;length of PCB data portionistatus 0 = successfulEthernet Address Response. The Adapter returns the 6-byteEthernet address in this response PCB. The address haspreviously been read from the Ethernet address PROM andstored into memory.dbdbdb33H066 dupe?)icommand code;length of PCB data portioniEthernet addressDownload Data To 3CS05. In this PCB, the Adapter requeststhat the Host download a block of host memory to the3C505. If the command is accepted by the Host, the Adapterwill use DMA to transfer the data through the dataregister.db 34H icommand codedb 06 ilength of data portion of PCBdw ? idata block byte length (must be even)dw ? iHost data block source offsetdw ? ;Host IIsegmentUpload Data To Host. In this PCB, the Adapter requeststhat the Host upload a block of data into Host memory. Ifthe command is accepted, the Adapter will set up a D¥~ totransfer the appropriate data through the data register.dbdbdwdwdw35H06???;command codeilength of data portion of PCBidata block byte length (must be even);Host data block destination offseti Host" segment37
  42. 42. 38H: Packet Received Response. When the Adapter receives apacket and there is an outstanding Host request to receivea packet, the Adapter sends this response PCB and followsit with a DMA upload. The number of bytes DMAed will notexceed the buffer length specified in the receive packetcommand PCB 8Hi extra packet data is discarded.39B:3~:dbdbdwdwdwdwdwdwdd38H10H???????Transmit Packettransmission isPCB.db 39Hdb 08Hdw ?dw ?dw ?dw ?icommand codeilength of PCB data portion;offset of Host receive bufferisegment of Host receive bufferinumber of bytes to be DMAediactual packet lengthicompletion status 0 = successfuli -1 = timeouti82586 receive statusidouble word time tag in 15us ticksComplete. The status of a packetreturned to the Host in this responseicommand codeilength of PCB data portionioffset of Host transmit bufferisegment of Host transmit buffer;completion status 0 = successful:82586 transmit statusNetwork statistics Response. The Adapter returns thetotal packet counters and the 82586 error counters inthis response PCB.dbdbdddddwdwdwdw3~OCH??????icommand code;length of PCB data portionitotal receive packetsitotal transmit packetsiCRC error counter;alignment error counterino resources error counter;overrun error counter3BH: Load Multicast Complete. After the multicast list isloaded into the 82586, the Adapter responds with this PCB.dbdbdw3BH02?;command codeilenqth of PCB data portion;status 0 = successful38
  43. 43. 3CH: Clear Downloaded Program Response. To clear the down-loadable program memory, the Adapter reinitializesthe structures and variables describing each downloadedprogram. The Adapter sends the amount of program memoryavailable in paragraphs in this response PCB.dbdbdw3CH02?icommand codeilength of PCB data portion;amount of downloadable program;memory in paragraphs3DB: Download Program Response. A downloaded program isassigned a "program id" by the Adapter. The id is used bythe Host and Adapter when specifying which downloadedprogram to execute or has executed.dbdbdwdwdwdw3DH08????icommand code;length of PCB data portion;program id: > 0 , if allocatediprogram offset in adapter memoryiprogram segment in adapter memoryiremaining memory in paragraphs3EH: Execute Program Response. After a downloaded program hasexecuted, it sends this response PCB to the Host. Thereturn status and parameters are program dependent.dbdbdwdb3EH02+n?n dupe?)iconunand code;lenqth of PCB data portion;program id: -1 if bad id in request;return status and parameters3FH: Self-Test Response. The adapter self-test consists of aROM checksum, non-destructive RAM test, and internalloopback test on the 82586. status of the test isreturned in this PCB.dbdbdwdw3FH2+2n?n dupe?);command code;length of PCB data portion;self-test status; and optional failure dataThe self-test status codes and failure data for each are:#o123STATUSno errorsROM checksumRAM test82586 testFAILURE DATAnonecomputed checksum valuefailed memory offset:seqmentstatus word:bit 14 = internal loopback failure13 = external loopback failure12 = configure error39
  44. 44. 40H: set Address Response.address in the 82586,After the Adapter sets the Ethernetthis response is sent to the Host.dbdbdw40H2?icommand codeilength of PCB data portionistatus O=successful41H: Adapter Info Response. The Adapter formats a responsecontaining the ROM revision code, ROM checksum value,total amount of memory in kilobytes, and the segment/offset pointer to free memory.dbdbdwdwdwdwdw41H10?????icommand codeilenqth of PCB data portioriiROM revision level (Ox0300 = rev 3.0)ichecksum value in romiamount of memory in kbyteifree memory offseti and seqment40
  45. 45. 3.3 SYSTEM ROM UTILITIESPrograms downloaded into the 3C505 Adapter can access the adapterresources directly or through a set of utilities available in ROMcode. To simplify and standardize usage, a set of soft interruptvectors have been allocated to support the following:* Host I/O* Network I/O* Configuration/status* System Timer* Download Program Support* PCB Command Processing* Receive Packet Processing* Timed execution* PCB EnqueuingThese vectors may be replaced or chained to by user downloadedprograms. To chain to a vector, the downloaded program shouldfirst save the current vector before replacing it with a pointerto itself. A program then gains control when the vector isinvoked. As appropriate, the program should pass control to thenext program in the chain.The 3C505 ROM utilities always save and restore the callingprograms SS, DS, ES and SP. It is suggested that downloadedprograms also maintain these registers.3.3.1 HOST I/O SUPPORT: INT aOHThis group of function allows upload and download of dataand command blocks between the Adapter and PC Host. BothDMA and PIO methods of IO are supported.01H: Download Request. The Adapter formats a downloadfor HostIf theshouldrequest PCB, sends it to the Host, and waitsacknowledgement (HSF2 and HSF1 state 01 or 10).Host accepts the request (state 01)1 the callerproceed with the data transfer.ax ~ 1es:bxcxdxfunction codeHost source buffer addressbuffer length bytes (must be even; maximum 64kb)initial timeout in 10ms increments(maximum is 32767 ticks)Return: carry clear if successfulcarry set if error, ax = error code41
  46. 46. 02H: DMA Upload Request. The Adapter formats a uploadrequest PCB and sends it to the Host. If the request isacknowledged by the Host (HSF2 and HSFl state 01), theAdapter should perform the data transfer.ax = 2es:bxcxdxfunction codeHost destination buffer addressbuffer length bytes (must be even: maximum 64kb)initial timeout in 10ms increments(maximum is 32767 ticks)Return: carry clear if successfulTry set if error, ax = errCJt code03B: Get Primary Command Block From Host. This functionreads a PCB through the Command Register and stores it intothe destination buffer.ax = 3 function codees:bx buffer addresscx buffer length bytesdx initial timeout in 10ms increments(maximum is 32767 ticks)Return: carry clear if successfulcarry set if error, ax = error code04H: Send primary Command Block To Host. This functionsends the given PCB buffer to the Host and waits for hostacknowledgement either accept or reject.ax = 4 function codees:bx buffer addresscx total buffer length bytesdx initial timeout in 10ms increments(maximum is 32767 ticks)Return: carry clear if successful and acceptedcarry set if error, ax = error codeOSB: 06H: Host Data Input. Assuming that the Host isalready configured to perform a download, this functiontransfers host data into the passed buffer using DMA or PIO.When DMA is used, the timeout value passed in register DX isthe amount of time the Adapter waits for the DMA semaphoreto signal "available". If a timeout occurs, the Adapterassumes some sort of error has occurred and takes over useof the DMA channel. Also, the function initiates DMAtransfer but does not wait for completion. Use int SOHfunction eBH to poll for DMA completion.42
  47. 47. ax - 5ax -= 6es:bxexdxDMA download orPIO downloadbuffer addressbuffer length in bytes to transfer (must be even)timeout in lOms increments(maximum is 32767 ticks)Return: carry clear if successfulcarry set if error, ax -= error code07H: OSH: Host Data output. Assuming that the Host isalready configured to perform an upload, this functiontransfers adapter data (using DMA or PIO) from the adapterbuffer to the Host. The comments descriping DMA in int SOHfunction OSH also apply here.ax -= 7ax -= Ses:bxexdxDMA upload orPIO uploadbuffer addressbuffer length in bytes to transfer (must be even)initial timeout in lOms increments(maximum is 32767 ticks)Return: carry clear if successfulcarry set if error, ax - error code09H: OAB: Accept or Reject PCB. When a PCB is read usingint SOH function 3, the protocol described in section 3.1.1requires that the PCB be accepted or rejected. Thefollowing function codes provide this ability to downloadedprograms:ax = 09H Accept Host PCBax = OAR Reject Host PCBFunction 9 to accept a PCB also includes a Data Registerflush operation to prepare for a DMA or PIO data transfer.OBH: Check DMA Complete. When a DMA transfer has beeninitiated, this function can be ~alled to check if the DMAhas completed.ax = OBH Check DMA Completedx timeout in lOms ticks (maximum is 32767 ticks)Return: carry clear if DMA donecarry set if timeout43
  48. 48. 3.3.2 NETWORK I/O SUPPORT: INT 81BlH: Transmit Packet. To transmit a packet, this functionlinks the given packet buffer to the first 82586 transmitbuffer descriptor, links the descriptor to the one and onlytransmit command block, links the command block to thesystem control block, and then signals channel attention tothe 82856. The transmit packet function will poll fortransmit complete before returning to the calling routine.ax ~ 1 function codees:bx buffer addresscx buffer length bytesdx timeout in 10ms incrementsReturn: carry clear if successfulcarry set if error, ax = 8258~ transmit status2H: Receive Packet. During execution of the Adapter and82586 configure commands (section 3.2), the 82586 ReceiveFrame Area is initialized and the Receive unit is commandedto start frame reception. A receive packet is firstdetected by the 82586 interrupt service routine, which timetags it and then updates global pointers to an "receivedpacket" list. This function checks that list for an entryand gives it to the caller.ax = 2dxfunction codetimeout in 10ms increments(maximum is 32767 ticks)Return: carry clear if successfules:bx = packet buffer addresscx:dx = double word time tag (high:low order)di = packet length in bytessi = 82586 receive statuscarry set if error, ax = error code03H: Return Buffer. After a packet buffer is processed,it must be· returned to the system so that the buffer can be·relinked to a Receive Buffer Descriptor which is in turnrelinked to the free RBD list.ax ~ 3 function codees:bx Buffer addressReturn: carry clear if successfulcarry set if error, ax = error code44
  49. 49. 3.3.3 CONFIGURATION/STATUS: INT 82H01H: confiqure A~apter .Memory. The Adapter allocatesmemory for the PCB command queue, receive command queue,multicast address list, frame descriptors, receive buffers,and download program structures. Each PCB or receivecommand queue entry is large enough to buffer a maximum sizePCB of 64 bytes. Each multicast address occupies 6 bytes.Receive and transmit buffers are fixed at 1.6kb in order todecrease management overhead. The number of transmitbuffers is fixed at one.ax ~ 1 function codees:bx pointer to configuration control blocknum PCB entries ow ? (10)num-receive Q entries OW ? 20)num-multicast-entries DW ? (0)num-frame descriptors OW ? (20)num-receive buffers OW ? (20)num download~rograms OW ? (10)Return: carry clear if successfulcarry set if error, ax = error code02H; Confiqure 82586 Receive Mo~e. Instructs the Adapterto set the 82586 coprocessor into the given receive mode.ax = 2 function codebx receive modebit 2,1,0: receive mode (000)000 = station only001 = plus broadcast010 = multicast100 = promiscuousbit 4,3 loopback mode (00)00 = none (default)01 = internal loopback10 = external loopbackReturn: carry clear if successfulcarry set if error, ax = error code03H: Return Ethernet Address. Read the Ethernet addressPROM and store the 6-byte address into the callers buffer.ax = 3 function codees:bx buffer addressReturn: carry clear if successful, buffer es:bx updatedcarry set if error, ax = error code45
  50. 50. 04H: set Ethernet Address. Use the supplied Ethernetaddress and issue an lA-setup command to the 82586coprocessor.ax = 4 function codees:bx buffer addressReturn: carry clear if successfulcarry set if error, ax = errorOSH: set LEDs. This function allows downloaded programs tocontrol the state of the Adapters two LEOs. LED #2 is~eriodically flashed by the Adapter to indicate normal"peration; this is called the "heartbeat" ..ax = 5 function codebx control wordbit 1,0 - LED2,LEDl value; l=ONbit 2 - enable/disable heartbeat; l=enableReturn: ax = current control register value in high bytecarry clear if successfulcarry set if error06H: Getinformation.Adapter Info. Retrieve generalax = 6 function codees:bx buffer addressReturn: es:bx = reV1S1on idrom checksumcxcarrycarrymemory size in kbytesfree memory offsetfre·e memory segment= data length in bytesclear if successfulset if error46adapter
  51. 51. 3.3.4 TIMER SUPPORT: INT 83BThe 3C505 Adapter maintains both a lOms and lSus double wordtime tick counter using two 16-bit timers in the 80186microprocessor. The lSus timer is meant for high resolutiontimeout or time tag applications and generates a timerinterrupt every 1.6 seconds. The 10ms timer generates aninterrupt every 10ms and can be used for timeoutcalculations. Every five 10ms ticks the Adapter also callsthe Idle vector (section 3.3.8). This allows downloadedprograms that are "chained" through the Idle vector a chanceto execute periodically.. .o12~ s~t lOms Double Word Time. set the global double wordlOms tick counter to given value.ax -= 1exdxfunction codehigh portion of 10ms countlow portion of count02H: Read lOms Double Word Time.double word lOms tick counter.ax -= 2 function codeRetrieve the currentReturn: cxdxhigh portion of 10ms countlow portion of count03H: Set 1Sus Double Word Time. Set the global doubleword lSus tick counter to given value.ax = 3exdxfunction codehigh portion of lSus countlow portion of count04H: Read lSus Double Word Time.aouble word lSus tick counter.ax = 4 function codeRetrieve the currentReturn: cxdxhigh portion of lSus countlow portion of count47
  52. 52. 3.3.5 DOWNLOAD PROGRAM SUPPORT: XNT 84HThe Adapter uses low memory for data, stack, packet buffers,and PCB command queue. Remaining memory is available fordownloaded programs. Programs must have staticallyallocated memory for global data. Programs can use the onekiloword stack segment setup by the 3C505 ROM. Downloadedprograms should not reconfigure adapter memory.OlH: Clear Downloaded Programs. This command releases alladapter memory previously allocated to downloaded programs.Soft interrupt vectors are restored to the reset state.ax = 1 function codeReturn: carry clear if successful, ax =# free paragraphscarry set if error, ax = error code02H: Execute Program. Control is passed to the programdefined by the program ide Executing a program is a farsubroutine call to the program with the following registerssetup:ax = 2 function codees:bx address of parameter listex length of parameter list in bytesdx program idReturn: carry clear if successfules:bx - address of return buffercx - length of return buffercarry set if error, ax = error code48
  53. 53. 3.3.6 PCB COMMAND PROCESSOR: INT aSHThe adapter Command Register ISR (interrupt service routine)reads host PCBs and places all PCBs except rece~vecommands (see section 3.3.7) into a command queue. The3CSOS ROM idle loop monitors and dequeues each PCB forexecution. The PCB is passed to a PCB Command Processorwhose address is stored in this interrupt vector. TheCommand Processor is given an ES:BX pointer to the PCBentry.It uses the PCB command number to key into a jump table ofcommand processing subroutine addresses. The selectedcommand processing subroutine is also passed the PCB (oftencontaining parameters for the slibroutine). The CommandProcessor ignores PCBs with command numbers not defined inthis specification, and immediately returns to theforeground idle.A downloaded program can chain to this vector; that is, theprogram saves the current interrupt vector contents andreplaces it with a pointer to itself. Then the downloadedprogram has an opportunity (not necessarily the first) toexamine the PCB. If the program does not want to executethe PCB, the program must pass it to the command processorthat it replaced. In this case the program must be carefulthat register values are not modified. This becomes amechanism for creating new commands or replacing existingones.49
  54. 54. 3.3. PACKET PROCESSOR VECTOR: INT 86HThis software interrupt vector defines the address of thePacket Processor. The Packet Processor centralizes handlingand queuing of host receive command PCBs and receivedpackets. The management of the,82S86 LAN coprocesser isperformed outside the Packet Processor. A downloadedprogram can replace this vector in order to implement a morespecialized scheme than the ROM-based functions describedbelow.As mentioned in section 3.3.6, all PCBs EXCEPT the receivepacket command are placed into a PCB queue. The CommandRegi,~;ter ISR gives the receive command to the PacketProcessor with:01H: Enqueue Receive Command PCBax -= 1es:bxcommand codepointer to PCBA separately managed Receive Command Queue is built.When packets are received, the 82S86 ISR time tags the framewith a double word lSus time and updates global pointers tothe frame and exits. The foreground idle loop obtains apacket from the the Network I/O vector INT SlH function 2.The idle loop gives the packet to the Packet Processor with:02H: Enqueue Receive Packetax = 2es:bxcx:dxdicommand codepointer to receive bufferdouble word time tag (high: low)packet lengthThe firmware builds a queue of receive packets. If there isa pending receive command, a receive response PCB is sent tothe Host, packet data is DMA uploaded, and the packet bufferis returned to the system. Otherwise, the packet isenqueued and processing is done. This vector/function canbe replaced by downloaded programs enabling them to receiveand process all incoming packet.sinceidlewith:receive commands have timeout values, the foregroundloop needs to periodically call the Packet Processorso
  55. 55. 03H: No Operationax - 3 NOPso that it has an opportunity to scan the receive commandqueue to check if any request has timed out. If a requesthas timed out, a receive response PCB with failure status isformatted and sent to the Host.3.3.8 IDLE VECTOR: INT 87KThe Idle vector is called every sOms from the main 3CsOs ROMidle loop. Programs chained through this vector will have achance to execute.To chain to the vector, a downloaded program should firstsave the.current vector before replacing it with a pointerto itself. It is also important that the program passcontrol (using a far jump) to the next program in the chain.Remember thau SS, SP, DS and ES should always be saved onentry and restored on exit. In this way, each downloadedprogram in the chain has an oppurtunity to execute.The default ROM Idle vector routine clears a global flagthat determines whether the Idle vector should be called.In a situation where a download program has chained to theIdle vector but never passes control to the default Idlevector routine, this flag is never cleared. The effect isthat the download program will be called en every passthrough the main 3C505 ROM idle loop.3.3.9 PCB ENQUEUE VECTOR: XNT 88HThe PCB Enqueue Vector is called to add a PCB entry into thesystem PCB queue. PCBs are dequeued by the foreground idleloop and given to the PCB Command Processor for execution.The calling sequence for this function is:es:bx pointer to PCBReturn: carry ciear if successfulcarry set if error, ax - error codeThe Command Register interrupt service routine (ISR) usesthis vector after it receives a PCB. If a downloadedprogram has read a PCB from the Host and does not recognizeit, it should use this vector to enqueue it for laterex,ecutien. Alternatively, a downloaded program can chain tothis vector to receive PCBs from the Command Register ISR.51
  56. 56. APPENDIX A80186 PERIPHERAL CONTROL BLOCK PROGRAMMING·,reloc reg contumcs cont-lmcs-contmmcs-contmpcs-contpacs-conti·,equequequequequequi pic priority assignment:·,level intolevel-int1level-int2level-int3level-dmaOlevel-dma1level-timer·,equequequequequequequOOffhOfc3ch3ffch81fchOaObch003ch4256o31iinitialization constant ofichip selectsiinto priority, Command Register Fulliint1 priority, interrupt form 82586inot usedinot usedidmaO priority, DRAM refreshidma1 priority, Data Registeritimer priority: initialization of pic control registers·,pic timer contpic-dmao contpic-dmal-contpic-into-contpic-int1-contpic-int2-contpic:int3:cont·,equequequequequequequlevel timerlevel-dmaOlevel-dma1level-intolevel-intlOOOdh-OOOehi initialization of timer 2 registers; 15 microsecond for DRAM refreshi and Hi RES Timer·,t2cnt contt2maxra contt2cntrl-cont·,equequequo30OcOOlhi initialization of timer 0 registersi 10 millisecond interrupt·,tOcnt conttOmaxra conttOmaxrb-conttOcntrl-cont·,;equequequequo20000jt2maxra_contoOe029h52
  57. 57. ;: initialization of timer 1 registers; Hi res system Timertlcnt cent equ 0tlmaxra cont equ OffffhtOmaxrb-cont equ 0tOcntrl cont equ Oe029h-;· initialization of dmaO registers; DRAM refreshI·IdmaOsrclo cont equ 0000dmaOsrchi-cont equ OOOOhdmaOdstlo-cont equ 0800hdmaOdsthi-cont equ 0OO8hdmaOcnt cont equ OffffhdmaOcntrl cont equ 0157fh;; DMA 1. control register values·Idmal from dr cntrl equdmal=to_dr cntrl equOa347h iDMA input from host1787h iDMA output to host53
  58. 58. APPENDIX BThis is an example of the parameters used to configure the Intel82586 LAN Coprocessor. Please refer to the "Intel LAN ComponentsUsers Manual" for the description of the abbreviations used.FIFO LIM = 6BYTE CNT = OCHEXT LP BCK = 0INT LP BCK = 0PREAM LEN = 2AT LOC = 1ADDR LEN = 6SAV BF = 0SRDY = 1INTERFRAME SPACING = 60HBOF MET = 0ACR = 0LIN PRIO = 0RETRY NOM = OFHSLOT TIME = 200HCDT SRC = 0CDTF = 0CRS SRC = 0CRSF = 0PAD = 0BT STF = 0CRC16 = 0NCRC INS = 0TONO CRS = 0MANCH/NRZ = 0BC DIS = 1 (reconfigurable by host command)PRM = 0MIN FRM LEN = 40H54
  59. 59. The 3C505 EtherLinkEtherLink Plus card3C505.EXE, which canproblems on the 3C505.APPENDIX C3CSOS DIAGNOSTICDiagnostic Diskette supplied with yourincludes a diagnostic program calledbe used to help you identify hardwareThis appendix describes the 3C505.EXE program, the equipment andtools required to run the program, and a step-by-step procedureon how to use the diagnostic.3C505.EXE takes about twelve minutes or less (five minutes in anAT) from start to finish. As it runs, it reports its progress bydisplaying the name of the group of tests being performed and apass count. The test stops and displays an error message if ahardware error is detected.o123Adapter self testPreliminary testDMA testPacket test4567Recognizer testMessage exchange testPassive receive testNS echo serverWhen the standard 3C505.EXE program is run, Test 0 through Test 4are performed in sequence. Test 5 through Test 7 arerun individually and must be specified separately. Tests 3 and 4require the use of a loopback plug to prevent network activityfrom producing erroneous test results, and to keep test packetsfrom polluting the network. Tests 5 through 7 must be run whilethe Adapter is connected to the network. A brief description ofeach test follows:TEST 0Test 0 resets the Adapter causing the self-test routines to beexecuted. These include 80186 and 82586 initialization, memoryand internal and external loopback tests. The results are passedback to the Host and displayed. If communication between theHost and Adapter can not be established, an error message isdisplayed.TEST 1Test 1 tests the interface between the Host and the Adapter usingProgrammed I/O data transfers.55
  60. 60. TEST 2Test 2 tests the interface between the Host and the Adapter usingDMA data transfers.TEST 3Test 3 performs a transmit test and, if successful, a loopbacktest. The transmit test checks for the correct status from the82586 LAN controller following transmits. Loopback test furthercompares the received packets with those transmitted.TEST ..Test 4 tests the 82586 LAN controller address matching functions.The receiver is configured to various modes; station only,multicast, broadcast, and promiscuous. In each mode, packets ofdiffering destination address and size are transmitted and theability of the Adapter to reject or accept packets properly istested.TEST 5Test 5 performs packet exchange with another PC or server on thenetwork. The PC transmits an "echo request packet" into thenetwork. A responding server or PC will transmit the packet(echo) back to the PC under the test.TEST ,Test 6 detects legal packets on the network and counts them.This tests the adapters receive function and provides adiagnostic tool for locating problems elsewhere on the network.This test is "passive" to the network and can be used to checkthe transmit capability of another PC on the network.TEST 7Designates this PC as an "echo server", which is used to exchangepackets with PCs running Test 5. The PC remains in this modeuntil a key is depressed.56
  61. 61. FORMAT3C505 [-Ix][-Dx][-Bxxx](-#][-E][-T]PROGRAM PARAMETERSIx Test uses interrupt x, default (factory setting) isInterrupt 3.Dx Test uses DMA channel x, default is DMA 1.Bxxx Sets the base address of the EtherLink card to xxx (threehexadecimal digits). This option should be used if the I/Oaddress jumpers on the EtherLink card have been changed.The default value is 300 hex.Enter 5, 6 or 7 to select one of the following test.S - Message exchange test6 - Passive receive test7 - NS echo serverE Used with test S only. Use NS echo protocol to accessremote nodes during the message exchange test. This optionshould be used on a Xerox NS 8000 network that have echoservers or if there is another PC with a 3Com EtherLink3C50S running 3C505 -7 to reply to the echo request. Ifthis option is not specified, the diagnostic will generateEtherSeries echo requests, and any EtherSeries server on thenetwork will reply using EtherSeries protocol.T Specifies that the Host computer is a TI Professional whichrequires special treatment.Requirements for TestingFor testing, you need:1. A loopback plug;2. Another IBM PC on the network OR an EtherSeries networkserver that is connected to the network.The second PC will be used as an echo server, which will exchangepackets over the network with the computer under test.57
  62. 62. RUNNING THE 3CSOS.EXE PROGRAMTo start the 3C505.EXE program, disconnect your PC from thenetwork, attach a loopback plug to the ENC connector, insert thediskette in drive A: and type:A> 3CSOSRemember to give the option -I, -D, -B if the factory settingswere changed. As the program runs, it prints a messageindicating which test is being performed and the progress. Onceit detects an error, the test stops and displays a message. Testo thru 4 mentioned above will start one after another.To :run Tes-~ 5, connect the PC to the .l:Ai:.d;;work with either:1. An EtherSeries network serverOR2. Another PC, with an EtherLink 3C505 as a echo server. startthe server running 3C505.EXE on this diskette by typing:A> 3CSOS -7OR3. Another PC with another type of 3Com EtherLink acting as anecho server. Use the diagnostic program supplied with thatspecific EtherLink such as the 3C501 and type:A> 3C501 7If the echo server is case 2 mentioned above, then type:A> 3C50S -5 -EIf the echo server is case 3 mentioned above, then type:A> 3C505 -558
  63. 63. 3C501 / 3C505 DIAGNOSE PROGRAM DIFFERENCESThe 3C505.EXE diagnostic is modeled after the 3C501 version,3C501.EXE (or DIAGNOSE.COM in earlier versions). For those of youfamiliar with the 3C501 diagnostic, all test types (Preliminary,DMA, Packet, Recognizer, Message exchange, Passive receive, NSEcho server) have been carried forward into the 3C505 diagnostic.The actual interpretation and implementation of these tests forthe 3C505 are, however, very different. It is worth noting thatin the 3C505 diagnostic,o there is an additional test 0 (Adapter self test) ;o command line switches (to set adapter base address, DMAchannel, etc. for the test) are always preceded by a dash It-"io tests _0 through 4- (Adapter Self test, Preliminary " DMA,Packet, Recognizer) are always executed one after another(i.e., you cannot use tt3C505 -3 tt to run Packet test only);o tests 0 through 4 are skipped when test 5, 6, or 7 (Messageexchange, Passive receive, NS Echo server) is selected.After running 3C505.EXE, you might find it necessary reboot yoursystem or reinitializethe 3C505. This is especially true if youuse download software or if a particular 3C505 configuration isexpected.59
  64. 64. APPENDIX D3D DEBUGGER3D is a program for loading and debugging programs that run onthe 3C505 adapter. 3D runs on an IBM PC (or compatible), underPC-DOS; the 3D Host program communicates through the CommandRegister with the "slave", a small program in the 3C505 ROM. 3Dcan start, stop, and single-step the 3C505s 80186 processor;set, and clear breakpoints; download, modify, and examine memory.3D requires an IBM PC with 2S6K of memory, one serial port, and aMouse Systems PC mouse. 3D also runs on IBM compatibles such asthe Compaq portable and Zenith Z-lS0. Attach the mouse to theCOM2 port. Recall that COM2 always uses interrupt level 3 sobeware of conflicts. The base I/O address~of the 3CS05 in thisversion of 3D must be set to 310 hex. The TEST jumper on the3C50S can also be set to the "1" position; this causes the 3DSlave to install itself at boot time. All "exception" and unusedinterrupt vectors will point to the 3D Slave. The ability tosingle step and to use breakpoints will be enabled.3D divides the display into four regions! from top to bottomthese are tile area, menu bar, typein, and message area. Thetile area is for display and alteration of 3C50S internalregisters, I/O registers, and memory. The menu bar is forcontrol of the 3CSOS. The typein area displays the accumulatedtypein from the user. The message area is for the display ofstatus and error messages from 3D.*AX 0000 BP 300C es 03FO *IP*BX 6892 *SP 3000 SS 3CSD *FLAGSex 0000 SI 04C4 OS 03FODX 0000 *OI 6806 *£5 03FO*40:8 0040 *3C6D:3000 SA7640:0A 0000 *3C6D:3002 03FO40:0C 0300 *3C6D:3004 F04640:0E 21:2E *3CSD:3006 F20640:10 0000 *3C6D:3008 6Aes40:12 0000 *3C6D:300A 6Ft>740:14 0000 *3C6D:30OC 3C6D40:16 0000 *3C60:300E 3C6D*3C60:3010 3C6D40:18 0014 *3C6D:3012 000040:1A 0000 *3C6D:3014 04C440:1C 0000 *3C6D:3016 303A40:1! 21:21: *3C6D:3018 302240:20 21:0E *3C60:30lA 064040:22 2FOA *3C6D:301C 000040:24 2FSA *3CSO:301E 0000Boot! Load! Go! Continue! Stop! Step! Break! Onbreak! OnbrealtAll! Probe!•• :.ppopf » Non masltable interrupt at 3FO:6A76Figure 1. The display just after a stop.606A7SF04S
  65. 65. TILE AREAThe tile area is divided into a 21 by 4 array of tiles. Eachtile displays the name of a register or memory location and itscontents. A tile consists of three fields; in reading orderthese are flag, left, and right. The left field holds theregister name and the right field displays it contents. A tilde,"-", in the flag means the data in the right field is invalid forsome reason. An asterisk, "*", means the right field changedsince 3D last read the register. When the cursor enters the tilearea, 3D inverts the tile occupied by the cursor.MENU BARThe menu bar provides access to functions for controlling the3C505. To select a function, move the cursor over the name ofthe function and click the left mouse button. Functions on themenu bar are Boot, Load, Go, continue, stop, step, Break,Unbreak, UnbreakAll, and Probe.Boot issues a hard reset to the 3C505 Adapter.Load downloads a file from the IBM PC to the 3C505 through theCommand Register. 3D always uses the last file specified unlessthe typein ends with a slash, "/". In this case, 3D uses thetypein, minus the slash, as the file name; thus, if the same fileis loaded many times, the file name need not be supplied everytime. The slash is not necessary for the first file loaded. Thefile is downloaded into Adapter memory at the address that isspecified in the typein area when function key F6 is pressed.Please note that this Load operation is NOT THE SAME as thedownload program PCB described in the Chapter 3.Go evaluates the typein and starts the 3C505 running at thespecified address.continue starts the 3C505 running at the current CS:IP. Once Goor continue starts the 3C505 running, 3D becomes a "dumb"terminal for the 3C505; 3D monitors both the IBM PC keyboard andthe Command Register. 3D transmits any character typed on thekeyboard through the Comnland Register. The bottom sixteen linesof the tile area become the display area for any characterstransmitted by the 3C505 through the Command Register.stop establishes communication between 3D and the Slave throughthe Command Register. If the Slave does not respond, 3D displaysan error in the message area. No other commands will work until3D and the Slave are communicating. stop is always appropriateno matter what state the 3C505 is in; however, booting willdestroy the state of the 3C505.61

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