Who am I ?

I make chips… For over 18 years

I help others make chips…

I live here… Austin, Texas

I went to school here… Texas A&M University BS Electrical Engineering MS Electrical Engineering

I work here… Professional Services Senior Design Consultant

I’ve consulted for…

I’ve consulted here… UK Korea USA China France Israel Germany Lived in Germany 5 years

My record… * Based on customer satisfaction reviews since Dec. 2004

My expertise… Power-Aware Flows Multi-Vth, Multi-VDD, MTCMOS Optimization and Analysis Full RTL to GDSII Flows Physical Design Custom and Semi-Custom Design

I’m an expert with… Power-Aware Design Power Compiler PrimeTime-PX PrimeRail UPF Front-end DC, DC-T PrimeTime Verilog Formality Physical Design IC Compiler PrimeTime-SI PC, Astro Astro-Rail JupiterXT Scripting TCL Perl Make Scheme

People aren’t bored when I do this… Competent Communicator

Or when they read these… Hold Me Please! How to Fix Post-Route Hold Violations Quickly and Easily Using Distributed Multi-Scenario Analysis SNUG Boston, Sept. 2007 Techniques for Power Optimization Compiler Magazine, Dec. 2004. Most read article every issue, two years running Branch History Table with Grey Coded Entry Bitcell Technical Developments, Jan. 1999 Advanced Low Power, Multi-Supply Implementation Techniques for 65nm and Beyond using DCT and ICC SNUG Boston, Sept. 2007 Power Management in Complex SoC Design Synopsys White Paper, Apr. 2004 Most downloaded White Paper in 2-year program Power Hungry? Strategies to Trim Your Chip's Appetite, Part 1: Overview, Analysis, Architectural Solutions Synopsys White Paper, July 2007 Timing Closure for 0.13um Design Using Various Clock Routing Techniques SNUG Europe, May 2005 Synopsys Distinguished Author

Want to see more? http://www.linkedin.com/in/brandonwaldo