Vishakantaiah validating

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  • Prefer “validation-aware design” to DFV – emphasis needs to be on designers understanding what is needed to make validation effective & efficient
  • Vishakantaiah validating

    1. 1. Validating next generation CPUs Praveen Vishakantaiah President, Intel India Feb 22, 2008 DV Club Bangalore
    2. 2. <ul><li>“ Validation is increasingly in the critical path of product success and requires continuous innovation to meet customer satisfaction, schedule and margin requirements” </li></ul>
    3. 3. Agenda <ul><ul><li>Current Challenges </li></ul></ul><ul><ul><li>Addressing the challenges </li></ul></ul>
    4. 4. CPU bug trends <ul><li>Exponential growth of design complexity </li></ul><ul><ul><li>Deeply pipelined complex micro-architecture </li></ul></ul><ul><ul><li>Logic bugs increase 3 - 4x per generation </li></ul></ul>Up to 70% of design time and resources are spent during functional validation Pre-silicon logic bugs per generation ( Source : Tom Schubert, Intel, DAC 2003 ) 7855 2240 800 25000 Pentium Pentium Pro Pentium 4 Next ?
    5. 5. The Pre-Si Verification gap EE Times 03/18/2004 Verification Capabilities is fast becoming the limiting factor for VLSI design improvements EE Times 2004
    6. 6. Current Challenges – Technical <ul><li>Increasing CPU design complexity </li></ul><ul><ul><ul><li>Multi core </li></ul></ul></ul><ul><ul><ul><li>Chipset integration </li></ul></ul></ul><ul><ul><ul><li>Power Management </li></ul></ul></ul><ul><ul><ul><li>New technology like security </li></ul></ul></ul><ul><ul><li>Increasingly bulky validation environment </li></ul></ul><ul><ul><ul><li>Increase in development and maintenance cost </li></ul></ul></ul><ul><ul><ul><li>Environment bugs >= Logic design bugs </li></ul></ul></ul><ul><ul><li>Increasing number of product variants </li></ul></ul><ul><ul><ul><li>Validation is not as incremental as design </li></ul></ul></ul><ul><ul><li>Increasing micro-architectural coverage space increases probability of escapes </li></ul></ul><ul><ul><li>Decreasing simulation/emulation speed limits pre-silicon cycles </li></ul></ul><ul><ul><li>Legacy features and compatibility validation </li></ul></ul>High volumes magnify the cost of a validation escape – can not let it happen!
    7. 7. Current Challenges – Non-Technical <ul><ul><li>Shorter TTM (Time to Market) </li></ul></ul><ul><ul><li>Physical limits and cost of data centers </li></ul></ul><ul><ul><li>CPU validation expertise </li></ul></ul><ul><ul><ul><li>More pronounced in India due to frequent job changes </li></ul></ul></ul><ul><ul><li>Cross site development </li></ul></ul><ul><ul><ul><li>Design and validation may not be co-located </li></ul></ul></ul>
    8. 8. Post-silicon validation <ul><li>SOC and Multi core leverage incremental design effort </li></ul><ul><ul><ul><li>Design interactions are spatial in nature </li></ul></ul></ul><ul><ul><ul><li>Effective design reuse is possible </li></ul></ul></ul><ul><li>Post Si Validation efforts currently not scaling incrementally </li></ul><ul><ul><li>- Logic interactions across widely separated areas introduces unexpected bugs </li></ul></ul><ul><ul><li>- No effective coverage feedback mechanism </li></ul></ul><ul><ul><li>- When is Validation enough ? </li></ul></ul><ul><ul><ul><ul><li>- Synthesis of approx coverage measure </li></ul></ul></ul></ul><ul><ul><ul><ul><li>- Effective Mathematical Models </li></ul></ul></ul></ul>
    9. 9. Addressing the challenges <ul><ul><li>Use experienced architects, micro-architects and front end designers </li></ul></ul><ul><ul><ul><li>Very likely to have lot more validation “burn” marks and will proactively code less bugs </li></ul></ul></ul><ul><ul><ul><li>Will be able to help validators debug issues faster </li></ul></ul></ul><ul><ul><ul><li>Raise the watermark for bugs and reduce iterations </li></ul></ul></ul><ul><ul><li>Validators drive requirements into architecture and micro-architecture </li></ul></ul><ul><ul><ul><li>Influence technology decisions to keep validation tractable </li></ul></ul></ul><ul><ul><ul><li>Minimize feature creep during execution </li></ul></ul></ul><ul><ul><ul><li>Reduce back end design impact on front end design </li></ul></ul></ul><ul><ul><li>Instrument design models to enable validation </li></ul></ul><ul><ul><ul><li>Assertions, instrumentation signals, comments </li></ul></ul></ul><ul><ul><ul><li>Aim for sweet spot with Effectiveness vs. Efficiency trade offs </li></ul></ul></ul><ul><ul><li>Validation Environment </li></ul></ul><ul><ul><ul><li>Minimize custom tool development </li></ul></ul></ul><ul><ul><li>Reuse design, validation and debug tools across programs </li></ul></ul><ul><ul><li>Scale emulation, formal verification and mixed signal validation </li></ul></ul>
    10. 10. Validation coverage profile and Efficacy Probability of bugs Time Si Spin1 Si Spin2 <ul><ul><ul><li>Efficiency: Catch bugs fast </li></ul></ul></ul><ul><ul><ul><li>Effectiveness: Catch all customer visible bugs </li></ul></ul></ul>Early detection and bug acceleration has significant business benefits
    11. 11. Q&A

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