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Verification of the QorIQ™ Communication
Platform Containing CoreNet™ Fabric with
SystemVerilog
Sakar Jain & Robert Page
F...
Agenda

                          Introduction

                          Verification Challenges

                    ...
Introduction

                 QorIQ™ (pronounced 'core eye-queue' ) Overview

                          Communication P...
QorIQ P4080 Communication Processor




Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. ...
CoreNet™ Platform Overview

                 CoreNet fabric sub-system is referred to as CoreNet Platform

             ...
CoreNet Platform Block Diagram

                         Core Complex                         Core Complex                ...
Agenda

                          QorIQ & CoreNet Platform Overview

                          Verification Challenges

...
Verification Challenges

                                      Multiple and new architectures to verify – CoreNet, Arbitr...
Agenda

                          QorIQ & CoreNet Platform Overview

                          Verification Challenges

...
Verification Methodology


                 Top-down – black box to white box

                 Transaction Based Verifi...
Agenda

                          QorIQ & CoreNet Platform Overview

                          Verification Challenges

...
SystemVerilog Testbench

                          SystemVerilog Base Class Library (SVBCL)
                             ...
CoreNet VIP Overview

                          Object oriented model of all platform CoreNet-compliant units – Fabric, P...
How SV helped

                          OOP concepts – Abstraction, Inheritance & Polymorphism

                       ...
SV Gotchas

                          Constraint-solving

                          Unsupported constructs (e.g. paramet...
Corenet Fabric Testbench
                                                 PA testcase                                     ...
IO Bridge Testbench
                                                 PA testcase                                      SV S...
CoreNet Platform Testbench
                                                                 PA testcase                   ...
Agenda

                          QorIQ & CoreNet Platform Overview

                          Verification Challenges

...
Successes

                 Successfully verified the entire CoreNet platform as an early adopter of System
             ...
Successes

                 First Networking & Multimedia Group (NMG) SoC with fully integrated SV
                  test...
Agenda

                          QorIQ & CoreNet Platform Overview

                          Verification Challenges

...
Q&A




Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service nam...
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Sakar jain

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  1. 1. Verification of the QorIQ™ Communication Platform Containing CoreNet™ Fabric with SystemVerilog Sakar Jain & Robert Page Freescale Semiconductor Austin Texas TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2009
  2. 2. Agenda  Introduction  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q&A Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 2
  3. 3. Introduction  QorIQ™ (pronounced 'core eye-queue' ) Overview  Communication Processors for networking applications  Multi-core with tri-level cache hierarchy  Intended for combined control, data-path and application layer processing  Freescale processors based on Power Architecture ®(PA) technology  New CoreNet™ Interconnect on-chip fabric Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 3
  4. 4. QorIQ P4080 Communication Processor Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 4
  5. 5. CoreNet™ Platform Overview  CoreNet fabric sub-system is referred to as CoreNet Platform  CoreNet is an on-chip, high efficiency, high performance multiprocessor coherent interconnect  Point-to-point interconnect  Independent address and data paths  Pipelined address bus, split transactions, out-of-order completion . Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 5
  6. 6. CoreNet Platform Block Diagram Core Complex Core Complex Core Complex 128KB Backside L2 Cache 128KB Backside L2 Cache 128KB Backside L2 Cache Power Architecture™ Power Architecture™ Power Architecture™ e500 Core e500 Core e500 Core 32KB 32KB 32KB 32KB 32KB 32KB D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache DUV 1MB DDR2/3 Front side Memory L3 Cache Controller CoreNet™ Coherency Fabric 1MB DDR2/3 Front side Memory L3 Cache Controller CoreNet L3 Cache IO Bridge IO Bridge IO Bridge Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 6
  7. 7. Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q&A Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 7
  8. 8. Verification Challenges  Multiple and new architectures to verify – CoreNet, Arbitration, Address Map, Security, Virtualization etc.  Extensive VIP development to support unit verification  New constrained random stimulus and associated coverage  Performance  Parameterized design to support multiple derivatives  Deal with legacy VIP  Adoption of new languages and tools (SV, SVA) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 8
  9. 9. Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q&A Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 9
  10. 10. Verification Methodology  Top-down – black box to white box  Transaction Based Verification Methodology (TBVM)  Coverage driven  Extensive correctness checking  Hierarchical Verification  Reuse, reuse, reuse! Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 10
  11. 11. Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q&A Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 11
  12. 12. SystemVerilog Testbench  SystemVerilog Base Class Library (SVBCL)  Basic building blocks for constructing testbenches  Same concept as OVM or VMM libraries  SVBCL Extensions  Register randomization, randomization routines  Algorithmic and random stimulus base classes  Enhanced run-time parameter management  Address manager to manage address regions between masters  Data manager for intermediate and final results checking  Cache/Memory preloaders and checkers  Platform Verification IP  Extensive set of BFMs for CoreNet and all other IP protocols  Monitors, Assertions, Coverage  Random and directed stimulus Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 12
  13. 13. CoreNet VIP Overview  Object oriented model of all platform CoreNet-compliant units – Fabric, Proc Master, IO Bridges, Targets.  Includes BFMs, monitors, coverage and stimulus objects  Layered Architecture of BFMs  Stimulus Layer - higher level stimulus objects  Transaction Layer – implements transaction attributes of CoreNet  Link Layer – implements flow control aspects of CoreNet  Phy Layer – implements physical attributes of CoreNet protocol  BFMs model buffer resources, significant towards finding deadlock issues  Embedded coverage using SV covergroups  Multitude of control parameters (run-time) to modify behavior at run-time Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 13
  14. 14. How SV helped  OOP concepts – Abstraction, Inheritance & Polymorphism  Object-based randomization and constraints programming  Enhanced inter-process synchronization and communication mechanisms  Fine grain process control ( fork…join)  No memory leaks ( automatic garbage collection)  Enhanced tasks and functions  Interfaces ( parameterized, nested)  Powerful assertions & functional coverage capabilities Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 14
  15. 15. SV Gotchas  Constraint-solving  Unsupported constructs (e.g. parameterized classes) Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 15
  16. 16. Corenet Fabric Testbench PA testcase SV Stim CoreNet™ Proc CoreNet™ Proc CoreNet™ Proc BFM BFM BFM CoreNet BFM CoreNet™ Coherency Fabric Memory Target DUV CoreNet BFM Memory Target CoreNet Monitors CoreNet BFM CoreNet BFM CoreNet BFM IO Bridge IO Bridge IO Bridge SV Stim SV Stim SV Stim Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 16
  17. 17. IO Bridge Testbench PA testcase SV Stim CoreNet BFM CoreNet BFM CoreNet BFM CoreNet BFM AltMaster AltMaster AltMaster CoreNet Monitor CoreNet BFM Memory Target CoreNet™ Fabric BFM CoreNet BFM Memory Target CoreNet Monitor DUV IO Bridge Monitor IP BFMs SV Stim Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 17
  18. 18. CoreNet Platform Testbench PA testcase SV Stim or PA testcase Core Complex CC CC 128KB Backside L2 Cache 128KB Backside L2 Cache 128KB Backside L2 Cache CoreNet Proc Power Architecture™ Power Architecture™ Power Architecture™ e500 Core e500 Core e500 Core BFM 32KB 32KB 32KB 32KB 32KB 32KB D-Cache I-Cache D-Cache I-Cache D-Cache I-Cache DUV 1MB DDR2/3 Front side Memory L3 Cache Controller CoreNet™ Coherency Fabric 1MB DDR2/3 Front side Memory L3 Cache Controller CoreNet Monitors L3 Cache CoreNet BFM IO Bridge IO Bridge IoMaster/Target IP BFM IP BFM SV Stim SV Stim Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 18
  19. 19. Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q&A Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 19
  20. 20. Successes  Successfully verified the entire CoreNet platform as an early adopter of System Verilog for testbenches.  Successfully applied advanced features of SV in creating a lean and efficient testbench with focus on reuse.  Reuse of CoreNet VIP for verification by cross-functional and cross-site teams.  Feature-rich testbench enabled early performance verification on RTL - helped flush out many performance bugs continued… Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 20
  21. 21. Successes  First Networking & Multimedia Group (NMG) SoC with fully integrated SV testbench  Sampled first silicon to customer in less than 3 weeks!  Customer is able to run 8-way MP software.  No major (show-stopper) functional CoreNet bugs in silicon  Lab Bugs/Verif Bugs = 0.7%  Found SV to be adequate for verifying complex designs. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 21
  22. 22. Agenda  QorIQ & CoreNet Platform Overview  Verification Challenges  Verification Methodology  Verification IP  Conclusions  Q&A Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 22
  23. 23. Q&A Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are TM the property of their respective owners. © Freescale Semiconductor, Inc. 2009. 23
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