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Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
Roy aerofone power_verif
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Roy aerofone power_verif

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  • 1. www.silabs.com Verifying Power Domains in AeroFONE® Subrata Roy Senior Design Engr, Wireless 10/23/06
  • 2. Silicon Labs Portfolio Wireless Wireline Broadcast MCU Core Capability Core Capability Core Capability Core Capability RF design in PLL and High Tuner and Demod System on a Chip CMOS Voltage Expertise Integration Products Products Products Products Aero® Transceivers Modem FM Tuners 8-bit, 8051, AeroFONE® Voice SiRX™ STB Receiver Mixed-Signal MCUs Power Amplifier Power XM Satellite Receiver Fixed-Function RF Synthesizers Timing solutions 2
  • 3. AeroFONE® based Design Si4300T Power Amplifier Si4905 AeroFONE: TX, ABB, DBB, PMU, Battery Charging Circuitry CP2102 USB to UART Bridge Si4700 FM Tuner 3
  • 4. AeroFONE® Power domains ♦ Motivations for Multiple Power Domains Power Saving : power what you need Power Saving : power as much as you need; Voltage scaling for different operating modes Backbias RAM, powerdown ROM Different voltages needed by the function Noise isolation ♦ Voltage Regulators Vpermanent Vgpio Vext_memory Vcore (Linear regulator, DCDC regulator) Vanalog VRF Vcustom_digital1 Vcustom_digital2 4
  • 5. Power Control Feedback loop ♦ The chip controls its power ♦ Make sure it is not stuck in a bad state; e.g., waiting for input through an un-powered path while powering-up Power domains P_ctl control status Vdd Voltage Battery Regulators 5
  • 6. Power Verification-1 ♦ Specify Map blocks to Power domain Reset & clocks Voltage modes, dynamic operating modes (load current) input power domains, output power domains pre-power domains : domains powered up before this block post-power domains: domains powered after this block is powered up ♦ Design : RTL: signal connectivity Interface Cells between power domains (level shifters, logic & noise isolators) have explicit supply pins; these cells are custom designed Analog components have explicit supply pins 6
  • 7. Power Verification-2 ♦ Static Verification: Checks conditions independent of stimulus; assuming specified constraints all inputs of the domain are defined Every domain can be reset at power up Correct level shifting All outputs to post-power domains are at 0 during ramp-up Lot of painful scripting & reviews ♦ Dynamic Verification : functional operation of the device exercising different power domains & power modes All possible power up sequences All possible sequences of power modes Use AMS methodology 7
  • 8. Assertions ♦ Check that the system is always in valid system power states ♦ Check that a transition from 1 valid system power state to another valid system power state satisfies all necessary conditions ♦ Examples If Vext_memory is in low power mode then no access to memory If Vgpio is in low power mode then no access to gpio pins except for some keypad pins 8
  • 9. Power Verification-3 ♦ Power Goals ♦ Design Level: Characterize Power usage of different blocks in different modes ♦ System Level: Use information from Power Characterization to build system level power models Example: DRX2 : 8 slots of p1-mode, 2 slots of p2-mode out of 816 slots 9
  • 10. Modeling ♦ The quality of dynamic verification depends on modeling ♦ Interface Cells: level shift, logic & noise isolators Voltage levels of power supply pins are modeled in Verilog-AMS Any error in voltage levels is indicated by driving X to logic signals as well as global error flags Lump any effect of the digital load to the Voltage signals of the interface cell ♦ All registers/outputs in a un-powered domain are forced to X ♦ The impact of power(vdd) on signals connected to an interface cell are modeled within the Verilog-AMS model of the interface cell ♦ Voltage Regulators Model impact of controls signals on voltage outputs Focus is on modeling the loop between Digital & analog domain feedback loops within the analog are ignored 10
  • 11. Interface Cells- AMS model ♦ New disciplines are defined for hv/lv logic in AMS ♦ AMS connectrules define the electrical equivalent of logic_hv/lv ♦ AMS automatically inserts connectors based on type vdd1 vdd2 LS_12.Cell Logic_hv Logic_lv AMS-model logic_hv_to_electrical connector electrical_to_logic_lv connector 11
  • 12. Summary ♦ Static Verification is well defined but requires lot of adhoc scripting – standardization will have big impact here ♦ Dynamic verification Better modeling of effects of system power states using AMS For unmodeled effects we use constraints to restrict digital behavior Example: Vgpio low power mode only allows access through some kepad pins Large number of combinations of power states and their sequencing 7 Regulators 3 power on events (power on key, RTC alarm, Charger insertion) Some regulators completely hardware controlled (configured by input pins); some are software controlled Based on ordering of input events and subsequent software control there are many possible sequences 12
  • 13. Wish List ♦ Efficient way to model effects of power modes/states ♦ Extension of our current modeling language (Verilog) but more efficient than AMS ♦ Some Objections different instances have different power contexts, keep power information seperate from design language constructs can address these issues (e.g., parameters, vunit binding in systemverllog) 13

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