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Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
Padhye dv club_low_power_verif_2006_11_20_ver0.1
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Padhye dv club_low_power_verif_2006_11_20_ver0.1

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  • 1. . Wireless Low Power and Verification Challenges Presented to DVClub, Austin, Tx Nov 20, 2006 . Milind Padhye, Noah Bamford, Ken Albin Freescale Semiconductor Inc. TM Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 2. Wireless Carriers Low Power Design is business critical need and has a direct impact to carrier revenue. If the cell phone is powered off, The source of revenue is off for carrier. Performance needed to sell the phone. Power needed to bring revenues. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 3. Wireless and Handheld Devices ►Standby & Talk time - Benchmark parameters in cell phone industry. ►Music playback time - Benchmark for MP3 capable phones. ►Frequent battery charging - Major negative in consumer mind. ►Increase performance with large battery – Increased Cost ►Increased Heat in phone – Increased liability and TCO. Power Performance ratio must be very high to win consumer mind. • End Consumers are becoming power aware and can make intelligent decisions and smart choices on power. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 4. Trends - GSM Phone Current 350 SGH-X497 GSM Voice Call Current (mA) 300 NGage QD 3395 SGH-C225 9500 N90 9 250 7260 V66 8 SGH-C225 SGH-E400 GSM Standby Current (mA) 3120 3620 200 SGH-E105 8800 3395 7270 7 6200 6010 6230i V60g T616 SGH-E730 150 6682 6 V180 SGH-E400 V400 Z500aSGH-E317 V66 V600 S710 PEBL V635 V360 9500 100 RAZR V3W800 5 T68i C331 K700i P900 ROKR EL NGage QD SGH-E105 3620 6010 4 V60g V600 V400 SGH-X497 50 T630 6682V360 V635 ROKR EL 3 6200 V180 3120 6230i 8800 SGH-E730 PEBL Z500a N90 7270 RAZR V3 P900 T630 S710 0 W800 T616 7260 1Q02 2Q01 3Q01 4Q01 1Q01 3Q02 4Q03 1Q03 2Q04 3Q04 4Q04 2Q05 3Q06 4Q06 1Q06 2Q07 3Q07 4Q07 2Q00 3Q00 4Q00 1Q00 4Q02 2Q03 3Q03 1Q04 3Q05 4Q05 1Q05 2Q06 07 2Q02 2 T68iC331 K700i SGH-E317 1Q 1 GSM Talk Current 0 3Q01 2Q02 3Q02 4Q02 1Q04 2Q05 3Q05 4Q05 2Q00 3Q00 4Q00 1Q00 2Q01 4Q01 1Q01 1Q02 2Q03 3Q03 4Q03 1Q03 2Q04 3Q04 4Q04 1Q05 2Q06 3Q06 4Q06 1Q06 2Q07 3Q07 4Q07 07 1Q GSM Standyby Current Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 5. Leakage Current in 65nm, Major concern for Wireless Design Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 6. It’s about Energy Goal: Extend Phone Battery Life Energy • Battery life is proportional to energy consumed • Energy is power consumed over time • Wireless designers must manage energy consumption. To extend battery life, designers must minimize active and leakage power. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 7. Problem Focus View Design Intent Hardware support for power gating, low-power idle modes, SRPG, AWB, DVFS, DPTC, Biasing techniques at all levels. Design RTL2gds, Power Integrity, Multimode synthesis, Placement, power Implementation grid creation, analysis, power estimation Design Behavioral and RTL verification, Gate level verification, testbench Verification styles, static and dynamic power Rule checking. Low Power Support library infrastructure with special cells. New cells and infrastructure parameters for cz. Multimode/multivoltage support infrastructure. PROCESS node Transistor design, Vt Optimization, memory bitcell design. Definitions custom and reusable analog. Silicon correlation. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 8. Low Power Design Needs ►Support Low Power Design Techniques thru the entire design flow using a single file format. • Design Representation Accurately define and capture the low power design intent, modes and constraints. • Design Implementation Floorplan and power grids. Common constraints for all tools (Synthesis, APR, timing, DFT) Design analysis tools with single power constraints. Accurate power estimation and measurements • Design Verification Voltage oriented simulators Various static power technique modeling and simulations. Silicon validation and correlation. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 9. Static Power Design ►Static Power is crucial for defining standby time of cell phone. ►Multiple Leakage Reduction Techniques • Active Well Biasing (AWB) • State Retention Power Gating (SRPG) • Save and Restore with power gating. (S&R PG) • Multi-Vt based design styles • Aggressive Voltage Reduction during standby mode (RV) • Device biasing. • Switches, Isolation collars and level shifters. ►Static Power a big part of active power • Use switches for power mode switching. • Thermal dissipation issues in packaging. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 10. Example Leakage Reduction Techniques C65 Leakage Reduction Example 1000 90 900 80 Battery Time Increase (%) 800 Leakage Current (uA) 70 700 60 600 50 500 40 400 30 300 200 20 100 10 0 0 Nominal RV AWB SRPG S&R PG SR/S&R SR/S&R PG PG/RV Techniques Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 11. Multi Voltage Design Styles - DVFS ►Voltage has quadratic effect on power. ►In Multivoltage design Style • Unused portion of design is switched off. • Low performance portion is running at lower voltage • High performance portion is at higher voltage. ►Voltage partitioning decisions are crucial and very key for power performance factor. ►Clocking is the major challenge for multivoltage designs. Need intelligent clock tree builders. ►Asynchronous protocols to enable efficient voltage partitioning. ►Design is optimized for multi voltage conditions. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 12. Isolation and Percolation VDD ►Picture power managed vs non power managed design implementation ►When a module is powered Module A Module B off, outputs will float. ►These outputs can corrupt the state of receiving modules. ►Modules must be isolated Controller VDD ►A separate logic is inserted to isolate and percolate. ► Logic State of isolation is I important and can cause Module A S Module B adverse effects if improper. O Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 13. Retention Verification ►A module can be turned off to Controller VDD save leakage. ►The state of module B must be retained during power off. I ►Special circuits and flipflops Module B Module A S have been created for this O purpose. ►Need to verify VDD • The state was saved correctly. Controller • State restored correctly. • System can function after powerup. ►The controller must ensure the I Module B correct save and restore Module A S In sequence. O Retention Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 14. Voltage and Frequency Variation VDD ►Voltage of module A is reduced Controller when lower performance need. ►Change of voltage is associated to change of Clock. Module B I ►Isolation is now Lisolator. (level Module A S In Shifter & isolation) O Retention ►Need to verify • System performance state. • Prepare & communicate regarding Controller VDDX VDD voltage change.. • System operational during change. • System operational after change. ►The controller must ensure the correct operating sequence and L Module B monitor progress. Module A I In S O Retention Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 15. Power Architecture Verification ►Architectural analysis required to achieve efficient voltage partition. ►Global Power Controller • Partial or full power up and power down is a controlled sequence. • Verify the sequence control and state machine completely. • The Global Power Controller should be capable of capturing and relinquishing the controls appropriately. ►The system should be functional and must be verified • During power off process • After power off has completed • Power up decision making • During power up • Full recovery after power-up. ►Ensure consistency of Power Programming Model in specification. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 16. How Does the world of Verification Change ►Verilog does not have a concept of power on/off. ►Verilog does not have association of voltage levels. ►Power shut off and multi voltage design style has brought in multiple new components in chip. ►Gate level and circuit level simulations are expensive and time consuming and very late to fix the problems. ►Functional coverage of state of system at the time of power off and activities following power up should be gathered ►All power related features must be checked at RTL stage. ►Power Equivalency Checks needed between RTL & gate. ►Power estimation in various functional mode needs to be integrated with power verification. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.
  • 17. Freescale™ and the Freescale logo are trademarks TM of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2006.

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