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Nilesh ranpura systemmodelling

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  • Silicon/Chip Realization Services eInfochips’ suite of solutions and services addresses all stages of a chip lifecycle, ranging from Design, Verification, Physical Design to Continuation Engineering Services. It helps silicon vendors reduce their cost and development time through IP leveraged design services that address to the complete chip lifecycle.
  • Transcript

    • 1. “ Modeling System behaviors ”….A better Paradigm on prototyping -Nilesh Ranpura
    • 2. Electronic System Structure Hardware development process Software development process System development process Software input/output Hardware input/output Abstraction trade offs
    • 3. System Abstraction and Development Process
      • System Development happens this way
      • Because,
      • “ Abstraction layers” ensure threads running concurrently
      • 2. Different approach of specs
      • due to different types of team
      • 3. More than one customer with different nature/features
      SPI 5 Design Flow Concept Chip/Block specs Product Specs System data/environment Board/proto specs Architecture specs Not documented Reference Platforms Hardware and proto specs
    • 4. Which are those System Properties ? Environmental System Properties Hardware & Software co-exist Safety/ Standards/ Compliance Performance New Approaches : Green mode Error injection Mixed Signal
    • 5. Compute Blade PCIe Inter-Domain Switch I/O Hub CPU CPU Memory Memory Memory Memory Local Storage Processor SATA / SAS Expander Dual GbE Controller Dual GbE Controller I/O Blade Processor Compute Blade PCIe Inter-Domain Switch I/O Hub CPU CPU Memory Memory Memory Memory (1)PCIe Switch Applications – System Interconnect Processor FC FC Fibre Channel Controller Storage Blade PCIe System Interconnect Switch GbE GbE GbE GbE Compute Blade I/O Hub CPU CPU Memory Memory Memory Memory
    • 6. Model parameter Values ECRC, etc Misc. Testcase 20/100/500/5000 No of packets Testcase 2/4/5/6/8 Active Port Testbench PM or non PM State Testcase 2.5Ghz, 5Ghz Speed Testbench Multicast, One to one, Many to one Traffic pattern Testcase MRD,MWR,IRD Packet types Testcase 128/256/512 Payload Testbench 128 MPS Remark Value Parameter
    • 7. Model Latency definition
      • Latency is the delay between starting and completing action
      • Latency Definition:
      • Throughput (pkts/sec) = (total number of pkts(i.e. 500)/(time_t1 - time_t0))
      • Throughput (bits/sec) = (throughput (pkts/sec) * length * 32)        In this case, length = Payload size + 3DW header Theoretical max throughput assumes a 20 byte framing overhead on top of payload.
      • After removing 8b/10 coding, useful x8 Gen2 unidirectional throughput is 4 GB/s.
      • (4 GBps * payload) / (payload + 20) = theoretical max (second column above)
      97% 3.360 3.459 128 95% 2.905 3.048 64 81% 2.000 2.462 32 Switch efficiency (Actual/Theoretical) % Actual throughput (GBps) Theoretical(GBps) Payload (Bytes)
    • 8. Usage Model and Error Model I/O CPU NTB P2P P2P P2P P2P P2P NTB I/O I/O I/O I/O CPU NTB P2P P2P P2P P2P P2P NTB I/O I/O I/O ... Internal Switch Error I/O 1GbE PCIe Switch I/O Hub CPU Memory ... I/O 1GbE I/O 1GbE PCIe Switch I/O Hub CPU Memory ... ... I/O 1GbE External Error
    • 9. (2)Modeling Channel properties and Mixed signal for Simple Link
      • Model as much as digital blocks up to last stage
      • Last analog Transceiver can be modelled and converted
      • in to Differential digital by just inverting it.
      • 3. Next slide depicts digital noise and transmission model
    • 10. (2)Introduce Digital Noise
              • Send 22, 20. 15, 5(which are analog sample’s value) in digital format but in parallal. So no. of data lines = no. of analog samples * 8 bit
              • Introduce noise in numbers by inversion or value changing.
      • Inversion
      • bit stuffing
      • dummy bits
      Noise Model 22 20 15 5 4 3 8 bit value of 20(sample value)
      • Inversion
      • bit stuffing
      • dummy bits
      Noise Model
    • 11. (2)Actual System High speed PHY MAC PAM modulation and Signal path processing block
    • 12. (2)Actual System
              • Modeled PAM modulation scheme over digital block
              • Created noise model to make noise variation between -20dB to 30dB for high speed signals on Cable.
              • Simulated virtual NEXT, FEXT, ISI with predictable noise model.
              • Loop back and system loop back mode tested
      High speed PHY MAC PAM modulation and Signal path processing block
      • Inversion
      • bit stuffing
      • dummy bits
      Noise Model
    • 13. Thank You, All…!