OpenSPARC on FPGAs

Durgam.Vahia@Sun.Com

OpenSPARC Engineering & Partnership Development
Sun Microsystems, Inc.


DV Club...
64 bits, 64 threads, and free


OpenSPARC
                                          OpenSPARC.net
                        ...
64 bits, 64 threads, and free


Agenda
  Chip Multi-threading
  OpenSPARC
  Motivation for the FPGA port
  Implementat...
64 bits, 64 threads, and free


Chip Multi-threading (CMT)




 www.OpenSPARC.net   DV Club – Silicon Valley              ...
64 bits, 64 threads, and free


UltraSPARC T1
                              SPARC V9 ISA, 64-bit
                        ...
64 bits, 64 threads, and free


SPARC Core Pipeline



                                                                  I...
64 bits, 64 threads, and free


UltraSPARC T2
     FB DIMM     FB DIMM      FB DIMM     FB DIMM                Eight core...
64 bits, 64 threads, and free


OpenSPARC Bundles
  Hardware
      −   HDL design files written in Verilog
      −   Veri...
64 bits, 64 threads, and free


Source browser at www.opensparc.net




 www.OpenSPARC.net   DV Club – Silicon Valley     ...
64 bits, 64 threads, and free


                           OpenSPARC Ecosystem

Area                Community             ...
64 bits, 64 threads, and free


OpenSPARC momentum



           Innovation
             will happen everywhere


        ...
64 bits, 64 threads, and free


Agenda
  Chip Multi-threading
  OpenSPARC
  Motivation for the FPGA port
  Implementat...
64 bits, 64 threads, and free


Why FPGAs?
  
      Community requested it
      −   As a platform for experimentation
  ...
64 bits, 64 threads, and free


OpenSPARC/Xilinx FPGA Evaluation Kit




        Available from http://www.digilentinc.com...
64 bits, 64 threads, and free


FPGA implementation – Key objectives
  
      Proliferation of OpenSPARC & Xilinx
      F...
64 bits, 64 threads, and free


Processor core changes
  
      Primarily to reduce the area foot-print of
      the mult...
64 bits, 64 threads, and free


OpenSPARC FPGA System
                                                                    ...
64 bits, 64 threads, and free


Software Stack
 • Out-of-the-box
   operating system
   installation
 • Boots from a virtu...
64 bits, 64 threads, and free


Results – Capacity Utilization
 • Using Xilinx XC5VLX110T device
 • Synthesis results (no ...
64 bits, 64 threads, and free


Results – Community building
• 50+MHz OpenSPARC FPGA system
   – Platform for experimentat...
64 bits, 64 threads, and free

Results - Partner




   http://www.beecube.com



  www.OpenSPARC.net     DV Club – Silico...
64 bits, 64 threads, and free


Key Learnings
• FPGA capacity and performance are
  increasing each successive generation,...
64 bits, 64 threads, and free


Web pointers
  Program
      − http://www.opensparc.net
  Publications
      − http://ww...
OpenSPARC on FPGAs
Durgam.Vahia@Sun.Com

OpenSPARC Engineering & Partnership Development
Sun Microsystems, Inc.

www.OpenS...
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Durgam vahia open_sparc_fpga

  1. 1. OpenSPARC on FPGAs Durgam.Vahia@Sun.Com OpenSPARC Engineering & Partnership Development Sun Microsystems, Inc. DV Club – July 2009 www.OpenSPARC.net 1
  2. 2. 64 bits, 64 threads, and free OpenSPARC OpenSPARC.net  Open source variants of Sun’s CMT microprocessors UltraSPARC T1 UltraSPARC T2  Governed by GPL version2  Widely used in Linux distribution  US export compliant for world- wide distribution www.OpenSPARC.net DV Club – Silicon Valley 2
  3. 3. 64 bits, 64 threads, and free Agenda Chip Multi-threading OpenSPARC Motivation for the FPGA port Implementation Results Resources Q & A www.OpenSPARC.net DV Club – Silicon Valley 3
  4. 4. 64 bits, 64 threads, and free Chip Multi-threading (CMT) www.OpenSPARC.net DV Club – Silicon Valley 4
  5. 5. 64 bits, 64 threads, and free UltraSPARC T1  SPARC V9 ISA, 64-bit  Eight cores, four threads each  Single issue 6-stage pipe  High BW 12-way associative 3 MB on-chip L2 cache  4 DDR2 channels  Shared on-chip FPU  Chip IO through JBUS www.OpenSPARC.net DV Club – Silicon Valley 5
  6. 6. 64 bits, 64 threads, and free SPARC Core Pipeline Interface to the core www.OpenSPARC.net DV Club – Silicon Valley 6
  7. 7. 64 bits, 64 threads, and free UltraSPARC T2 FB DIMM FB DIMM FB DIMM FB DIMM  Eight cores, eight threads each FB DIMM FB DIMM FB DIMM FB DIMM  8-stage single issue pipe MCU MCU MCU MCU  One FPU per core L2$ L2$ L2$ L2$ L2$ L2$ L2$ L2$  16-way associative 4 MB Full Cross Bar on-chip L2 cache C0 C1 C2 C3 C4 C5 C6 C7  Four dual channel FPU FPU FPU FPU FPU FPU FPU FPU FBDIMM  Two 10G Ethernet NIU Sys I/F PCI-Ex  PCIe and Crypto (E-net+) Buffer Switch Core excluded Power 60 – 123W 2x 10GE Ethernet x8 @2.5GHz www.OpenSPARC.net DV Club – Silicon Valley 7
  8. 8. 64 bits, 64 threads, and free OpenSPARC Bundles Hardware − HDL design files written in Verilog − Verification test-bench, diagnostics, scripts − Synthesis scripts for ASIC and FPGA − Lots of documents Software − SPARC Architecture Model (SAM) source − Full-system simulator (Legion) source − Hypervisor, Open Boot PROM (OBP) source − Solaris10 disk image − Scripts to build all the components www.OpenSPARC.net DV Club – Silicon Valley 8
  9. 9. 64 bits, 64 threads, and free Source browser at www.opensparc.net www.OpenSPARC.net DV Club – Silicon Valley 9
  10. 10. 64 bits, 64 threads, and free OpenSPARC Ecosystem Area Community Universities Partners  OpenSPARC.net  Center of Excellence  FPGA implementation  Contests  Collaborations  ASIC implementation  Blogs Tool Kit  Conferences  Curriculum  EDA  Research  SoC implementation  Tutorials  Tutorials  Foundry relationship Operating System Port  Evangelize OpenSPARC  Research publications  Chip spins Focus  Encourage contributions  Textbooks  Coprocessors  Build knowledgebase  Shared coursework  CMT EDA tools Encourage community innovation www.OpenSPARC.net DV Club – Silicon Valley 10
  11. 11. 64 bits, 64 threads, and free OpenSPARC momentum Innovation will happen everywhere More than 11,000 downloads Includes academic and commercial interests www.OpenSPARC.net DV Club – Silicon Valley 11
  12. 12. 64 bits, 64 threads, and free Agenda Chip Multi-threading OpenSPARC Motivation for the FPGA port Implementation Results Resources Q & A www.OpenSPARC.net DV Club – Silicon Valley 12
  13. 13. 64 bits, 64 threads, and free Why FPGAs?  Community requested it − As a platform for experimentation − Gentler introduction to server class processor design − Basic building block for more interesting/complex designs  Need off-the-shelf FPGA board that is − Large enough for “good-sized” design points − At the “right” price point − Available world-wide www.OpenSPARC.net DV Club – Silicon Valley 13
  14. 14. 64 bits, 64 threads, and free OpenSPARC/Xilinx FPGA Evaluation Kit Available from http://www.digilentinc.com/v5osdk www.OpenSPARC.net DV Club – Silicon Valley 14
  15. 15. 64 bits, 64 threads, and free FPGA implementation – Key objectives  Proliferation of OpenSPARC & Xilinx FPGA Technology − Make OpenSPARC FPGA-Friendly − Create reference design with complete system functionality − Boot Solaris and Linux − Open it up .. − Seed ideas in the community www.OpenSPARC.net DV Club – Silicon Valley 15
  16. 16. 64 bits, 64 threads, and free Processor core changes  Primarily to reduce the area foot-print of the multi-threaded SPARC core  Recode custom SRAM cells for better resource utilization  Parameterizable single- and multi-thread options  Removal of all the asynchronous logic – no clock gating  Simplified reset  Only flops, no latches  Reduce multi-port SRAM arrays  Removable logic – Crypto accelerator, Floating-point Overall 50% reduction in area www.OpenSPARC.net DV Club – Silicon Valley 16
  17. 17. 64 bits, 64 threads, and free OpenSPARC FPGA System Xilinx Embedded Developer’s FPGA Boundary External DDR2 Dimm (EDK) Design MCH-OPB MemCon CCX-FSL Microblaze Proc Microblaze Debug UART SPARC T1 Core Interface SPARC T1 UART 10/100 Ethernet www.OpenSPARC.net DV Club – Silicon Valley 17
  18. 18. 64 bits, 64 threads, and free Software Stack • Out-of-the-box operating system installation • Boots from a virtual disk in RAM which Solaris/Linux holds the Solaris Open Boot PROM (OBP) binaries Reset Hypervisor Code • Able to boot either Linux or OpenSolaris • Entire software stack is open source www.OpenSPARC.net DV Club – Silicon Valley 18
  19. 19. 64 bits, 64 threads, and free Results – Capacity Utilization • Using Xilinx XC5VLX110T device • Synthesis results (no SPU, 16 TLB entries) 1-thread core: 31475 LUT (45%), 115 BRAM (78%) 4-thread core: 51558 LUT (74%), 115 BRAM (78%) (synthesized with Synplicity Synplify Pro) • Complete system: SPARC core, MicroBlaze, 2 UARTs, Ethernet, and DDR2 controller: 1-thread core: 38271 LUT (55%), 128 www.OpenSPARC.net DV Club – Silicon Valley 19
  20. 20. 64 bits, 64 threads, and free Results – Community building • 50+MHz OpenSPARC FPGA system – Platform for experimentation for HW developers – Building blocks to design truly multi-core, multi-thread processors – Based on open-source technology – Costs ~$700 for academics ($2,000 for others) – Higher-end boards available for larger design points • Used in 200+ Universities world-wide – Architectural exploration, fault tolerance, reconfigurable computing, low power architectures Free download, visit http://www.opensparc.net www.OpenSPARC.net DV Club – Silicon Valley 20
  21. 21. 64 bits, 64 threads, and free Results - Partner http://www.beecube.com www.OpenSPARC.net DV Club – Silicon Valley 21
  22. 22. 64 bits, 64 threads, and free Key Learnings • FPGA capacity and performance are increasing each successive generation, however – Optimal use of these resources is a big challenge • FPGA design/coding is significantly different from ASIC style – E.g. pipeline bypass, latches, clock gating creates both functional and P&R issues – For prototyping, create special FPGA models • FPGA tools are full of quirks – Invest in verification at each level – RTL, gate, layout, system www.OpenSPARC.net DV Club – Silicon Valley 22
  23. 23. 64 bits, 64 threads, and free Web pointers Program − http://www.opensparc.net Publications − http://www.opensparc.net/publications/ Downloads − http://www.opensparc.net/opensparc-t1/downloads.html − http://www.opensparc.net/opensparc-t2/downloads.html  Participation (Forums) − http://forums.sun.com/category.jspa?categoryID=120  FPGA development boards − http://www.digilentinc.com/v5osdk www.OpenSPARC.net DV Club – Silicon Valley 23
  24. 24. OpenSPARC on FPGAs Durgam.Vahia@Sun.Com OpenSPARC Engineering & Partnership Development Sun Microsystems, Inc. www.OpenSPARC.net www.OpenSPARC.net 24

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