CMOS
INTRODUCTION   Integrated circuits: many transistors on single chip.   Metal Oxide Semiconductor (MOS) transistor    Fa...
INTRODUCTION         MOSFET NMOS      PMOS   CMOS
MOSFET                      Gate             Drain              SourceMetal Oxide Semiconductor Field Effect TransistorSou...
NMOSP-type substrateN-type dopant for Source & DrainInversion layer is formed to conduct electricity
PMOSN-type substrateP-type dopant for Source & DrainInversion layer is formed to conduct electricity
CMOSA combination of both NMOS & PMOS technologyMost basic example: inverter
PROCESS FLOW         WELL FORMATION        ISOLATION FORMATION        TRANSISTOR MAKING         INTERCONNECTION
CMOS FABRICATION PROCESSwell formation    Start with clean p-type substrate (p-type      wafer)
CMOS FABRICATION PROCESSwell formation    Grow epitaxy layer (made from SiO2) as mask     layer for well formation
CMOS FABRICATION PROCESSwell formation                                      Well will be formed                           ...
PHOTOLITHOGRAPHY (CED)photoresist                Si02         Photoresist   coating (C) P-substrate   UV light           ...
ETCHING              Removing   the unwanted patternP-substrate    by wet etching              Resistclean              ...
CMOS FABRICATION PROCESSwell formation                         Phosphorus ion          Ion bombardment by ion implantatio...
CMOS FABRICATION PROCESSIsolation formation                   Thick oxide     IncreaseSiO2 thickness by oxidation at high...
CMOS FABRICATION PROCESStransistor making             nmos will     pmos will            be formed     be formed          ...
CMOS FABRICATION PROCESStransistor making                     Gate oxide     Grow very thin gate oxide at elevated      te...
CMOS FABRICATIONPROCESStransistor making                      polisilicon     Deposit polisilicon layer
CMOS FABRICATIONPROCESStransistor making                             gate    Photolithography (photo) and etching to     f...
CMOS FABRICATIONPROCESStransistor making                          Arsenic ionphotoresist          Photo process to define...
CMOS FABRICATION PROCESStransistor making                             VDD          source   drain    contact    Nmos’s   ...
CMOS FABRICATIONPROCESStransistor making                         Boron ion photoresist         Photo process to define th...
CMOS FABRICATIONPROCESStransistor making           GND          contact    Pmos’s    Pmos’                      drain   so...
CMOS FABRICATIONPROCESSinterconnection CVDOxide        Deposit CVD Oxide layer through out         wafer surface
CMOS FABRICATION PROCESSInterconnection                       contact    Photo and etching process to make contact
CMOS FABRICATION PROCESSinterconnection       Metal 1           Metal 1 deposition throughout wafer            surface
CMOS FABRICATIONPROCESSinterconnection Photo and etching processes to pattern  interconnection
ADVANTAGES  High   operating speed    Low cost  Very   low static power consumption  High   degree of noise immunity.
DISADVANTAGESOptical lithography is limited by the light frequency.Material limitationsSpace limitations
APPLICATIONS Integrated Circuits Data converters Integrated transceivers Image sensors Logic circuits
CONCLUSION CMOS Transistors are stack of gate, oxide, silicon Build logic gates out of switches Draw masks to specify l...
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Cmos

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Cmos

  1. 1. CMOS
  2. 2. INTRODUCTION Integrated circuits: many transistors on single chip. Metal Oxide Semiconductor (MOS) transistor Fast, cheap, low-power transistors Complementary: mixture of n- and p-type leads to less power
  3. 3. INTRODUCTION MOSFET NMOS PMOS CMOS
  4. 4. MOSFET Gate Drain SourceMetal Oxide Semiconductor Field Effect TransistorSource ( Phosphorous, Boron)Drain ( Phosphorous, Boron)Gate (Aluminum, Polysilicon)
  5. 5. NMOSP-type substrateN-type dopant for Source & DrainInversion layer is formed to conduct electricity
  6. 6. PMOSN-type substrateP-type dopant for Source & DrainInversion layer is formed to conduct electricity
  7. 7. CMOSA combination of both NMOS & PMOS technologyMost basic example: inverter
  8. 8. PROCESS FLOW WELL FORMATION ISOLATION FORMATION TRANSISTOR MAKING INTERCONNECTION
  9. 9. CMOS FABRICATION PROCESSwell formation Start with clean p-type substrate (p-type wafer)
  10. 10. CMOS FABRICATION PROCESSwell formation Grow epitaxy layer (made from SiO2) as mask layer for well formation
  11. 11. CMOS FABRICATION PROCESSwell formation Well will be formed here By photolithography and etching process, well opening are made photolithography and etch processes are shown in next slides
  12. 12. PHOTOLITHOGRAPHY (CED)photoresist Si02 Photoresist coating (C) P-substrate UV light Masking and exposure under mask UV light(E) Resist dissolved after Opaque area developed (D) P-substrate ◦ Pre-shape the well pattern at Transparent area resist layer
  13. 13. ETCHING Removing the unwanted patternP-substrate by wet etching Resistclean Desired pattern formedP-substrate
  14. 14. CMOS FABRICATION PROCESSwell formation Phosphorus ion Ion bombardment by ion implantation SiO2 as mask, uncovered area will exposed to dopant ion
  15. 15. CMOS FABRICATION PROCESSIsolation formation Thick oxide IncreaseSiO2 thickness by oxidation at high temperature Oxide will electrically isolates nmos and pmos devices
  16. 16. CMOS FABRICATION PROCESStransistor making nmos will pmos will be formed be formed here here By photolithography and etching process, pmos and nmos areas are defined
  17. 17. CMOS FABRICATION PROCESStransistor making Gate oxide Grow very thin gate oxide at elevated temperature in very short time
  18. 18. CMOS FABRICATIONPROCESStransistor making polisilicon Deposit polisilicon layer
  19. 19. CMOS FABRICATIONPROCESStransistor making gate Photolithography (photo) and etching to form gate pattern
  20. 20. CMOS FABRICATIONPROCESStransistor making Arsenic ionphotoresist Photo process to define the nmos active (source and drain) area and VDD contact Ion implantation with Arsenic ion for n+ dopant. Photoresist and polysilicon gate act as mask
  21. 21. CMOS FABRICATION PROCESStransistor making VDD source drain contact Nmos’s Source and drain with VDD contact formation Resist removal
  22. 22. CMOS FABRICATIONPROCESStransistor making Boron ion photoresist Photo process to define the GND contact and pmos active area (source and drain) Ion implantation with boron for p+ dopant Photoresist and gate act as mask
  23. 23. CMOS FABRICATIONPROCESStransistor making GND contact Pmos’s Pmos’ drain source Pmos’s source and drain formation with GND contact Resist removal
  24. 24. CMOS FABRICATIONPROCESSinterconnection CVDOxide Deposit CVD Oxide layer through out wafer surface
  25. 25. CMOS FABRICATION PROCESSInterconnection contact Photo and etching process to make contact
  26. 26. CMOS FABRICATION PROCESSinterconnection Metal 1 Metal 1 deposition throughout wafer surface
  27. 27. CMOS FABRICATIONPROCESSinterconnection Photo and etching processes to pattern interconnection
  28. 28. ADVANTAGES  High operating speed  Low cost  Very low static power consumption  High degree of noise immunity.
  29. 29. DISADVANTAGESOptical lithography is limited by the light frequency.Material limitationsSpace limitations
  30. 30. APPLICATIONS Integrated Circuits Data converters Integrated transceivers Image sensors Logic circuits
  31. 31. CONCLUSION CMOS Transistors are stack of gate, oxide, silicon Build logic gates out of switches Draw masks to specify layout of transistors
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