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Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
Aicd cmos layouts
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Aicd cmos layouts

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analog electronics

analog electronics

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  • 1. Analog IC Design BITS Pilani Pilani Campus ANU GUPTAp
  • 2. BITS PilaniBITS Pilani Pilani Campus Analog Layout Techniques
  • 3. Organisation • Design rules, Schematic to layout, vice versa, • cross-sectional diagram, big layouts • Matched componentsp  Over-etching errors unit components designunit components design design using non unit component  Boundary condition matching Boundary condition matching Common centroid layout, parasitic cap estimation BITS Pilani, Pilani Campus
  • 4. Scalable design rules-----same set can be used for next tech generation by changing λ. Worst case values of spacings, widths etc. are used , so can’t be an optimized set. e. g. MOSIS design rulesg g Absolute design rules----optimized set but same set can’t be used for next tech gen. Entire new set is to be created. BITS Pilani, Pilani Campus
  • 5. Tanner BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 6. 4 NAND GATES4 NAND GATES
  • 7. CADENCE
  • 8. MOS LAYOUT λ λ 2λ 2λ BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 λ 5λ
  • 9. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 10. Junction cap- single transistorsingle transistor BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 11. Other layouts of MOS Annular transistor BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Elongated annular transistor
  • 12. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 13. Dense MOS layouts metal1metal1 metal2 B t t i t BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Waffle transistor Bent transistor Compute w/L?
  • 14. Circuit And Layout BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956 Try more examples
  • 15. How to reduce parasitic capacitances? Careful layout by junction sharing
  • 16. CAPACITOR LAYOUTS BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 17. RESISTOR LAYOUT BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 18. Matching Issues Large device => many small unit devicesg y Same boundary conditions for devices BITS Pilani, Pilani Campus
  • 19. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 20. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 21. Overetching – MOS dimensions (W/L)u = 8um/2um= 4 desired MOS dimensions After over etching --- (W/L)u = 7um/1um= 7; 0.5um= ∆e LL ∆e Poly layer w Over etched Poly layer BITS Pilani, Pilani Campus
  • 22. Absolute dimension of MOS Remedy---use Unit components w=L (W/L)u = 10um/10um, RATIO=1 Remedy---use Unit components w=L After fab. (W/L)u  8um/8um, RATIO=1 Conclusion—Abs. dimensions change, ratio does not changechange BITS Pilani, Pilani Campus
  • 23. Ratio of matched devices • (W/L)1 = 2, (W/L)2 = 8, ratio= 4 Ratio of matched devices ( )1 , ( )2 , • We take unit device (W/L)u = 10um/10um • After fab. (W/L)u  8um/8um( )u (W/L)2 8(W/L)u 4 ( )2 ( )u (W/L)1 2(W/L)u = =4 Thus, ratio remains same, if same unit device is used
  • 24. Application of technique BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 25. BITS PilaniBITS Pilani Pilani Campus Layout of CAPACITORSLayout of CAPACITORS
  • 26. CAPACITOR LAYOUTS BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 27. Over-Etching BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 28. Let C1/ C2 = 3.4 = 2+1.4 = [6/3] + [1.4/1][6/3] [1.4/1] [6/3]---can be implemented by using unit[6/3]---can be implemented by using unit capacitors [1 4/1]---we require non unit capacitor[1.4/1]---we require non unit capacitor Mismatch can occur due to second term BITS Pilani, Pilani Campus
  • 29. No mismatch conditionNo mismatch condition • We should design non unit cap Such thatWe should design non unit cap. Such that ratio (1.4) remains constant even after overetchingoveretching H t d i ?• How to design? • What is the condition?
  • 30. Condition = c1 c2c εr1= εr2 BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 31. Non unit sized cap dim. estimation = 1 4 estimation = 1.4 BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 32. BITS PilaniBITS Pilani Pilani Campus Boundary condition matchingBoundary condition matching Common centroid layout
  • 33. What if unit devices change randomly?g y Since one device is facing larger change in dimension,g g g maintaining constant ratio would be difficult. So We should have same change in all unit devices how?So, We should have same change in all unit devices. how? Inter-digitization
  • 34. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 35. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 36. Reduce mismatches BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 37. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 38. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 39. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 40. D DD S SS S S
  • 41. Bulk (backgate contact) BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 42. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 43. RESISTOR LAYOUT BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 44. Big Resistor BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 45. BIG RESISTOR (unit components) BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 46. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 47. BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 48. Multi fingered Common Centroid layoutCommon Centroid layout Parasitic cap. calculation of MOS device BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 49. 20λ 6λ 6λ 6λ 5λ 5λ BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 50. Fingered layout BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 51. View of fingered layout BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
  • 52. BITS PilaniBITS Pilani Pilani Campus ENDEND

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