Timing

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Timing

  1. 1. Gate Delay Propagation Delay (inverting)• Transistors within a gate take a finite amount of A Y time to switch. This means that a change on the input of a gate takes a finite amount of time to Signal rise time cause a change on the output. Signal fall time• This time is known as Propagation Delay H• Smaller transistors means faster switching times. A Semiconductor companies are continually finding L tphl new ways to make transistors smaller, which means tplh transistors are faster, and more can fit on a die in H the same area. Y L BR 1/99 1 BR 1/99 2Propagation Delay (non inverting) Propagation Delay Definitions H Y • Tplh -- time between a change in an input and a A low to high change on the output. Measured from 50% point on input signal to 50% point on the output signal. The ‘lh’ part (low to high) refers to H OUTPUT change, NOT input changeA • Tphl -- time between a change in an input and a L tplh high to low change on the output. Measured from tphl H 50% point on input signal to 50% point on the output signal. The ‘hl’ part (high to low) refers toY L OUTPUT change, NOT input change BR 1/99 3 BR 1/99 4Propagation Delay (non inverting) DFF Timing B Y A • Propagation Delay S – C2Q: Q will change some propagation delay after change in C. Value of Q is based D QEach Input to Output path has its own delay: on D input for DFF. – S2Q, R2Q: Q will change some propagation C A2Y_tplh, A2Y_tphl, B2Y_tplh, B2Y_tphl delay after change on S input, R input RThese delays can be different. – Note that there is NO propagation delay D2Q for DFF!For simplicity, may just assign one delay for entire gate: Y_tpd – D is a Synchronous INPUT, no prop delayDatabooks give typical and maximum propagation delays value for synchronous inputsfor combinational outputs. BR 1/99 5 BR 1/99 6 1
  2. 2. Setup, Hold Time Setup, Hold Times tsu thd • Synchronous inputs (e.g. D) have Setup, Hold time specification with respect to the CLOCK C input • Setup Time: the amount of time the synchronous input (D) must be stable before the active edge of Stable clock D changing D changing • Hold Time: the amount of time the synchronous input (D) must be stable after the active edge of If changes on D input violate either setup or hold clock. time, then correct FF operation is not guaranteed. Setup/Hold measured around active clock edge. BR 1/99 7 BR 1/99 8 Sequential System Timing Longest Paths in Sequential System Diagram n m Combinational Paths to check: k-bit Logic k-bit A. Clock to Output delay: Tc2q + Tcomb_Q2O max Present State Circuit Next State Value Tcomb_Q2O is longest path from Q output to any output Value k DFF k Q D clk B. Register to Register delay: Tc2q + Tcomb_Q2D max + Tsetup Tcomb Q2D is longest path from Q dff output to D dff inputQuestion: What is the MAXIMUM frequency of operation ofthis system? C. Pin to Pin combinational delay: Tcomb_I2O max Maximum Frequency = 1/ (longest delay path) (input pin to output pin, no intervening registers) What are longest paths??? Typically, path “B” is the worst case. BR 1/99 9 BR 1/99 10 Inputs/Outputs Registered Hold Time and Shortest Paths Very often, all inputs and outputs are registered. Then register- Thold to-register delay will almost always determine maximum D Combinational frequency. N Q D Logic K Q Tsetup C N Tpd min C K D Combinational N Q D Logic K Q C N Tpd max C2Q C K To satisfy hold time: C2Q Tc2q + Tpd (minimum) >= Thold delay = Tc2q + Tpd max + Tsetup This is normally easily satisfied in a sequential system. BR 1/99 11 BR 1/99 12 2
  3. 3. Toggle Frequency Setup, Hold Time for External Inputs External inputs are buffered through pad drivers and may go through combinational logic before they reach a synchronous toggle frequency = 1 /(C2Q + Tsetup) input. This buffering adds propagation delay. How does this D assume wire delay is neglible propagation delay affect the EXTERNAL setup and hold time???? Q ASIC DIN Thd, Tsu C What about setup time? Thd, Tsu Comb Log D Y Q 0 CLK Comb Log C Tc2q + Tpd (min) >= Thold Tcq > Thold What is Thd, Tsu for DIN? It is NOT the same as for Thd, assuming zero wire delay Tsu of the internal D FF!!!!!!! Thd, Tsu for DIN is specified in the DATASHEET for design. BR 1/99 13 BR 1/99 14 Calculating External Setup times Calculating External Hold times Tpd DIN Tpd DIN ASIC ASICDIN Tsu DIN Tsu Comb Log D Comb Log D Q QCLK Comb Log CLK Comb Log C C Tpd Clk Tpd Clk Worst case setup time for DIN occurs when ‘DIN’ is Worst case hold time for DIN occurs when ‘CLK’ is DELAYED relative to CLK. Means clock edge arrives DELAYED relative to DIN. Means clock edge arrives late, early, requiring DIN to be ready sooner. requiring DIN to hold its value longer. Din Setup = Tsu + Tpd DIN (max) - Tpd CLK (min) Din Hold = Thd + Tpd CLK (max) - Tpd DIN (min) BR 1/99 15 BR 1/99 16 A Timing Example Timings 1 ns U5 U6 A Y Max Register to Register Delay U7 U2 Tc2q + U3 Tpd + U1 Tsu = 5 + 8 + 3 = 16 ns. 7 ns 6 ns U1 U2 9 ns D D A setup time = Tsu + A2D Tpd max - Clk Tpd min Q Q = Tsu + (Tpd U3 + Tpd U7) - Tpd U8 U4 C C = 3 + (8 + 1) - 2 = 10 ns DFFs : U3 Tsu = 3 ns A hold time = Thd + Clk Tpd max - A2D Tpd minCK U8 8 ns Thd = 4 ns = Thd + Tpd U8 - (Tpd U4 + Tpd U7) Tc2q = 5 ns = 4 + 2 - (7 + 1) = -2 ns 2 ns BR 1/99 17 BR 1/99 18 3
  4. 4. Timings (Cont) DataSheet Clock to Out = U8 Tpd + U2 Tc2q + U5 Tpd + U6 Tpd Parameter Description Min Max Units = 2 + 5 + 9 + 6 = 22 ns Tclk Clock Period 22 ns Fclk Clock Frequency 45.5 Mhz Atsu A setup time 10 ns Pin to Pin Combinational Delay (A to Y) Athd A hold time -2 ns = U7 Tpd + U5 Tpd + U6 Tpd A2Y A to Y Tpd 16 ns = 1 + 9 + 6 = 16 ns Ck2Y Clock to Y tpd 22 nsMax Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin) = 1/ Max (16, 22, 16) Negative hold times are typically specified as 0 ns. = 45.5 Mhz BR 1/99 19 BR 1/99 20 How do we improve timings? New TimingsRegister all Inputs, Outputs! 1 ns U8, DFF U5 U6 A Y Max Register to Register Delay U2 Tc2q + U5 Tpd + U9 Tsu = 5 + 9 + 3 = 17 ns. U7 7 ns 6 ns U1 U2 9 ns D A setup time = Tsu + A2D Tpd max - Clk Tpd min D Q = Tsu + (Tpd U7) - Tpd U8 Q U4 U9, DFF = 3 + (1) - 2 = 2 ns C C DFFs : U3 8 ns A hold time = Thd + Clk Tpd max - A2D Tpd min CK U8 Tsu = 3 ns = Thd + Tpd U8 - (Tpd U7) Thd = 4 ns = 4 + 2 - ( 1) = 5 ns 2 ns Tc2q = 5 ns BR 1/99 21 BR 1/99 22 New DataSheet How does a PLL/DLL help? • A Phased Locked Loop or Delay Locked Loop Parameter Description Min Max Units circuit is used to align the external clock edge at the Tclk Clock Period 17 ns Fclk Clock Frequency 58.8 Mhz pin with the internal clock edges at the DFF clk Atsu A setup time 2 ns pins Athd A hold time 5 ns – Some clock skew due to clock routing network from PLL will still be present, but input buffer delay Ck2Y Clock to Y tpd 13 ns eliminated. • This means that we can drop out the Clk Tpd term Most designs have all inputs, outputs registered. from the equations • How does this change things? BR 1/99 23 BR 1/99 24 4
  5. 5. Without PLL With PLL Buffer Delay Buffer Delay eliminated ExtCK ExtCK IntCK IntCK D D D D Q Q Q Q C C P C C ExtCK ExtCK L IntCK L IntCK IO Buffer Delay IO Buffer Delay BR 1/99 25 BR 1/99 26 New Timings (PLL, Inputs/Outputs Reg) New Timings (PLL, Inputs/Outputs Reg)Max Register to Register Delay Clock to Out = U8 Tpd + U9 Tc2q + U6 Tpd U2 Tc2q + U5 Tpd + U9 Tsu = 5 + 9 + 3 = 17 ns. = 0 (due to PLL) + 5 + 6 = 11 ns A setup time = Tsu + A2D Tpd max - Clk Tpd min = Tsu + (Tpd U7) - 0 (due to PLL) NO pin to Pin combinational delay! All inputs/outputs = 3 + (1) - 0 = 4 ns registered! Max Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin) = 1/ Max (17, 11, 0) A hold time = Thd + Clk Tpd max - A2D Tpd min = 58.8 Mhz = Thd + 0 (due to PLL) - (Tpd U7) = 4 + 0 - ( 1) = 3 ns BR 1/99 27 BR 1/99 28 New DataSheet (PLL, Inputs/Outputs Reg) Chip to Chip Timing Calculation Parameter Description Min Max Units Tclk Clock Period 17 ns Fclk Clock Frequency 58.8 Mhz Atsu A setup time 4 ns Inputs Athd A hold time 3 ns ASIC #1 ASIC #2 Ck2Y Clock to Y tpd 11 ns CLK Clock to Output improved; important in multiple chip designs. External Setup/Hold times closer to setup/hold Need to know external setup/hold times all inputs, clk to out times of internal DFFs. of all outputs, all pin to pin combinational delays. ASIC = Application Specific Integrated Circuit BR 1/99 29 BR 1/99 30 5
  6. 6. Max Register to Register Delay Other Factors that effect Timing 2 ASIC SystemAssume no pin to pin combinational delays and that inputs/outputs • Voltage: the higher the voltage, the faster thatof both ASICs are registered. gates switch • Temperature: the lower the temperature, the fasterFor any outputs from ASIC #1 which are Inputs to ASIC #2 find that gates switchmaximum of ASIC #1 Clk to out + ASIC#2 Setup time. • Process Technology (transistor gate width). The shorter the transistor gate length, the faster the transistor will switch (I.e, 0.5u process versusFor any outputs from ASIC #2 which are Inputs to ASIC #1 findmaximum of ASIC #2 Clk to out + ASIC#1 Setup time. 0.35u process).The maximum of these two times will be the minimum clock • In a given process run, may get fast N transistors,period. fast P transistors, slow N transistors, slow P transitors BR 1/99 31 BR 1/99 32 Speed Grades Device Characterization • Do timing analysis on ASICs at four extreme • Databooks often list different speed grades for a corners to make sure they meet timing specs under part at the same temperature all conditions • Simply test parts that come off the fabrication line • Fastest Case: Fast N transistors, Fast P transistors, and see how fast they are High Vdd, Low temperature – Divide the parts into different speed bins – For three speed grades, a design goal might be to have • Slowest Case: Slow N transistors, slow P 15% of your parts fall in the upper bin, 50% in the transistors, low Vdd, high temperature middle bin, and 25% in the lower bin. • Other two corners can vary but two possible – As the process matures, more and more fabricated parts corners are: will move into the upper speed bin, at which point you – Fast N, Slow P, Typical Temperature make a new upper speed bin. – Slow N, Fast P, Typical Temperature – Obviously, faster parts cost more (and are more profitable) BR 1/99 33 BR 1/99 34 Static Path Analysis Static Timing Analysis Reports • After your gate netlist has been mapped to the • The static timing analyzer will report the following FPGA, a timing analysis tool will analyze the paths times in the design and compute the timings we have – Register to Register delays discussed – Setup times of all external synchronous inputs • The timing analyzer takes into account the routing – Clock to Output delays delays in the physical routing and the speed grade – Pin to Pin combinational delays of the part you have mapped to. • The clock to output delay is usually just reported as – Because routing can sometimes change somewhat simply another pin-to-pin combinational delay drastically for even small changes, often try run multiple • Timing analysis reports are often pessimistic since device mappings to try to get a ‘good route’. they use worst case conditions BR 1/99 35 BR 1/99 36 6
  7. 7. Timing Simulation• The timings extracted by the Timing analysis tool (routing delays, gate delays for a particular speed grade, etc) are used in the simulation• It may be tempting to simply ignore the delays reported by the timing analyzer, and simply simulate the design ‘at speed’ to see if it works. – If the design simulates correctly, only means that it works for the particular test vectors that you used! – Different test vectors exercise different delay paths - you must use test vectors that exercise the LONGEST paths BR 1/99 37 7

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