Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our User Agreement and Privacy Policy.

Slideshare uses cookies to improve functionality and performance, and to provide you with relevant advertising. If you continue browsing the site, you agree to the use of cookies on this website. See our Privacy Policy and User Agreement for details.

Like this presentation? Why not share!

- Vedic Mathematics ppt by Krishna Kumawat 98975 views
- Vedic maths .PPT by jaisreenivasan 27190 views
- Vedic maths by Saransh Sharma 11266 views
- What is Vedic Maths? by Gaurav Tekriwal 16669 views
- Vedic math by Career_Clicks 9926 views
- Genius Vedic Maths Tutorials or L... by Raji Reddy Katukoori 14314 views

7,811 views

7,365 views

7,365 views

Published on

This ppt allows to handle different methods to deal with asic multiplier

Published in:
Technology

No Downloads

Total views

7,811

On SlideShare

0

From Embeds

0

Number of Embeds

6

Shares

0

Downloads

397

Comments

0

Likes

7

No embeds

No notes for slide

- 1. Presented by.. S.Noor Mohammad
- 2. VedicMathematics
- 3. The delay associated with the array multiplier is the Array time taken by the signals to propagate through theMultiplier gates that form the multiplication array. Large booth arrays are required for high speed multiplication and exponential operations which in turn require large partial sum and partial carry Booth registers.Multiplier Multiplication of two n-bit operands using a radix-4 booth recording multiplier requires approximately n / (2m) clock cycles to generate the least significant half of the final product, where m is the number of Booth recorder adder stages. Thus, a large propagation delay is associated with this case.
- 4. What is Vedic Mathematics..? The word „Vedic‟ is derived from the word „veda‟ which means the store-house of all knowledge. Jagadguru Shankaracharya Bharati Krishna Teerthaji Maharaja (1884-1960) Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras (Formulae). It covers explanation of several modern mathematical terms including arithmetic, geometry (plane, co- ordinate), trigonometry, quadratic equations, factorization and even calculus.
- 5. 16 Suthras(Formules) in Vedic Mathematics 1) (Anurupye) Shunyamanyat 2) Chalana-Kalanabyham 3) Ekadhikina Purvena 4) Ekanyunena Purvena 5) Gunakasamuchyah 16) Yaavadunam 6) Gunitasamuchyah15) Vyashtisamanstih 7)Nikhilam Navatashcaramam14) Urdhva-tiryakbhyam Dashatah13) Sopaantyadvayamantyam 8) Paraavartya Yojayet12) Shunyam Saamyasamuccaye 9) Puranapuranabyham 11) Shesanyankena Charamena 10) Sankalana- vyavakalanabhyam
- 6. Conventional method for 4-bit multiplication.3256*7384 3256 *7384 13024 Memory usage is high for each stage 26048+ and causes delay in 9768++ execution 22792+++ 24042304
- 7. How to reduce memory usage capability and propogation delay for acomplex multiplication. 3256 Here it is *7384 24042304 Reduces Complexity levels Decrese memory usage capacity Less Propagation delay HOW.. ….?
- 8. 1. CP X0 = X0 * Y0 = A Y02. CP X1 X0 = X1 * Y0+X0 * Y1 = B Y1 Y03. CP X2 X1 X0 = X2 * Y0 +X0 * Y2 +X1 * Y1 = C Y2 Y1 Y04. CP X3 X2 X1 X0 = X3 * Y0 +X0 * Y3+X2 * Y1 +X1 *Y2 = D Y3 Y2 Y1 Y05. CP X3 X2 X1 = X3 * Y1+X1 * Y3+X2 * Y2 = E Y3 Y2 Y16. CP X3 X2 = X3 * Y2+X2 * Y3 = F Y3 Y27 CP X3 = X3 * Y3 = G Y3
- 9. Hardware architecture of the Urdhva tiryakbhyammultiplier
- 10. Where it can be used Basic Applications: Vedic Mathematics is a branch of Mathematics which teaches pattern-observation and faster calculations. Vedic Mathematics covers Arithmatics Decimal operations in all decimal work, Ratios, Proportions, Trigonometry, Percentages, Averages, Interest, Annuities, Discount, the Centre of Gravity of Hemispheres, Transformation of Equations, Dynamics, Statistics, Hydro Statistics, Pneumatics, Applied Mechanics, Solid Geometry, Plane Spherical Trigonometry, Astronomy, etc.ASCI Application: The propagation delay of the resulting(16, 16)x(16, 16) complex multiplier is only 4ns andconsume 6.5 mW power. We achieved almost 25%improvement in speed from earlier reported complexmultipliers, e.g. parallel adder and DA based architectures.

No public clipboards found for this slide

×
### Save the most important slides with Clipping

Clipping is a handy way to collect and organize the most important slides from a presentation. You can keep your great finds in clipboards organized around topics.

Be the first to comment