ISA DMA & Bus Masters By Nishant H. Shah Roll No : 0412096 Batch : B4

What is DMA ? ISA DMA Signals Modes of Dma Tranfers Dmac Priority Logic Dmac Adressing capabilty ISA Bus Master

What is DMA ?

ISA DMA Signals

Modes of Dma Tranfers

Dmac Priority Logic

Dmac Adressing capabilty

ISA Bus Master

ISA Bus Master All The Channels of DMA is Programmed for Cascaded Mode Bus Master is Attached To Master DMAC

All The Channels of DMA is Programmed for Cascaded Mode

Bus Master is Attached To Master DMAC

ISA DMA Signal Lines DRQ [3:0] - DMA Request DRQ [7 :0] - DMA Request DAK# [3:0] - DMA Acknowledge DAK# [7:5] - DMA Acknowledge TC - Transfer Complete Master16# - For 16 bit Bus Master AEN - Address Enable

DRQ [3:0] - DMA Request

DRQ [7 :0] - DMA Request

DAK# [3:0] - DMA Acknowledge

DAK# [7:5] - DMA Acknowledge

TC - Transfer Complete

Master16# - For 16 bit Bus Master

AEN - Address Enable

Associated Signals with ISA DMA SA [19:0] - System Address Bus La [ 23:7] - Latchable Address Bus SBHE# - System Bus High Enable

SA [19:0] - System Address Bus

La [ 23:7] - Latchable Address Bus

SBHE# - System Bus High Enable

DMA Channel Assignments In ISA Channel 0 : Earlier was used for DRAM Refresh on 8bit ISA .Now its on 16 bit ISA used for 16 bit Bus Master Channel 1: For External Device Channel 2: Floppy And Hard drive Controller

Channel 0 :

Earlier was used for DRAM Refresh on 8bit ISA .Now its on 16 bit ISA used for 16 bit Bus Master

Channel 1:

For External Device

Channel 2:

Floppy And Hard drive Controller

DMA Channel Assignments In ISA Channel 3 : Hard disk controller Channel 5 : Hard disk controller Channel 6 & 7: External Device

Channel 3 :

Hard disk controller

Channel 5 :

Hard disk controller

Channel 6 & 7:

External Device

Modes of DMA Transfers Single Transfer Mode Block Transfer Mode Demand Transfer Mode Cascaded Mode (used in 16 bit ISA Bus)

Single Transfer Mode

Block Transfer Mode

Demand Transfer Mode

Cascaded Mode (used in 16 bit ISA Bus)

DMA Priority Logic Fixed Priority Rotating Priority

Fixed Priority

Rotating Priority

Addressing Capability of DMA Address Range of 16 MB 000000H-FFFFFFH This Can Achieved with 16bit Memory Address Register associated with DMA & 8bit external DMA Page Register

Address Range of 16 MB

000000H-FFFFFFH

This Can Achieved with 16bit Memory Address Register associated with DMA & 8bit external DMA Page Register

Addressing Capability of DMA Addressing for Slave DMA Addressing Master DMA Addressing The ISA Memory DMAC resides on X-bus & Addresses Bus on ISA Bus

Addressing for Slave DMA

Addressing Master DMA

Addressing The ISA Memory

DMAC resides on X-bus & Addresses Bus on ISA Bus

When ISA MASTER requests for the Bus following Sequence Takes place Requesting device asserts DRQ line Master DMA 8237 asserts Hold request to the Microprocessor In response The Microprocessor asserts HLDA

When ISA MASTER requests for the Bus following Sequence Takes place

Requesting device asserts DRQ line

Master DMA 8237 asserts Hold request to the Microprocessor

In response The Microprocessor asserts HLDA

Master DMAC asserts DAK line associated with respective DRQ line of Bus Master Now ISA Bus Master card should Asserts MASTER16# This causes AEN signal on ISA bus to be deasserted.

Master DMAC asserts DAK line associated with respective DRQ line of Bus Master

Now ISA Bus Master card should Asserts MASTER16#

This causes AEN signal on ISA bus to be deasserted.

When ISA Bus Master has completed it uses of the bus it desasserts DRQ line And DMAC deasserts DAK and HOLD And this Deasserts HLDA line On Micro processor

When ISA Bus Master has completed it uses of the bus it desasserts DRQ line

And DMAC deasserts DAK and HOLD

And this Deasserts HLDA line On Micro processor

Thank You Nishant H. Shah BE ETRX BATCH – B4 Roll No: 0412096