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Curriculum Vitae
Curriculum Vitae
Curriculum Vitae
Curriculum Vitae
Curriculum Vitae
Curriculum Vitae
Curriculum Vitae
Curriculum Vitae
Curriculum Vitae
Curriculum Vitae
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Curriculum Vitae

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  • 1. CURRICULUM VITÆ Dr. Andrew Paul NisbetSchool of Computing, Mathematics & Oce Phone: (+44) 161-246-1566Digital Technology, Mobile Phone: Not provided.Manchester Metropolitan University, Work Email: A.Nisbet@mmu.ac.ukChester Street, Home Email: Not provided.Manchester, M1 5GD, http://sites.google.com/site/drandynisbet/UK.Employment 10/2004current: Senior Lecturer in Computer Science, Manchester Metropolitan Univer- sity. Ph.D student Adeel Hashmi: Hardware Acceleration of Snort Network Intrusion Detec- tion using FPGAs, supervised to completion in January 2011. Currently supervising 2 Ph.D students. Member of Novel Computation Group undertaking research on compilers, perfor- mance optimisation for multicore, GPUs, Xilinx Virtex-4 FPGAs, and applications concerning biologically inspired algorithms and wireless sensor networks. 10/199910/2004: Lecturer in Computer Science, Trinity College Dublin, Dublin, D2, Ireland. Principal investigator/scientist for 3 national and an EU (Marie-Curie) project, collaborator on 2 further nationally funded projects. Research in compilation, performance optimisation, Xilinx Virtex2/Spartan3 FPGAs and virtual environments. Joint management of a team of 8 personnel including Ph.D. students, and postdoctoral researchers. 02/199309/1999: Research Associate, Centre for Novel Computing, Department of Com- puter Science, Manchester University, Oxford Road, Manchester, M13 9PL, UK. Involved in a variety of EU and EPSRC projects concerning high performance parallel computing, computer architecture, operating/run-time systems, compilers and parallel application development for a semantic network classier and a temporal logic theorem prover. Delivered short fat inten- sive 2-5 day C/C++ and OOAD courses as a consultant to industry. Expertise in C/C++ and some SPARC assembler (rewrote a network driver for a distributed parallel computer architecture). 07/198809/1989: Systems Engineer, Siemens (UK) PLC, Energy and Automation Division, Varey Road, Congleton, UK. Application of S5 Programmable Logic Controllers for the au- tomation of plant and machinery. Seconded to Erlangen, Germany January-August 1989, German language training course (January-March 1989).Education19891993 (conferred 1994) Ph.D., Dept. of Electrical and Electronic Engineering, University of Manchester, Dover Street, Manchester. My Ph.D. research (An Object Oriented Environment
  • 2. Dr. Andrew Paul Nisbet 2 for the Simulation of Multiprocessor DSP Systems), produced software tools for the design and implementation of real-time digital signal processing systems. An ecient method for the evaluation of graphically specied algorithms was produced. Algorithms were automatically scheduled and partitioned for minimum execution time on user-specied multiprocessor hard- ware. This was accomplished using a multiprocessor simulator in conjunction with simulated annealing or genetic algorithm optimisation techniques. All software was implemented under the object-oriented paradigm using C++ on Sun-4 workstations.19851988 University of Manchester, Oxford Road, Manchester, M13 9PL. Grade II(i) B.Sc. joint honours degree in Physics and Electronic Engineering. This gave a solid grounding in the theory and practice of Physics and Electronic Engineering. Final year options in Numerical Methods and Computing, Digital Speech and Image Processing, and Communications. Final year project: (Post-processing Software for the Hilo-3 Digital Logic Simulator) transformed textual simulation output into a graphical display with pan, zoom and HPGL plotting func- tionality.ResearchResearch InterestsThe main drive of my research work is to develop tools and techniques to aid the exploitation ofparallel/novel computing technology. My work has mainly addressed the development of parallelis-ing compiler tools, run-time systems, and hardware compilation techniques for embedded systemsand applications. My interests include the development of skills/expertise in areas related to com-pilation, computer architecture and application or system level optimisation for high performanceand/or low power.Compilation I initiated, devised and performed all implementation work on an EPSRC project asa natural extension of my PhD research; GAPS GR/K82291 (April 96 - April 99), Genetic AlgorithmOptimised Compilation of FORTRAN for Distributed Memory Architectures. GAPS developed anovel iterative feedback based approach to compilation where a genetic algorithm was used tooptimise the applied loop transformations. The Omega projects petit prototype auto-parallelisingsource-to-source compiler tools provided the base software infrastructure for this work.Compiler research under the EC ESPRIT OCEANS 22729 project retargeted GAPS to optimizecode for embedded applications running on VLIW or superscalar architectures. The main back-endtarget for this work was the Phillips TriMedia-1 VLIW processor. The continuation of this workat Trinity College has resulted in the development and funding of an Enterprise Ireland ResearchInnovation Fund grant IDEAS: Iterative Design Tools for Embedded FPGA Systems.Optimisation for multicore:GPUs:FPGAs The main focus of my current research is theapplication of parallelising compiler and parallel applications research to optimisation. This requiressignicant knowledge of compiler theory, program performance optimisation, computer architectureand digital logic design. My research seeks to develop tangible assets such as software prototypecompilers, optimised applications, as well as the traditional research outputs of learned publicationsand research theses. The signicance of my research is that it will make the development of optimisedembedded and/or high performance systems easier and faster. Further, that it will reduce the levelof expertise required to develop such systems. The base software infrastructure for this work isLLVM which is used in my teaching for compiler related (Software Architecture) courses.
  • 3. Dr. Andrew Paul Nisbet 3Funded Research Grants Host academic: HiPEAC Collaboration Grant 2010 subsistence funding for Jose Maria Cecilia (University of Murcia, Spain) to collaborate for 3 months and work on biologically inspired computiation using GPUs in the Novel Computation Group at MMU. Co-investigator: ¿27000 2010-2011 Engineering and Physical Sciences Research Council from Bridging the Gaps: Nano-Info-Bio (Principal Investigator Dr M. Amos, MMU), salary costs of a research assistant to investigate novel real-time GPU implementations of algorithms for tracking skeletal muscle contraction in ultrasound video sequences. Principle Investigator: e2000 HiPEAC travel and networking 2009: Value Based Optimisa- tion: aims to perform preliminary investigations into how value based optimisation can be used to optimise sparse-matrix based applications. Principle Investigator: e4000 HiPEAC travel and networking 2008: Value Proling Driven Optimisation for Embedded Processor Architectures and Applications, using a combination of Pin, LLVM and Simics. Principle Investigator: e113970 IDEAS: Iterative Design Tools for Embedded FPGA Sys- tems, Enteprise Ireland Research Innovation Fund, 2yr project, IDEAS/IF2002/035 (2002-2004). Principle Investigator: e143928 Hardware Acceleration of High Performance Computing Applications, Enterprise Ireland, Basic Research Grant, 3yr project, SC/02/288 (2002-2005) Principle Investigator: e214487 Virtually Healthy: Creating a compelling on-line environ- ment to help young people access positive mental health information, HEA/Media Lab Europe. 3 year project, (2002-2005) Principle Investigator: e123000 Marie-Curie Intra-European Fellowship for Milan Tichy, LFAPDIFI 502085, Digital Filtering using Fast Ane Projection and Logarithmic Arithmetic, 2yr project, EU FP6, Trinity College, Dublin (2004-2006). Co-investigator: e350000 FIAMMA: Finite Iterative Algorithm Matrix Mathematics Accel- erator TD/04/205, Trinity College, Dublin, 2yr project, Enterprise Ireland, Commercialisation Fund (2004-2006). Involvement in research limited due to changing post to MMU. Co-investigator: e90000 approx. Worlds Fastest Java Interpreter, Trinity College, Dublin, Enterprise Ireland, Research Innovation Fund (2002-2004).Professional ActivitiesMemberships Member of HiPEAC: European Network of Excellence on High Performance and Embedded Architecture and Compilation http://www.hipeac.net. MBCS: Member of the British Computer Society.Awards Patents The initialPersonal Investigator 3D virtual environment prototype software developed under my Virtually Healthy Project at Trinity College Dublin and Media Lab Europe, won an O2 Digital Media Innovation Award (Consumer category) in 2004. http://medialabeurope.org/news/announcement.php?id=5
  • 4. Dr. Andrew Paul Nisbet 4 2004, Trinity College Dublin, Ireland. Honorary M.A. Ozer, E., Nisbet, A.P., Gregg, D., Trinity College Dublin Preliminary Irish Patent TRI213: Filed November 2004 - Expired November 2005, An Estimation Method in Customising Data Bus Size for Application-Specic Processors, funded with support from Enterprise Ireland IF/2002/035/IDEAS.Examining M.Phil (external examiner): Iain Walsh, A Study of Contention Management for Transactional Memory, Manchester University, 2010. M.Phil (external examiner): O.M. Esoul, VMX-Rootkit: Implementing Malware With Hardware Virtual Machine Extensions, Salford University, 2008. M.Phil. (external examiner): Dervla OKeefe, A Simple HDL, Trinity College Dublin 2007. Ph.D. (external examiner): Faycaal Bensaali, Accelerating Matrix Product on Recongurable Hardware For Image Processing Applications, Queens University of Belfast, 2005. Ph.D. (internal examiner): Philip Mackenzie, Software and Recongurability for Software Radio Systems, Trinity College Dublin, Ireland, 2004.Supervisions 3 M.Sc. project supervisions. Fayez Abdulrahman Alfayez, (due to start in July 2011), Optimisation of Multichannel Medium Access Control Protocols for Wireless Mesh Networks (joint with Dr Mohammad Hammoudeh, Dr. Zuhair Bandar, Dr Liangxiu Han). Matthew Crossley: Bioinspired Computation using Multicore GPUs (started September 2010, joint with Dr. Martyn Amos). Tariq Alsbooey: An Integrated Framework for Information Extraction in Wireless Sensor Net- works (started October 2010, joint with Dr Mohammad Hammoudeh. Dr Zuhair Bandar) Dr. Adeel Hashmi, Ph.D. (completed January 2011). Dr. Owen Callanan (Trinity College Dublin 2002-04), supervised to completion by Dr. David Gregg in 2006. Dr. David Coyle (Trinity College Dublin 2002-04), supervised to completion by Dr. Gavin Doherty in 2008. Dr. Mark Matthews (Trinity College Dublin 2002-04), supervised to completioon by Dr. Gavin Doherty in 2009.Conference Committee Memberships IMVIP 2005: Irish Machine Vision Image Processing Conference, Northern Ireland, 2005 HipHac08: 1st International Workshop on New Frontiers in High-performance and Hardware- aware Computing, Italy, 2008 HipHac11: 2nd International Workshop on New Frontiers in High-Performance and Hardware- aware Computing, USA, 2011. ITA11: 4th Intl. Conference on Internet Technologies Applications, Wales, 2011.
  • 5. Dr. Andrew Paul Nisbet 5 UCHPC2011: 4th Workshop on UnConventional High Performance Computing 2001, held in conjunction with Euro-Par, Bordeaux, France 2011.General SkillsLLVM : supervised undergraduate student projects using LLVM. Incorporating a simple-C front- end into laboratory and lecture material for compiler courses. Developed a back-end for a soft- core FPGA processor. Currently evaluating a high-level synthesis LLVM backend developed at Haifa University and developing an LLVM backend to ILOC (similar to MIPS) for teaching of compilation concepts.Virtutech Simics previously used in M.Sc. level courses to demonstrate virtualisation and system level simulation.Intel Pin dynamic binary instrumentation tool, used in undergraduate and M.Sc. level courses to obtain memory access traces, value load/store information.Computer Language Exposure: familiar with Linux and Windows operating systems, and have used C++, C, Java, Python, Pascal, Z80, 6809 and SPARC assembler. Hardware compilation has used Celoxicas DK toolds for HandelC, Synopsys Design Compiler/SystemC Compiler, Xilinx ISE, Mentor Graphics Modelsim, Verilog and Balsa (asynchronous logic simulation/synthesis system from University of Manchester).Self Development: Attended a one week residential SERC graduate school course (February 1991). Involved group work, decision making, and presentations. I have developed, lectured and demonstrated intensive C, C++ and Object Oriented Design courses as a consultant to industry whilst employed as a Research Associate at Manchester University. Attended Xilinx Training modules on Fundamentals of FPGA Design and Designing for Performance. At- tended ACID-WG Summer School on Asynchronous Logic Design in Grenoble, July 2002. Attended 3 seminars on Intel compiler/performance optimisation tools June/July 2011.German language: Intensive language training and secondment to Siemens in Germany has pro- vided a basic knowledge of German.TeachingManchester Metropolitan University3 year undergraduate and one year postgraduate degree courses, currently taught units have coursecodes and enrolled student numbers for session 2010-2011. Bold font indicates unit leader. 63SN5301: Computer Networks and Operating Systems, 100 students, 2nd year courses 24 weeks, 2 lectures, 1 hour lab sessions. Innovation: introduced virtualisation into teaching via kvm, and dynamic binary instrumentation using Pin. Network Management Security, 3rd year unit, 24 weeks, 1 lecture, 1 laboratory session. 63SN6302: Information Network Security, 44 students, 3rd year unit dealing with crypto- graphic applications and network security. Python programming is used to introduce simple cryptographic examples.
  • 6. Dr. Andrew Paul Nisbet 6 63SN6301 Software Architectures, 22 students, 3rd year unit, 24 weeks, 1 lecture, 1 labo- ratory session. Research led unit in compilation and performance optimisation. Also delivered in a modied form as an advanced M.Sc. 63SW7301 unit with 10 students over 13 weeks with 4 contact hours. Innovations: introduced LLVM, ANTLR and Pin material. Currently introducing Intel compiler and optimisation tools for academic session 2011-2012. 63CP6302 Software Engineering Group Project, 20 students, 24 weeks. Responsible for collating group project list, organising project selection, group formation, vivas and managing problematic group dynamics as they arise. 63MM7301 Introduction to Multimedia the Internet, MS.c. conversion unit, 25 students, 4 hours per week over 13 weeks. JavaScript and material on Mozilla refox plugins.Trinity College Dublin4 year undergraduate and one year postgraduate degree courses. Concurrent Programming and Operating Systems. 3rd year course, 24 weeks, 2 lectures + 2 hours programming. Hardware Compilation. Final year research led unit in compilation, performance optimisation and high-level synthesis. 24 weeks, 2 lectures + 2 hours programming. Client-Side Programming. Conversion M.S.c unit for arts graduates covering basic JavaScript, HTML and multimedia. 12 weeks, 4 hours.PublicationsRefereed Journals 1. Ozer, E., Nisbet, A.P., Gregg, D., A Stochastic Bit-width Estimation Technique for Compact and Low-power Custom Processors, ACM Transactions on Embedded Computing Systems (TECS), Volume 7 Issue 3, April 2008, 2. Gregg, D., Beatty, A., Casey, K., Davis, .B, Nisbet, A., The Case for Virtual Register Machines, Science of Computer Programming, Volume 57, Issue 3, September 2005, Pages 319-338 3. Ozer, E., Nisbet, A.P., Gregg, D. Callanan, O., Estimating Data Bus Size for Custom Processors in Embedded Systems, Springer Design Automation for Embedded Systems Journal, Volume 10(1), pp. 5-26, Springer, March 2005. 4. Coyle, D., Matthews, M., Sharry, J., Nisbet, A., Doherty, G., Personal Investigator: A Therapeutic 3D Game for Adolescent Psychotherapy. International Journal of Interactive Technology and Smart Education, Volume 2, issue 2, pp.73-88, 2005. 5. Nisbet, A.P. S. Dobson, S., A Systems Architecture for Sensor Networks based on Hard- ware/Software Co-design, The 1st IFIP TC6 WG6.6 Workshop on Autonomic Communication (WAC 2004) Autonomic Communication Principles 18-19 October 2004 in Berlin, Germany, Lecture Notes in Computer Science, Volume 3457, pages 115-126.
  • 7. Dr. Andrew Paul Nisbet 7 6. Ozer, E., Nisbet, A.P., Gregg, D., Automatic Customization of Embedded Applications for Enhanced Performance and Reduced Power using Optimizing Compiler Techniques, Euro- Par04, Pisa, Italy, Aug., Lecture Notes in Computer Science, Volume 3149, ISBN: 3-540- 22924-8, ISSN: 0302-9743, pages 318-327, 2004. 7. Ozer, E., Nisbet, A.P., D. Gregg, D., Stochastic Bit-width Approximation using Extreme Value Theory for Customizable Processors, in 13th International Conference on Compiler Construction (CC), LNCS 2985, Barcelona, Spain, Mar. 2004, ISBN: 3-540-21297-3 ,ISSN: 0302-9743 , Chapter: pp. 250 - 264. 8. Casey, K., Gregg, D., Ertl, M.A., Nisbet, A., Towards Superinstructions for Java In- terpreters Lecture Notes in Computer Science, ISSN: 0302-9743, Volume 2826 / 2003, Title: Software and Compilers for Embedded Systems: 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings ISBN: 3-540-20145-9, pages 329-343. 9. Barreteau, M., Bodin, F., Chamskiz, Z. Charles, H., Eisenbeis, C., Gurd, J., Hoogerbrug- ger. J., Hu, P., Jalby, W., Kisuki, T., Knijnenburg, P.M.W, van der Mark, P., Nisbet, A.P., OBoyle, M.F.P., Rohou, E., Seznec, A., Stoehr, E.A., Treers, M. Wijsho, H.A.G., OCEANS: Optimising Compilers for Embedded Applications, Euro-Par99, 5th European Con- ference on Parallel Processing, Toulouse, France, Lecture Notes in Computer Science, Volume 1685, pages 1171 - 1175, (1999). 10. OBoyle, M., Ford R.W., Nisbet, A.P., Compiler Reduction of Invalidation Trac in Virtual Shared Memory Systems, Proceedings of Euro-Par 96, Lyon, France, August, Lecture Notes in Computer Science, Volume 1123, pages 432-440.(1996) 11. Nisbet, A.P. Ford, R.W., Spinning-on-Coherency: A New VSM Optimisation for Write- invalidate, Proceedings of High Performance Computing and Networking Europe, Brussels, Belgium, April, Lecture Notes in Computer Science , Volume 1067, pages 792-797. (1996) 12. Ford, R.W., Nisbet, A.P., Bull, J.M., User-level VSM Optimisation and its Application, Proceedings of PARA95 Workshop on Applied Parallel Computing in Physics, Chemistry and Engineering Science, Lyngby, Denmark, August, Lecture Notes in Computer Science, Volume 1041, pages 223232. (1995)Refereed Conferences 13. Alsboui, T.A.A, Hammoudeh, M., Bandar, Z., Nisbet, A,, An Overview and Classication of Approaches to Information Extraction in Wireless Sensor Networks, SENSORCOMM2011, Fifth International Conference on Sensor Technologies and Applications, August, 2011 ( in press, accepted for publication). Nisbet, A., Amos, M., Parallelization Strategies for 14. Cecilia, J.M, Garcia, J.M., Ujaldon, M., Ant Colony Optimisation on GPUs, 14th International workshop on Nature Inspired Comput- ing (NIDISC 2011 May16th-20th), held in conjunction with 25th IEEE/ACM Intl. Parallel and Distributed Computing Symposium (IPDPS 2011). 15. Hashmi, A, Nisbet, A., Hardware/Software Co-design Platform for Network Intrusion Detection System (NIDS), Proceedings of ITA 09, 3rd International Conference on Internet Technologies and Applications, September 2009, Wrexham, UK.
  • 8. Dr. Andrew Paul Nisbet 8 16. Callanan, O., Gregg, D., Nisbet, A., Peardon, M. High Performance Scientic Computing using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD FPL 2006 16th International Conference on Field Programmable Logic and Applications, School of Engineering - Universidad Autonoma de Madrid, SPAIN Madrid, August 28-30. 17. Callanan, O., Nisbet, A., Ozer, E., Sexton, J. Gregg, D., FPGA Implementation of a Lattice Quantum Chromodynamics Algorithm Using Logarithmic Arithmetic, in 12th Recon- gurable Architectures Workshop (RAW 2005), in 19th International Parallel and Distributed Processing Symposium CD-ROM / Abstracts Proceedings, IEEE Computer Society, Denver, California, May 2005. Nisbet, A., Doherty, G. (2004), Personal Investigator: 18. Matthews, M., Coyle, D., Sharry, J., Computer Mediated Adolescent Psychotherapy using an interactive 3D game. Proceedings of NILE2004 Narrative and Interactive Learning Environments, pp. 75-81, 10-13 August 2004, Edinburgh, Scotland. 19. Beatty, A., Casey, K., Gregg, D. Nisbet, A.P., An optimized Java interpreter for connected devices and embedded systems, in Proceedings of the 18th ACM Symposium on Applied Com- puting (SAC 03), pp. 692-697, Melbourne, Florida, March 2003, Symposium on Applied Computing archive Proceedings of the 2003 ACM symposium on Applied computing, Pages: 692 - 697 , ISBN:1-58113-624-2 20. Eadie, D., Shevlin, F. Nisbet, A.P., Geometric Correction of Image Distortion using FPGAs, Proceedings of SPIE Conference on Optical Metrology, Imaging and Machine Vision, September 2002, Galway, Ireland, Volume 4877, pg 28-37,ISBN 0-8194-4658-0. 21. OBoyle, M., Nisbet, A.P., Ford, R.W., A Compiler Algorithm to Reduce Invalidation La- Proceedings tency in Virtual Shared Memory Systems, (also appears as invited publication 35), of Parallel Architectures and Compilation Techniques, Boston USA, October, (1996). 22. Johnson, R., Shen. K., Fisher, M.D., Keane, J.A. Nisbet, A.P., An Abstract Machine for Prototyping Parallel Proof Mechanisms, Proceedings of Third Annual Workshop on Abstract Machine Models for Parallel and Distributed Computing, IOS Press, April 1996, pages 191- 202.(1996) 23. Mayes, K., Quick, S., Bridgland, J. Nisbet, A.P., Language- and Application-oriented Proceedings of the 6th ACM SIGOPS Euro- Resource Management for Parallel architectures. pean Workshop Matching Operating Systems to Application Needs, Dagstuhl Castle, Wadern, Germany, September, 172-177.(1994)Non-refereed Papers 24. Tichy, M.,Nisbet, A., Gregg, G., GSFAP adaptive ltering using log arithmetic for resource- constrained embedded systems, (poster) Proceedings of the International Symposium on Field programmable gate arrays, Monterey, California, USA, (poster), Pages: 236 - 236 Year of Publication: 2006 ISBN:1-59593-292-5. Nisbet, A., Implementation of an Image Segmentation 25. Bannister, R., Gregg, D., Wilson,S., Application using Logartihmic Arithmetic, Proceedings of the IEEE Intl. Midwest Symposium on Circuits and Systems, Ohio USA, August, (poster) 2005.
  • 9. Dr. Andrew Paul Nisbet 9 26. Ozer, E., Nisbet, A.P., Gregg, D., Fine-tuning Loop-level Parallelism for Enhancing Performance of DSP Applications on FPGAs, in 12th Annual IEEE Symposium on Field- Programmable Custom Computing Machines (FCCM04), Napa Valley, CA, USA, Apr. 2004, pages 273-274 (poster) ,ISBN 0-7695-2230-0 27. Ozer, E., Nisbet, A.P., D. Gregg , ILP versus Clock Rate: A Study of Performance Analysis for Embedded Applications on FPGAs, Technical Report, Department of Computer Science, Trinity College, Dublin, Ireland, May 2004. 28. Coyle, D., Sharry, J., Nisbet, A., Matthews, M. (2003). Virtual Perspectives: Developing a Therapeutic 3D Virtual Environment for Adolescents. Invited Publication in Eisteach: A Quarterly Journal of Counselling and Psychotherapy, 2(25), 27-31. 29. Ozer, E., Nisbet, A.P., D. Gregg, Classication of Compiler Optimizations for High Per- formance, Small Area and Low Power in FPGAs, Technical Report, Department of Computer Science, Trinity College, Dublin, Ireland, June 2003. 30. Nisbet A.P., Towards Retargettable Compilers Feedback Directed Compilation Using Ge- netic Algorithms, Proceedings of Compilers for Parallel Computers, Edinburgh, Scotland, June 2001, http://www.icsa.informatics.ed.ac.uk/cpc2001/Speakers/nisbet.html 31. Nisbet, A.P., Iterative Feedback Directed Parallelisation Using Genetic Algorithms, Work- shop on Prole and Feedback-Directed Compilation, in conjunction with PACT98: Interna- tional Conference on Parallel Architectures and Compilation Techniques (1998). 32. Nisbet, A.P., GAPS: Iterative Feedback Directed Parallelisation Using Genetic Algorithms, (poster), in Proceedings of Supercomputing 98,November, Orlando Florida, USA (1998). 33. Nisbet, A.P., GAPS: A Compiler Framework for Genetic Algorithm (GA) Optimised Paral- lelisation, (extended poster) Proceedings of High-Performance Computing and Networking Europe, Amsterdam, April, Lecture Notes in Computer Science, Volume 1401, pages 987-989. (1998) 34. Nisbet, A.P., GAPS: Genetic Algorithm Optimised Parallelisation, (invited publication), 7th Workshop on Compilers for Parallel Computers, pages 172-183, Linkoeping, Sweden. (1998) 35. Mayes, K.R., Bridgland, J., Quick, S., Nisbet, A., Network Performance in Arena, Pro- ceedings of High-Performance Computing and Networking Europe, Brussels, Belgium, April, Lecture Notes in Computer Science, Volume 1067, (poster), pages 1007-1008. (1996) 36. OBoyle, M., Nisbet, A.P., Ford, R.W. (1996), A Compiler Algorithm to Reduce In- validation Latency in Virtual Shared Memory Systems, (also appears in PACT96) (invited publication) 6th Workshop on Compilers for Parallel Computers, Aachen, Germany, Decem- ber, Volume 21, Konferenzen des Forschungszentrums Juelich (1996) 37. Riley, G.D., Bull, J.M., Nisbet, A.P., Parallelisation of a Semantic Network Classier, Proceedings of the 2nd European School of Computer Science Parallel Programming Environ- ments for High Performance Computing (ESPPE), IMAG-INRIA, France, Alpe dHuez, April, pages 209-212.(1996)
  • 10. Dr. Andrew Paul Nisbet 10 38. Nisbet, A.P. (1995), Static Task Scheduling and Partitioning for Shared Memory Multi- processors Using Stochastic Techniques, Proceedings of 5th IMACS-Symposium on Systems Analysis and Simulation, Berlin, Germany, June, Systems Analysis Modelling Simulation, Volumes 18-19, pages 463-466.(1995) 39. Mayes, K., Nisbet, A.P., (1993) Aspects of Multiprocessor and Multi-computer Schedul- ing, Centre for Novel Computing Technical Report CNC/1993/015, University of Manch- ester.(1993) 40. Nisbet, A.P., An Object Oriented Environment For The Simulation of Multiprocessor Digital Signal Processing (DSP) Systems, PhD thesis, Dept. Electronic Engineering, University of Manchester.(1993)Papers under Review 41. Cecilia, J.M. Garcia, J.M., Nisbet, A., Amos, M, Ujaldon, M.: Enhancing Data Parallelism for Ant Colony Optimisation on GPUs, JPDC-11-139, under review for the Journal of Parallel and Distributed computing, Elsevier.Papers in Preparation 42. Harding P., Costen, N., Nisbet, A., Darby, J., Loram, I.: A Real-time Biofeedback Applica- tion Using Ultrasound Imaging on the GPU, extended version of presentation at Using GPUs for Vision, One Day BMVA Symposium at the British Computer Society, May 18th 2011. 43. Andy Nisbet, Adeel Hashmi: Snort Network Intrusion Detection on an Embedded FPGA Platform.References supplied on request Last updated: June 28, 2011

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