Amvdd Data Converter Fundamentals

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Amvdd Data Converter Fundamentals

  1. 1. Unit I Data Converter Fundamentals Analog and Mixed Mode VLSI Design 06EC63 Session: Jan – June 2010
  2. 2. Terminology <ul><li>analog: continuously valued signal, such as temperature or speed, with infinite possible values in between. </li></ul><ul><li>Analog data (All values on the time and amplitude are allowed). </li></ul><ul><li>digital: discretely valued signal, such as integers, encoded in binary. Digital data (Only a few amplitude levels are allowed). </li></ul>
  3. 3. Introduction <ul><li>- Signals in real world; light, sound . </li></ul><ul><li>-When you scan a picture with a scanner what the scanner is doing?? (ADC) </li></ul><ul><li>It is taking the analog information provided by the picture (light) and converting into digital . </li></ul><ul><li>-When you record your voice on your computer. </li></ul>
  4. 4. Introduction cont'd <ul><li>- Since analog signals can assume any value, noise is interpreted as being part of the original signal. Digital system, on the other hand, can only understand two numbers, zero and one. Anything different from this is discarded. </li></ul><ul><li>- Here we need a translator from analog to digital. The devices which play this job are called analog to digital converter. </li></ul>
  5. 5. Analog-to-digital converter <ul><li>- An analog-to-digital converter (abbreviated ADC, A/D or A to D or A2D) is an electronic circuit that converts continuous signals to discrete digital numbers . </li></ul><ul><li>- The digital output may be using different coding schemes, such as binary and two's complement binary. However, some non-electronic or only partially electronic devices, such as shaft encoder, can also be considered as ADCs. </li></ul>
  6. 6. Analog-to-digital converters Embedded Systems Design: A Unified Hardware/Software Introduction, (c) 2000 Vahid/Givargis proportionality V max = 7.5V 0V 1111 1110 0000 0010 0100 0110 1000 1010 1100 0001 0011 0101 0111 1001 1011 1101 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V 6.0V 6.5V 7.0V analog to digital 4 3 2 1 t1 t2 t3 t4 0100 0110 0110 0101 time analog input (V) Digital output digital to analog 4 3 2 1 0100 1000 0110 0101 t1 t2 t3 t4 time analog output (V) Digital input
  7. 8. Example: <ul><li>You live in Moscow, Idaho, where the weather in the winter stays between 0 °F and 50 °F (Fig. 28.2a). </li></ul><ul><li>Suppose you had a thermometer that contained only two readings on it, hot and cold, and that you wanted to record the weather patterns and plot the results The two quantization levels can be correlated with the actual temperature as follows: </li></ul><ul><ul><li>If 0°F ≤ T ≤ 25°F Temperature is recorded as cold </li></ul></ul><ul><ul><li>If 25°F ≤ T ≤ 50°F Temperature is recorded as hot </li></ul></ul><ul><li>You take a measurement every day at noon and plot the results after one week </li></ul>
  8. 9. Example contd…
  9. 10. Note: <ul><li>The accuracy of the digitized signal is dependent on two things: </li></ul><ul><ul><li>the number of samples taken and </li></ul></ul><ul><ul><li>The resolution, or number of quantization levels of the converter. </li></ul></ul><ul><ul><li>In our example, we need to increase both the number of samples and the resolution of thermometer. </li></ul></ul>Example contd…
  10. 11. Example contd… <ul><li>We obtain a thermometer with 25 temperature readings and that we now take a reading eight times per day. </li></ul><ul><li>Each of the 25 quantization levels now </li></ul><ul><li>represents a 2 °F band of temperature </li></ul>
  11. 12. How many samples should one take in order to accurately represent the analog signal? <ul><li>Suppose a sudden rainstorm swept through Moscow and caused a sharp decrease in temperature before returning to normal. </li></ul><ul><li>If that storm had occurred between our sampling times, our experiment would not have shown the effects of the storm. If sampling time was too slow to catch the change in the weather. </li></ul><ul><li>If we had increased the number of samples, we would have recognized that something happened which caused the temperature to drop dramatically during that period. </li></ul>
  12. 13. Nyquist Criteria <ul><li>the sampling rate be at least two times the highest frequency contained in the analog signal. </li></ul><ul><li>In our example, we need to know how quickly the weather can change and then take samples twice as fast as that value. </li></ul><ul><li>The Nyquist Criterion can be described as </li></ul><ul><li>F sampling = 2 F MAX </li></ul>
  13. 14. How much resolution should we use to represent the analog signal accurately? <ul><li>In our weather example, </li></ul><ul><ul><li>if we were only interested in following general trends, then the 25 quantization levels would more than suffice. </li></ul></ul><ul><ul><li>However, if we were interested in keeping an accurate record of the temperature to within ±0.5 °F, we would need to double the resolution to 50 quantization levels so that each quantization level would correspond to each degree ±0.5 °F . </li></ul></ul><ul><li>There is no criterion for this specification. </li></ul><ul><li>Each application will have its own requirements. </li></ul>
  14. 15. Note: <ul><li>Sampling depends on the frequency of the signal. </li></ul><ul><li>Quantization depends on amplitude of the signal. </li></ul><ul><li>The rate of sampling and the no. of quantization levels do not have any relation with each other. </li></ul>
  15. 16. Sample and Hold Characteristics <ul><li>Behavior is analogous to that of a camera. </li></ul><ul><li>Function: To sample the analog signal and hold it until the ADC processes it. </li></ul><ul><li>Limits both speed and accuracy. </li></ul><ul><li>It operates in both </li></ul><ul><ul><li>Dynamic (sample) and </li></ul></ul><ul><ul><li>Static (hold) circumstances </li></ul></ul>
  16. 17. Track and Hold Circuit <ul><li>Analog Signal continues to vary in between the sampling periods. </li></ul><ul><li>In S/H circuit : Impulse functions are utilized for sampling. </li></ul><ul><li>In T/H circuit : Complete tracking time itself is sampling time. </li></ul>
  17. 18. Major Errors associated with S/H Circuit <ul><li>Op-amp: </li></ul><ul><ul><li>Matching of impedance such that the capacitor doesn’t discharge into the load. </li></ul></ul><ul><ul><li>Response dependent on slew rate, sampling will not be instantaneous at the output. </li></ul></ul>
  18. 20. <ul><li>Acquisition Time: Time taken by the S/H ckt. To track the analog signal, after the issue of the sampling command . </li></ul><ul><li>Cause: Improper compensation & smaller phase margin of the op-amp’s closed loop gain. </li></ul><ul><li>Worst case: Time required for the o/p to have transition from zero to V in(max) . </li></ul><ul><li>Comprises of Overshoot and Settling Time. </li></ul><ul><ul><li>Overshoot: Normalized difference b/w the time response peak & the steady o/p. </li></ul></ul><ul><ul><li>Settling Time: Time required for the response to reach & stay within a specified tolerance band (usually 2% or 5%) of its final value. </li></ul></ul>Major Errors associated with S/H Circuit: Sampling Mode
  19. 21. <ul><li>When control signal is removed, the switch turns off & capacitor holds the sampled value. </li></ul><ul><li>Pedestal Error. </li></ul><ul><li>Droop. </li></ul><ul><li>Aperture Error. </li></ul>Major Errors associated with S/H Circuit: Hold Mode
  20. 22. <ul><li>Pedestal Error: </li></ul><ul><ul><li>Def: Slight reduction in the o/p voltage, after the removal of the control signal. </li></ul></ul><ul><ul><li>Cause: Charge injection onto C H as MOSFET is turned off. </li></ul></ul><ul><li>Droop: </li></ul><ul><ul><li>Def: Gradual reduction in the o/p voltage. </li></ul></ul><ul><ul><li>Cause: Leakage of current from C H . </li></ul></ul><ul><ul><li>reduced by C H , but it Acquisition time. </li></ul></ul><ul><ul><li>Max. allowable droop is ½ LSB. </li></ul></ul>Major Errors associated with S/H Circuit: Hold Mode
  21. 23. <ul><ul><li>Occurs between sample & hold modes. </li></ul></ul><ul><ul><li>Cause: </li></ul></ul><ul><ul><ul><li>MOSFET doesn’t turn off until gate-voltage reached below V t .“ Aperture time”. </li></ul></ul></ul><ul><ul><ul><li>Switching noise in control signal. </li></ul></ul></ul><ul><ul><li>Worst case: At Zero crossing( dV/dt is max). </li></ul></ul><ul><ul><li>So, resolution of conversion is affected. </li></ul></ul>Major Errors associated with S/H Circuit: Hold Mode Aperture Error / Aperture jitter / Aperture Uncertainty
  22. 24. Ex.1) A periodic sinusoidal signal has maximum amplitude of 2V & frequency of 100KHz. If the aperture uncertainty is equal to 0.5ns, find the max. sampling error. <ul><li>Slew Rate = dV/dt </li></ul><ul><li>dV(max)/dt = </li></ul><ul><li>Max. Sampling Error =dV(max) </li></ul><ul><li>Ans: 0.628mV </li></ul>
  23. 25. Ex.2) A S/H ckt. is supposed to have a max. sampling error of 1mV, with the aperture jitter of 1ns. If the freq. of the signal is 50KHz, find its max. possible amplitude. <ul><li>Given: dV(max) = 1mV, dt = 1ns. </li></ul><ul><li>V in = A sin (2 π f)t </li></ul><ul><li>Substitute values in dV/dt = A (2 π f) x cos(2 π f)t </li></ul><ul><li>Ans: 3.18V </li></ul>
  24. 26. Resolution <ul><li>Def: The smallest change in voltage which can be produced at the output (or input) of the converter. </li></ul><ul><li>No. of Quantization levels corresponds to resolution. </li></ul><ul><li>For DAC: </li></ul><ul><ul><li>8 bit DAC has 2 8 -1 = 255 equal intervals. </li></ul></ul><ul><ul><li>Smallest change in output voltage is (1/255) of full scale output range. = 0.392 = 1LSB. </li></ul></ul><ul><ul><li>It is stated in no. of ways: </li></ul></ul><ul><ul><ul><li>8 bit resolution. </li></ul></ul></ul><ul><ul><ul><li>A resolution of 0.392 of full scale </li></ul></ul></ul><ul><ul><ul><li>A resolution of 1 part of 255. </li></ul></ul></ul>DAC Specifications contd.
  25. 27. <ul><li>For ADC: smallest change in analog input for a one bit change at the output. </li></ul><ul><ul><li>8 bit ADC: is divided into 255 intervals. </li></ul></ul><ul><ul><ul><li>Resolution for a 10V input range is 39.22mV (= 10/255 V) </li></ul></ul></ul>Resolution DAC Specifications contd.
  26. 28. DAC Specifications <ul><li>O/P voltage of DAC </li></ul><ul><li>V OUT = F. V REF </li></ul><ul><li>F = D / 2 N </li></ul><ul><li>where, D = Input word. </li></ul><ul><li>N = No. of bits </li></ul><ul><li>in the word. </li></ul><ul><li>2 N = No. of input combinations </li></ul>
  27. 29. Ex.3) If a 3 bit DAC is considered with V ref = 5V, and if the input word is 110, then V out is <ul><li>V out = {(110) 2 / 2 3 } x5 </li></ul><ul><li> =(6/8)x5 </li></ul><ul><li> =3.75V </li></ul><ul><li>Thus , the max analog o/p for this DAC can be, </li></ul><ul><li>V out (max) = (111) 2 / 2 3 x 5 = 4.375V </li></ul>
  28. 30. DAC Specifications contd.
  29. 31. Note <ul><li>Full Scale Voltage: </li></ul><ul><li>V FS = {(2 N -1)/ 2 N } x V REF </li></ul><ul><li>Resolution: 1 LSB = V REF / 2 N </li></ul><ul><li>More no. of i/p bits results in smaller changes in o/p voltage & thus yielding better resolution. </li></ul><ul><li>Hence, in case of data-converters, </li></ul><ul><li>the resolution is expressed in terms of the no. of bits. </li></ul><ul><li>Also, Accuracy of DAC = 1 / 2 N </li></ul>DAC Specifications contd.
  30. 32. <ul><li>Ex.4) Given V REF of a DAC is 5V & the o/p voltage increment desired is 1mV, find the resolution of the DAC. </li></ul><ul><li>Ans: using formula :1 LSB = V REF / 2 N </li></ul><ul><li>N= 12.29 bits = 13 </li></ul>DAC Specifications contd.
  31. 33. <ul><li>Ex. 5) A digitally programmable signal generator uses a 14 bit DAC with a 10V reference. Find a) Smallest incremental change at the o/p. b) DAC’s Full scale value. c) The accuracy. </li></ul><ul><li>Ans: a)1LSB = 610µV. </li></ul><ul><li>b) V FS = 9.9993V </li></ul><ul><li>c) Accuracy = 0.0062% </li></ul>DAC Specifications contd.
  32. 34. <ul><li>DIFFERENTIAL NONLINEARITY ERROR (DNL) </li></ul><ul><li>Cause : Non-linear components within DAC cause increments to differ from their ideal values. </li></ul><ul><li>Def: The difference between the ideal and non-ideal values of the increments. </li></ul><ul><li>DNL n = (Actual increment of transition n) –(Ideal increment height) </li></ul><ul><ul><li>Where, n = No. corresponding to digital i/p transition. </li></ul></ul>DAC Specifications contd.
  33. 35. DIFFERENTIAL NONLINEARITY ERROR (DNL) DAC Specifications contd.
  34. 36. <ul><li>Points to remember: </li></ul><ul><ul><li>DNL ≤ ± ½LSB. “ Monotonic ” i.e. the analog o/p does increment as digital input code is incremented. </li></ul></ul><ul><ul><li>If DNL = ± 1 LSB, then DAC is called as “ non– monotonic ”. </li></ul></ul><ul><ul><li>A 5-bit DAC with 0.75 LSBs DNL actually has resolution of 4-bit DAC. </li></ul></ul><ul><ul><li>So, DAC should exhibit montonicity to work without error. </li></ul></ul><ul><ul><li>The overall error of DAC is defined by its worst case DNL. </li></ul></ul>DIFFERENTIAL NONLINEARITY ERROR (DNL) DAC Specifications contd.
  35. 37. <ul><li>Def: The difference between the data converter o/p values & the corresponding points on the reference line drawn through the first & last o/p values. </li></ul><ul><li>INL n = (O/p value for i/p code n) – (o/p value on the reference line) </li></ul>INTEGRAL NONLINEARITY ERROR (INL) DAC Specifications contd.
  36. 38. <ul><li>DNL is defined in accordance with the increment height. i.e. the previous position. </li></ul><ul><li>INL defined in accordance with the slop of the curve. i.e. the transition line. </li></ul><ul><li>INL = (Actual o/p voltage) – (Ideal o/p voltage) </li></ul><ul><li>Note: </li></ul><ul><li>Using the value of V REF & resolution it is possible to </li></ul><ul><li>express DNL & INL in terms of volts as well. </li></ul><ul><li>Normally assumed that a DAC will have < ± ½LSB of DNL & INL. </li></ul>INTEGRAL NONLINEARITY ERROR (INL) DAC Specifications contd.
  37. 39. INTEGRAL NONLINEARITY ERROR (INL) DAC Specifications contd.
  38. 40. INTEGRAL NONLINEARITY ERROR (INL) DAC Specifications contd.
  39. 41. Q. Determine the maximum DNL (in LSBs) for a 3-bit DAC, which has the following characteristics. Does the DAC have 3-bit accuracy? If not, what is the resolution of the DAC having this characteristic?
  40. 42. Q. Repeat the above problem for calculating the INL (in LSB’s). <ul><li>The maximum magnitude INL is at 010 and at 110 where the actual analog output is 0.3125 above the line and 0.3125 below the line, respectively. </li></ul><ul><li>These INLs convert to ± ½LSB </li></ul><ul><li>after dividing by V REF /8 (1LSB). </li></ul><ul><li>The worst INL is ½ LSB and 3-bit accuracy is 1LSB, </li></ul><ul><li>so yes, it has 3-bit accuracy. </li></ul>
  41. 43. Q. A DAC has a reference voltage of 1,000V, and its maximum INL measures 2.5mV. What is the maximum resolution of the converter assuming that all the other characteristics of the converter are ideal? <ul><li>Assume that a converter with N-bit resolution will have less than ±0.5LSB of INL and DNL. </li></ul><ul><li>So, finding </li></ul><ul><li>Also, </li></ul>Answer will be N= 18 as when we substitute 17 in INL(max) it is greater than 2.5mV
  42. 44. ADC Specifications <ul><li>Process complex than DAC. </li></ul><ul><li>Infinite no. of input values. </li></ul><ul><li>Quantization of 2 N levels. </li></ul><ul><li>Transfer curve reverse of that of DAC. </li></ul>
  43. 45. ADC Specifications
  44. 46. Quantization Error Q E <ul><li>Def: The difference bet n the actual analog input & the value of the staircase o/p. </li></ul><ul><li>Q E = V IN – V staircase </li></ul><ul><li>Where, V staircase = D. V LSB </li></ul><ul><li>V LSB = V REF / 2 N </li></ul><ul><li>D = o/p ‘s coe’s value in decimal </li></ul><ul><li>Q E (max)= 1 LSB for above curve. </li></ul>ADC Specifications
  45. 47. Quantization Error Q E reduced by 50% ADC Specifications
  46. 48. <ul><li>Q E (max)= 0.5 LSB </li></ul><ul><li>Transitions occur in bet n two quantization levels. </li></ul><ul><li>However, last transition occurs bet n 6/8 and 7/8. </li></ul><ul><li>Also, step–width is 1.5 times larger than previous ones. Hence, Q E (max)= 1LSB. But it occurs at max. amplitude of the i/p signal. The converter considered out of range, for F ≥ 15/16. </li></ul><ul><li>Hence, Q E (max) remains = 0.5 LSB </li></ul>Quantization Error Q E reduced by 50% ADC Specifications
  47. 49. <ul><li>Def: The difference bet n the actual code width of a non-ideal converter & the ideal case. </li></ul><ul><li>DNL = (Actual Step width – Ideal Step width) </li></ul>DNL ADC Specifications
  48. 50. <ul><li>Q.Plot the transfer curve for the 3-bit ADC with V REF = 5V & with the following analog inputs: 0.3125V,0.9375V, 1.875V,2.1875V, 2.8125V, 3.125V, 4.0625V, 5.0V. Determine its DNL also. </li></ul>ADC Specifications
  49. 51. Ans : ADC Specifications
  50. 52. IMP points derived <ul><li>Quantization error directly related to the DNL. </li></ul><ul><li>As DNL increases in either direction, the quantization error worsens. </li></ul><ul><li>Each “tooth“ in the quantization error waveform should ideally be the same size. </li></ul>ADC Specifications
  51. 53. Missing codes <ul><li>In transfer curve, ideally, height remains constant. </li></ul><ul><li>But, if any step width becomes 2 LSB or more then the height gets increased. </li></ul><ul><li>Cause: ADC tries to follow-up with the slope of the ideal line. </li></ul><ul><li>Occurrence : when DNL exceeds ± 1 LSB </li></ul>ADC Specifications
  52. 54. INL <ul><li>Def: The difference between the data-converter code transition points & the ideal straight line. </li></ul><ul><li>INL = (Actual transition – Ideal transition) </li></ul>ADC Specifications
  53. 55. Determine the INL for the ADC whose. V REF = 5V & with the following analog inputs: 0.3125V,0.9375V, 1.875V,2.1875V, 2.8125V, 3.125V, 4.0625V, 5.0V. Determine its INL also. Draw the quantization error, Q, in units of LSBs. ADC Specifications
  54. 56. <ul><li>Q. Plot the transfer curve for the 3-bit ADC with VREF = 5V & with the following analog inputs : 0.3125V, 1.25V, 1.875V, 2.1875V, 3.4375V, 4.375V, 4.6875V, 5.0V. Determine its INL as well. </li></ul>ADC Specifications
  55. 57. Problem contd.. ADC Specifications
  56. 58. OFFSET ERROR & GAIN ERROR ADC Specifications
  57. 59. Aliasing ADC Specifications <ul><li>Analog signal sampled at a rate slower than the Nyquist criteria requires. </li></ul><ul><li>A totally different signal of lower frequency (dashed line) is being sampled actually. </li></ul><ul><li>the lower frequency signal is an “alias” of the original signal, its frequency given by f alias = f actual - f sample </li></ul>
  58. 60. <ul><li>Elimination Techniques: </li></ul><ul><ul><li>Sampling at higher frequencies. </li></ul></ul><ul><ul><li>Filtering the analog signal before sampling & removing any frequencies that are greater than half the sampling frequency. </li></ul></ul><ul><ul><ul><li>Removes unknown higher order harmonics or noise. </li></ul></ul></ul><ul><ul><ul><li>However, adds delay to overall conversion. </li></ul></ul></ul><ul><ul><li>Therefore, combination of both methods are used. </li></ul></ul>Aliasing ADC Specifications
  59. 61. Aliasing ADC Specifications
  60. 62. <ul><li>Def: represents the ratio of largest RMS input signal value into the converter over the RMS value of noise. Unit : dB. </li></ul><ul><li>SNR = 20 log(v in(max) / v noise ) </li></ul><ul><li>Input signal, v in(max) = 2 N . V LSB = V REF </li></ul><ul><li>Therefore , v in(max)RMS = 2 N . V LSB / 2√2 (=V p-p ) </li></ul><ul><li>RMS of Noise is Q e(RMS) = V LSB / √12 (as sawtooth waveform) </li></ul><ul><li>SNR = (6.02N + 1.76)dB </li></ul>SIGNAL TO NOISE RATIO ADC Specifications
  61. 63. <ul><li>SNR = (6.02N + 1.76)dB </li></ul><ul><li>Relates SNR to resolution </li></ul><ul><li>To find: </li></ul><ul><ul><li>Resolution </li></ul></ul><ul><ul><li>calculating SNRD( Signal to noise ratio with Distortion ratio ) </li></ul></ul><ul><li>As o/p is digital so can’t use Spectrum Analyzer to calculate ratio, but use DFT( Discrete Fourier Transform ) </li></ul>SIGNAL TO NOISE RATIO contd… ADC Specifications
  62. 64. <ul><li>Q. An ADC has a stated SNR of 94dB. Determine the resolution of the converter. </li></ul><ul><li>Given 94 = 6.02N + 1.76 </li></ul><ul><li>Therefore, N = (94 – 1.76) / 6.02 </li></ul><ul><li>=15.32 bits </li></ul>ADC Specifications
  63. 65. <ul><li>= SAMPLING ERROR IN S/H CKT. </li></ul><ul><li>Related to ADC characteristics. </li></ul><ul><li>Max. errors associated are related to 0.5LSB. </li></ul><ul><li>Aperture error can be no longer than 0.5LSB. </li></ul>APERTURE ERROR ADC Specifications
  64. 66. <ul><li>Q. Find the maximum resolution of an ADC which can use the S/H having aperture uncertainty of 0.628mV, while maintaining a sampling error less than 0.5LSB. </li></ul><ul><li>Ans. 0.628mV ≤ 0.5LSB </li></ul><ul><ul><ul><ul><ul><li> = V REF / 2 N+1 </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>= 5/ 2 N+1 </li></ul></ul></ul></ul></ul><ul><ul><ul><ul><ul><li>Now, 2 N+1 ≤ 7.961.8 </li></ul></ul></ul></ul></ul><ul><li>Solving for N limited to an integer, N =11 </li></ul>ADC Specifications
  65. 67. <ul><li>Analog ICs more sensitive to noise than digital. </li></ul><ul><li>Therefore, Layout to be done carefully. </li></ul><ul><li>So having both digital & analog at one single chip requires lot of attention & care. </li></ul><ul><li>Eg: Majority of ADCs uses switches controlled by digital signal, so separate routing channels needs to be provided. </li></ul><ul><li>A successful mixed-mode design will always minimize the effect of digital switching on the analog circuits. </li></ul>MIXED SIGNAL LAYOUT ISSUES
  66. 68. MIXED SIGNAL LAYOUT ISSUES
  67. 69. <ul><li>The integrated circuit from an Intel </li></ul><ul><li>8742, an 8-bit microcontroller that </li></ul><ul><li>includes a CPU running at 12 MHz, </li></ul><ul><li>128 bytes of RAM, 2048 bytes of </li></ul><ul><li>EPROM, and I/O in the same chip. </li></ul>MIXED SIGNAL LAYOUT ISSUES Integrated IC at NASA
  68. 70. <ul><li>Integrated circuit of </li></ul><ul><li>Atmel Diopsis 740 </li></ul><ul><li>System on Chip </li></ul><ul><li>showing memory blocks, </li></ul><ul><li>logic and input/output </li></ul><ul><li>pads around the </li></ul><ul><li>periphery </li></ul>MIXED SIGNAL LAYOUT ISSUES
  69. 71. MIXED SIGNAL LAYOUT ISSUES <ul><li>Techniques used to increase the success of mixed-signal designs vary </li></ul><ul><li>in complexity & priority. </li></ul><ul><li>Lowest issues are foundational & considered before each succeeding </li></ul><ul><li>step. </li></ul>
  70. 72. MIXED SIGNAL LAYOUT ISSUES FLOORPLANNING <ul><li>Analog circuitry categorized by the sensitivity of the analog signal to noise. </li></ul><ul><ul><li>Sensitive nodes: Low-level signals or high impedance nodes typically associated with input signals. </li></ul></ul><ul><ul><li>High-swing analog ckts: comparators & o/p buffer amplifiers. </li></ul></ul><ul><li>Digital Circuitry categorized by speed & function. </li></ul><ul><ul><li>Digital o/p buffers designed to drive capacitive loads at very high rates. So, kept farthest from sensitive analog signals. </li></ul></ul><ul><ul><li>Then high & low speed digital ckt should be kept. </li></ul></ul>
  71. 73. MIXED SIGNAL LAYOUT ISSUES POWER SUPPLY & GROUNDING Danger: Injecting noise from digital system to the sensitive analog circuitry through the power supply & ground connections. How power supply & ground are supplied to both? R i1 & R i2 = small & non-negligible resistance of the interconnect to the pad. L s1 & L s2 = inductance of bonding wire which connects the pads to the pin on the lead frame. Voltage Spike : 1) Digital circuitry has high transient currents due to switching, small amount of resistance associated with interconnect can result in significant spikes. Low level analog signals sensitive to such interference, thus contaminating analog system. 2)Inductance of the bonding wire. Voltage across the inductor α change in current through it. Voltage spikes equating to hundreds of multi volts can result.
  72. 74. MIXED SIGNAL LAYOUT ISSUES POWER SUPPLY & GROUNDING
  73. 75. <ul><li>Fig a) Serious degradation in analog circuitry performance as power supply & ground bounces : </li></ul><ul><ul><li>For low-swing signals, when there are transient currents due to high speed switching parasitic components become prominent : </li></ul></ul><ul><ul><ul><li>R = Resistance of the interconnect. </li></ul></ul></ul><ul><ul><ul><li>L = Inductance of the bonding wire. </li></ul></ul></ul><ul><li>Fig b) Parasitic resistance not common to digital & analog circuitry, but inductance still remains. </li></ul><ul><li>Fig c) two circuits completely decoupled, so low swing analog cktary completely isolated from switching transients. </li></ul><ul><ul><li>Disadv: pad count increases on die & pin count on lead frame. </li></ul></ul><ul><ul><li>NOTE: R ↓ Power supply & gnd bus widest possible. </li></ul></ul><ul><ul><li>L ↓ Planning supply & gnd pins closest to die. </li></ul></ul>MIXED SIGNAL LAYOUT ISSUES POWER SUPPLY & GROUNDING
  74. 76. MIXED SIGNAL LAYOUT ISSUES FULLY DIFFERENTIAL DESIGN <ul><li>i/ps & o/ps both designed to be differential. </li></ul><ul><li>noise that gets coupled thru stray capacitances gets rejected(common mode nature) </li></ul><ul><li>Common centroid & interdigitated techniques to match transistors in layout. </li></ul>
  75. 77. MIXED SIGNAL LAYOUT ISSUES GUARDED RINGS <ul><li>Sensitive circuitry placed inside a separate well. </li></ul><ul><li>Well surrounded by guard ring. </li></ul><ul><li>Guard ring connected to analog V DD , such that digital switching noise effect becomes minimum. </li></ul>
  76. 78. MIXED SIGNAL LAYOUT ISSUES SHIELDING Whenever low-level signal line crosses high speed digital line : <ul><li>Metal 1 placed in bet n analog & digital signals. </li></ul><ul><li>Analog signal = Poly layer. </li></ul><ul><li>Digital = Metal 2 Layer. </li></ul><ul><li>Shielding Metal 1 connected to analog ground. </li></ul>
  77. 79. MIXED SIGNAL LAYOUT ISSUES SHIELDING CONTD. <ul><li>During routing, sensitive analog line in parallel with high speed digital line should be avoided. </li></ul><ul><li>A shielding to be provided whenever not possible. </li></ul>
  78. 80. MIXED SIGNAL LAYOUT ISSUES OTHER INTERCONNECT CONSIDERATIONS <ul><li>Strategies to improve performance of analog circuitry: </li></ul><ul><ul><li>minimal Length of analog current carrying line. </li></ul></ul><ul><ul><li>Changing of layers -> use contacts (minimizes resistance in path & improves fabrication reliability). </li></ul></ul><ul><ul><li>Avoid poly for routing current carrying signals. </li></ul></ul><ul><ul><li>Use poly to route only high impedance gate nodes, which carry no current. </li></ul></ul>
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