ccNUMA Cache Coherent Non-Uniform Memory Access Chris Coughlin  MSCS521 Prof. Ten Eyck Spring 2004
Let’s First Talk About  Computer Architectures <ul><li>SISD(Single Instruction Stream-Single Data Stream) </li></ul><ul><l...
Multiprocessors <ul><li>The idea behind multiprocessors is to create powerful computers by connecting many smaller ones. <...
MIMD Systems <ul><li>Shared Memory Multiprocessor System </li></ul><ul><li>Multiple processors are connected to multiple m...
MIMD Systems (cont.) <ul><li>Multicomputer </li></ul><ul><li>A term for parallel processors with separate, private address...
Computer Architecture Classifications  Processor Organizations Single Instruction, Single Instruction, Multiple Instructio...
Back to Shared Memory Multiprocessors <ul><li>Two styles:  UMA  and  NUMA : </li></ul><ul><li>UMA (Uniform Memory Access) ...
Shared Memory Multiprocessors (cont.) <ul><li>NUMA (Non-Uniform Memory Access) </li></ul><ul><li>Since memory is physicall...
Communication and Connection Options for Multiprocessors Multiprocessors come in two main configurations: a single bus con...
A Multiprocessor Bus Configuration The single bus design is limited in terms of scalability.  The largest number of proces...
A Multiprocessor Network Configuration The network-connected processor design is very scalable.  Since each processor has ...
A Quick Look at Cache <ul><li>Modern processors use a faster, smaller  cache   memory to act as a buffer for slower, large...
What is  ccNUMA ? <ul><li>The  cc  in ccNUMA stands for  c ache  c oherent . </li></ul><ul><li>The use of cache memory in ...
Computer Architecture Classifications (revisited)   Processor Organizations Single Instruction, Single Instruction, Multip...
Cache Coherency Protocols <ul><li>Snooping protocol   </li></ul><ul><li>A bus-based method in which cache controllers moni...
Cache Coherency Protocols (cont.) <ul><li>Directory-based protocol   </li></ul><ul><li>A central directory maintains the i...
A Side-Effect of Cache Coherency <ul><li>False sharing </li></ul><ul><li>Caches are organized into blocks of contiguous me...
ccNUMA Implementations <ul><li>Stanford Dash  –  </li></ul><ul><li>Dash stands for Directory Architecture for Shared Memor...
References <ul><li>Computer Organization and Design: The Hardware/Software Interface, David A. Patterson & John L. Henness...
References (cont.) <ul><li>A Primer on NUMA ( Non-Uniform Memory Access) </li></ul><ul><li>Cache Coherence in the context ...
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ccNUMA Cache Coherent Non-Uniform Memory Access

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ccNUMA Cache Coherent Non-Uniform Memory Access

  1. 1. ccNUMA Cache Coherent Non-Uniform Memory Access Chris Coughlin MSCS521 Prof. Ten Eyck Spring 2004
  2. 2. Let’s First Talk About Computer Architectures <ul><li>SISD(Single Instruction Stream-Single Data Stream) </li></ul><ul><li>A single-processor computer (uniprocessor) in which a single stream of instructions is generated from the program. </li></ul><ul><li>SIMD(Single Instruction Stream-Multiple Data Stream) </li></ul><ul><li>Each instruction is executed on a different set of data by different processors. (Used for vector and array processing) </li></ul><ul><li>MISD(Multiple Instruction Stream-Single Data Stream) </li></ul><ul><li>Each processor executes a different sequence of instructions. </li></ul><ul><li>Never been commercially implemented. </li></ul><ul><li>MIMD(Multiple Instruction Stream-Multiple Data Stream) </li></ul><ul><li>Each processor has a separate program. </li></ul><ul><li>An instruction stream is generated from each program. </li></ul><ul><li>Each instruction operates on different data. </li></ul>In 1966, Michael Flynn proposed a classification for computer architectures based on the number of instruction steams and data streams (Flynn’s Taxonomy).
  3. 3. Multiprocessors <ul><li>The idea behind multiprocessors is to create powerful computers by connecting many smaller ones. </li></ul><ul><li>Computational speed is increased by using multiple processors operating together on a single problem. </li></ul><ul><li>A parallel processing program is a single program that runs on multiple processors simultaneously. </li></ul><ul><li>The overall problem is split into parts, each of which is performed by a separate processor in parallel. </li></ul><ul><li>In addition to a faster solution, it may also generate a more precise solution. </li></ul>
  4. 4. MIMD Systems <ul><li>Shared Memory Multiprocessor System </li></ul><ul><li>Multiple processors are connected to multiple memory modules such that each processor can access any other processor’s memory module. This multiprocessor employs a shared address space (also known as a single address space). </li></ul><ul><li>Communication is implicit with loads and stores – there is no explicit recipient of a shared memory access. </li></ul><ul><li>Processors may communicate without necessarily being aware of one another. </li></ul><ul><li>A single image of the operating system runs across all the processors. </li></ul>
  5. 5. MIMD Systems (cont.) <ul><li>Multicomputer </li></ul><ul><li>A term for parallel processors with separate, private address spaces ( not accessible by the other processors in the system). </li></ul><ul><li>Communicate by message-passing – the messages carry data from one processor to another as dictated by the program. </li></ul><ul><li>Complete computers, consisting of a processor and local memory, connected through an interconnection network (e.g. a LAN). </li></ul>
  6. 6. Computer Architecture Classifications Processor Organizations Single Instruction, Single Instruction, Multiple Instruction Multiple Instruction Single Data Stream Multiple Data Stream Single Data Stream Multiple Data Stream (SISD) (SIMD) (MISD) (MIMD) Uniprocessor Vector Array Shared Memory Multicomputer Processor Processor (tightly coupled) (loosely coupled) Note: We will expand on this later
  7. 7. Back to Shared Memory Multiprocessors <ul><li>Two styles: UMA and NUMA : </li></ul><ul><li>UMA (Uniform Memory Access) </li></ul><ul><li>The time to access main memory is the same for all processors since they are equally close to all memory locations. </li></ul><ul><li>Machines that use UMA are called Symmetric Multiprocessors (SMPs). </li></ul><ul><li>In a typical SMP architecture, all memory accesses are posted to the same shared memory bus. </li></ul><ul><li>Contention - as more CPUs are added, competition for access to the bus leads to a decline in performance. </li></ul><ul><li>Thus, scalability is limited to about 32 processors. </li></ul>
  8. 8. Shared Memory Multiprocessors (cont.) <ul><li>NUMA (Non-Uniform Memory Access) </li></ul><ul><li>Since memory is physically distributed, it is faster for a processor to access its own local memory than non-local memory (memory local to another processor or shared between processors). </li></ul><ul><li>Unlike SMPs, all processors are not equally close to all memory locations. </li></ul><ul><li>A processor’s own internal computations can be done in its local memory leading to reduced memory contention. </li></ul><ul><li>Designed to surpass the scalability limits of SMPs. </li></ul>
  9. 9. Communication and Connection Options for Multiprocessors Multiprocessors come in two main configurations: a single bus connection, and a network connection. The choice of the communication model and the physical connection depends largely on the number of processors in the organization. Notice that the scalability of NUMA makes it ideal for a network configuration. UMA, however, is best suited to a bus connection. NUMA UMA 2-36 Bus 8-256 Network Physical Connection 8-256 2-64 Shared address 8-256 Message passing Communication model Number of Processors Choice Category
  10. 10. A Multiprocessor Bus Configuration The single bus design is limited in terms of scalability. The largest number of processors in a commercial product using this configuration is 36 (SGI Power Challenge).
  11. 11. A Multiprocessor Network Configuration The network-connected processor design is very scalable. Since each processor has its own memory, the network connection is only used for communication between processors.
  12. 12. A Quick Look at Cache <ul><li>Modern processors use a faster, smaller cache memory to act as a buffer for slower, larger memory. </li></ul><ul><li>Caches exploit the principal of locality in memory accesses . </li></ul><ul><li>Temporal locality – the concept that if data is referenced, it will tend to be referenced again soon after. </li></ul><ul><li>Spatial locality – the concept that data is more likely to be referenced soon if data near it was just referenced. </li></ul><ul><li>Caches hold recently referenced data, as well as data near the recently referenced data. </li></ul><ul><li>This can lead to performance increases by reducing the need to access main memory on every reference. </li></ul>
  13. 13. What is ccNUMA ? <ul><li>The cc in ccNUMA stands for c ache c oherent . </li></ul><ul><li>The use of cache memory in modern computer architectures leads to the cache coherence problem . </li></ul><ul><li>It is a situation that can occur when two or more processors reference the same shared data. If one processor modifies its copy of the data, the other processors will have stale copies of the data in their caches. </li></ul><ul><li>Machines that are cache coherent ensure that a processor accessing a memory location receives the most up-to-date version of the data. </li></ul><ul><li>Cache coherence is maintained by software, special-purpose hardware, or both. </li></ul><ul><li>NUMA systems that maintain cache coherence are referred to as ccNUMA machines. </li></ul><ul><li>Since few applications still exist for non-cache coherent NUMA machines, the terms NUMA and ccNUMA are used interchangeably. </li></ul>
  14. 14. Computer Architecture Classifications (revisited) Processor Organizations Single Instruction, Single Instruction, Multiple Instruction Multiple Instruction Single Data Stream Multiple Data Stream Single Data Stream Multiple Data Stream (SISD) (SIMD) (MISD) (MIMD) Uniprocessor Vector Array Shared Memory Multicomputer Processor Processor (tightly coupled) (loosely coupled) UMA (SMP) NUMA ccNUMA
  15. 15. Cache Coherency Protocols <ul><li>Snooping protocol </li></ul><ul><li>A bus-based method in which cache controllers monitor the bus for activity and update or invalidate cache entries as necessary. </li></ul><ul><li>Two types: </li></ul><ul><li>Write invalidate – the writing processor sends an invalidation signal to the bus. All other caches check to see if they have a copy of the cache block. If they do, the block containing the data gets invalidated. The writing processor then changes its local copy. </li></ul><ul><li>Write-update – the writing processor broadcasts the new data over the bus and all copies are updated with the new value. </li></ul><ul><li>Commercial machines use write-invalidate to preserve bandwidth. </li></ul><ul><li>Write-update has the advantage of making the new values appear in the caches sooner. </li></ul>
  16. 16. Cache Coherency Protocols (cont.) <ul><li>Directory-based protocol </li></ul><ul><li>A central directory maintains the information about which memory locations are being shared in multiple caches and which are contained in just one processor’s cache. </li></ul><ul><li>On any memory access, it knows the caches that need to be updated or invalidated. </li></ul><ul><li>It is used by all software-based implementations of shared memory. </li></ul><ul><li>It is a scalable scheme that is suitable for a network configuration. </li></ul>
  17. 17. A Side-Effect of Cache Coherency <ul><li>False sharing </li></ul><ul><li>Caches are organized into blocks of contiguous memory locations – mainly because programs tend to use spatial locality of reference. </li></ul><ul><li>It is therefore possible for two processors to share the same cache block, but to not share the same memory location within the block. </li></ul><ul><li>If one processor writes to its own part of the block, it then causes the other processor’s entire block, including the memory location it was accessing, to get updated or invalidated. </li></ul><ul><li>Unnecessary invalidations can affect performance. </li></ul><ul><li>It is up to the programmer to detect it and avoid it. </li></ul><ul><li>Compiler-based solutions are being researched. </li></ul>
  18. 18. ccNUMA Implementations <ul><li>Stanford Dash – </li></ul><ul><li>Dash stands for Directory Architecture for Shared Memory. </li></ul><ul><li>First to use directory-based cache coherence. </li></ul><ul><li>SGI Origin 2000 (Silicon Graphics Inc.) - </li></ul><ul><li>Can support up to 1024 processors. </li></ul><ul><li>SGI claims it accounts for over 95% of worldwide shipments of ccNUMA-based systems . </li></ul><ul><li>IBM’s LA (Local Access) ccNUMA </li></ul>
  19. 19. References <ul><li>Computer Organization and Design: The Hardware/Software Interface, David A. Patterson & John L. Hennessy, 1998, 2 nd edition </li></ul><ul><li>Supercomputing Systems: Architectures, Design, and Performance, Svetlana P. Kartashev & Steven I. Kartashev, 1990 </li></ul><ul><li>Parallel Programming: Techniques and Applications Using Networked Workstations and Parallel Computers, Barry Wilkinson & Michael Allen, 1999 </li></ul><ul><li>www.mkp.com/cod2e.htm </li></ul><ul><li>Non-Uniform Memory Access – Wikipedia </li></ul><ul><li>Symmetric Multiprocessing - Wikipedia </li></ul><ul><li>Cache Coherence - Wikipedia </li></ul><ul><li>Parallel Computing - Wikipedia </li></ul><ul><li>Locality of Reference – Wikipedia </li></ul>
  20. 20. References (cont.) <ul><li>A Primer on NUMA ( Non-Uniform Memory Access) </li></ul><ul><li>Cache Coherence in the context of Shared Memory Architecture </li></ul><ul><li>Distributed shared memory -- ccNUMA interconnects </li></ul><ul><li>The Stanford Dash Multiprocessor </li></ul><ul><li>The SGI Origin: A ccNUMA Highly Scalable Server </li></ul><ul><li>IBM Distributed Shared Memory Plans Uncovered </li></ul><ul><li>http:// benchoi .info/Bens/Teaching/Csc364/PDF/CH18. pdf </li></ul><ul><li>http://www. cs . ucsd . edu /classes/fa00/cse240/lectures/Lecture17.html </li></ul><ul><li>http://www. cs . ucsd . edu /users/carter/260/260class02. pdf </li></ul>

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