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Field programable gate array
 

Field programable gate array

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Contact me on pradeep1961@gmail.com if you wanna load the presenation.

Contact me on pradeep1961@gmail.com if you wanna load the presenation.

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    Field programable gate array Field programable gate array Presentation Transcript

    • FIELD PROGRAMABLE GATE ARRAY
      PREPARED BY:-
      NEHA AGARWAL
      B.TECH(EC) Vth SEM
      BTBTE08057
    • WHAT IS FPGA?
      • a PLD with high density and capable of implementing different functions in a short period of time
      • silicon chip containing an array of configurable logic blocks (CLB)
      • can be reprogrammed to perform a different function in a matter of microseconds
    • WHAT IS FPGA?
    • WHAT IS PROGRAMMABLE LOGIC DEVICE (PLD)?
      • is an electronic component used to build reconfigurable digital circuits
      • has an undefined function at the time of manufacture
      • before using in a circuit it must be programmed or reconfigured
      • can be customized as per needs of the user by programming
      • can be reprogrammed in case of problems
    • ARCHITECTURE OF FPGA
      • There are three key parts of a FPGA structure:
      I/O BLOCKS: it forms a ring around the outer edge of the structure
      INTERCONNECTS: connects logic blocks to logic blocks and I/O blocks to logic blocks
      LOGIC BLOCKS: Inside the ring of I/O blocks lies a rectangular array of logic blocks.
    • ARCHITECTURE OF FPGA
    • ARCHITECTURE OF FPGA:I/O BLOCKS
      • FPGAs provide support for I/O standards providing interface bridge in a system.
      • I/O in FPGAs is grouped in banks with each bank independently able to support different I/O standards.
    • ARCHITECTURE OF FPGA:LOGIC BLOCKS
      • The logic blocks in an FPGA are generally nothing more than a couple of logic gates or a look-up table and a flip-flop.
      • Its purpose is to implement combinational and sequential logic functions.
      • Logic blocks can be implemented by:-
      Transistor pairs
      Multiplexers
      Look up tables( LUT)
      Wide fan-in AND-OR structure.
    • ARCHITECTURE OF FPGA: ROUTING MATRIX
      • An FPGA device contains flexible programmable routing matrix which is used to connect logic blocks with each other.
      • There are various type of connection lines in FPGA:
      long lines are used to connect distant logic blocks
      short lines connect neighboring blocks with each other
      dedicated clock trees are used to distribute synchronization signals
      dedicated set/reset lines are used to reset all flip-flops in the FPGA
    • HOW FPGA WORKS?
    • HOW FPGA WORKS?
      • When a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments
    • PROGRAMMING A FPGA
      • Understand and define design requirements
      • Design description
      • Behavioral simulation
      • Synthesis
      • Implementation
      • Translate
      • Mapping
      • Place and Route
      • Timing or Post layout simulation
      • Programming, Test and Debug
    • PROGRAMMING A FPGA
      • This is how a program in any HDL is loaded on the FPGA or any other PLD.
    • PROGRAMMING METHODOLOGY
      • Electrically programmable switches are used to program FPGA
      • Properties of programmable switch determine: resistance, volatility, reprogrammability, size etc.
      • Various programming techniques are:
      SRAM PROGRAMMING TECHNOLOGY
      EPROM/EEPROM PROGRAMMING TECHNOLOGY
      ANTIFUSE PROGRAMMING METHODOLOGY
    • PROGRAMMING METHODOLOGY: SRAM PROGRAMMING TECHNOLOGY
      • Use Static RAM cells to control pass gates or multiplexers
      • SRAM cells control the configuration of logic block as well
      • Advantage:
      Fast re-programmability, lesser configuration time
      In-circuit re-programmable
      • Disadvantage:
      SRAM is volatile
      Requires large area
      Needs an external storage
      Needs a power-on configuration mechanism
    • PROGRAMMING METHODOLOGY: EPROM/EEPROM PROGRAMMING
      • Tech used in EPROM and EEPROM devices is used Switch is disable by applying high voltage to gate-2 between gate-1 and drain.
      • The charge is removed by UV light
      • Advantage
      No external permanent memory is needed to program it at power-up
      Re-programmable by exposing to UV radiation or high voltage
      • Disadvantage
      Consumes static power
      Not in-system re-programmable
    • PROGRAMMING METHODOLOGY: ANTIFUSE PROGRAMMING METHODOLOGY
      • two terminal device with an un-programmed state present very high resistance
      • By applying high voltage create a low resistance link
      • Advantage
      Small size
      Retain configuration after power off
      • Disadvantage
      One Time Programmable
    • ADVANTAGE DISADVANTAGE
      • faster response times
      • reduced time to market
      • low cost
      • long-term maintenance
      • reduced development time and risk
      • harsh environments
      • FPGAs are generally slower than application-specific integrated circuit (ASIC)
      • It cannot handle complex designs
      • draw more power
    • APPLICATIONS
      • aerospace & defense
      • automotive
      • broadcast
      • full-featured consumer applications
      • fulfilling industrial/ scientific/ medical needs
      • wireless communications
      • wired communications
    • REFERENCE
      • WEB REFERENCE:
      http://www.cse.iitb.ac.in/~cs330/FPGA-Arch.ppt
      www.fpgacentral.com
      http://en.wikipedia.org/wiki/Field_Programmable_Gate_Array
      • BOOK REFERNECE:
      FPGA ARCHITECTURE Survey and Challenges by Ian Kuon (University of Toronto, Canada), Russell Tessier (University of Massachusetts, Amherst, USA) & Jonathan Rose (University of Toronto, Canada) 
    • THANK YOU