FIELD PROGRAMABLE GATE ARRAY<br />PREPARED BY:-		<br />NEHA AGARWAL	<br />B.TECH(EC) Vth SEM	<br />BTBTE08057		<br />
WHAT IS FPGA?<br /><ul><li>a PLD with high density and capable of implementing different functions in a short period of time
silicon chip containing an array of configurable logic blocks (CLB)
can be reprogrammed to perform a different function in a matter of microseconds</li></li></ul><li>WHAT IS FPGA?<br />
WHAT IS PROGRAMMABLE LOGIC DEVICE (PLD)?<br /><ul><li>is an electronic component used to build reconfigurable digital circ...
has an undefined function at the time of manufacture
before using in a circuit it must be programmed or reconfigured
can be customized as per needs of the user by programming
can be reprogrammed in case of problems</li></li></ul><li>ARCHITECTURE OF FPGA<br /><ul><li>There are three key parts of a...
ARCHITECTURE OF FPGA<br />
ARCHITECTURE OF FPGA:I/O BLOCKS<br /><ul><li>FPGAs provide support for I/O standards providing interface bridge in a system.
I/O in FPGAs is grouped in banks with each bank independently able to support different I/O standards.</li></li></ul><li>A...
Its purpose is to implement combinational and sequential logic functions.
Logic blocks can be implemented by:-</li></ul>Transistor pairs<br />Multiplexers <br />Look up tables( LUT)<br />Wide fan-...
ARCHITECTURE OF FPGA: ROUTING MATRIX<br /><ul><li>An FPGA device contains flexible programmable routing matrix which is us...
There are various type of connection lines in FPGA:</li></ul>long lines are used to connect distant logic blocks<br />shor...
HOW FPGA WORKS?<br />
HOW FPGA WORKS?<br /><ul><li>When a wire enters a switch box, there are three programmable switches that allow it to conne...
Design description
Behavioral simulation
Synthesis
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Transcript of "Field programable gate array"

  1. 1. FIELD PROGRAMABLE GATE ARRAY<br />PREPARED BY:- <br />NEHA AGARWAL <br />B.TECH(EC) Vth SEM <br />BTBTE08057 <br />
  2. 2. WHAT IS FPGA?<br /><ul><li>a PLD with high density and capable of implementing different functions in a short period of time
  3. 3. silicon chip containing an array of configurable logic blocks (CLB)
  4. 4. can be reprogrammed to perform a different function in a matter of microseconds</li></li></ul><li>WHAT IS FPGA?<br />
  5. 5. WHAT IS PROGRAMMABLE LOGIC DEVICE (PLD)?<br /><ul><li>is an electronic component used to build reconfigurable digital circuits
  6. 6. has an undefined function at the time of manufacture
  7. 7. before using in a circuit it must be programmed or reconfigured
  8. 8. can be customized as per needs of the user by programming
  9. 9. can be reprogrammed in case of problems</li></li></ul><li>ARCHITECTURE OF FPGA<br /><ul><li>There are three key parts of a FPGA structure: </li></ul>I/O BLOCKS: it forms a ring around the outer edge of the structure<br />INTERCONNECTS: connects logic blocks to logic blocks and I/O blocks to logic blocks<br />LOGIC BLOCKS: Inside the ring of I/O blocks lies a rectangular array of logic blocks.<br />
  10. 10. ARCHITECTURE OF FPGA<br />
  11. 11. ARCHITECTURE OF FPGA:I/O BLOCKS<br /><ul><li>FPGAs provide support for I/O standards providing interface bridge in a system.
  12. 12. I/O in FPGAs is grouped in banks with each bank independently able to support different I/O standards.</li></li></ul><li>ARCHITECTURE OF FPGA:LOGIC BLOCKS<br /><ul><li>The logic blocks in an FPGA are generally nothing more than a couple of logic gates or a look-up table and a flip-flop.
  13. 13. Its purpose is to implement combinational and sequential logic functions.
  14. 14. Logic blocks can be implemented by:-</li></ul>Transistor pairs<br />Multiplexers <br />Look up tables( LUT)<br />Wide fan-in AND-OR structure. <br />
  15. 15. ARCHITECTURE OF FPGA: ROUTING MATRIX<br /><ul><li>An FPGA device contains flexible programmable routing matrix which is used to connect logic blocks with each other.
  16. 16. There are various type of connection lines in FPGA:</li></ul>long lines are used to connect distant logic blocks<br />short lines connect neighboring blocks with each other<br />dedicated clock trees are used to distribute synchronization signals<br />dedicated set/reset lines are used to reset all flip-flops in the FPGA<br />
  17. 17. HOW FPGA WORKS?<br />
  18. 18. HOW FPGA WORKS?<br /><ul><li>When a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments</li></li></ul><li>PROGRAMMING A FPGA<br /><ul><li>Understand and define design requirements
  19. 19. Design description
  20. 20. Behavioral simulation
  21. 21. Synthesis
  22. 22. Implementation
  23. 23. Translate
  24. 24. Mapping
  25. 25. Place and Route
  26. 26. Timing or Post layout simulation
  27. 27. Programming, Test and Debug</li></li></ul><li>PROGRAMMING A FPGA<br /><ul><li>This is how a program in any HDL is loaded on the FPGA or any other PLD.</li></li></ul><li>PROGRAMMING METHODOLOGY<br /><ul><li>Electrically programmable switches are used to program FPGA
  28. 28. Properties of programmable switch determine: resistance, volatility, reprogrammability, size etc.
  29. 29. Various programming techniques are:</li></ul>SRAM PROGRAMMING TECHNOLOGY <br />EPROM/EEPROM PROGRAMMING TECHNOLOGY<br />ANTIFUSE PROGRAMMING METHODOLOGY<br />
  30. 30. PROGRAMMING METHODOLOGY: SRAM PROGRAMMING TECHNOLOGY<br /><ul><li>Use Static RAM cells to control pass gates or multiplexers
  31. 31. SRAM cells control the configuration of logic block as well
  32. 32. Advantage:</li></ul>Fast re-programmability, lesser configuration time<br />In-circuit re-programmable<br /><ul><li>Disadvantage:</li></ul>SRAM is volatile <br />Requires large area<br />Needs an external storage<br />Needs a power-on configuration mechanism<br />
  33. 33. PROGRAMMING METHODOLOGY: EPROM/EEPROM PROGRAMMING<br /><ul><li>Tech used in EPROM and EEPROM devices is used Switch is disable by applying high voltage to gate-2 between gate-1 and drain.
  34. 34. The charge is removed by UV light
  35. 35. Advantage</li></ul>No external permanent memory is needed to program it at power-up<br />Re-programmable by exposing to UV radiation or high voltage<br /><ul><li>Disadvantage</li></ul>Consumes static power<br />Not in-system re-programmable<br />
  36. 36. PROGRAMMING METHODOLOGY: ANTIFUSE PROGRAMMING METHODOLOGY<br /><ul><li>two terminal device with an un-programmed state present very high resistance
  37. 37. By applying high voltage create a low resistance link
  38. 38. Advantage</li></ul>Small size<br />Retain configuration after power off<br /><ul><li>Disadvantage</li></ul>One Time Programmable<br />
  39. 39. ADVANTAGE DISADVANTAGE<br /><ul><li>faster response times
  40. 40. reduced time to market
  41. 41. low cost
  42. 42. long-term maintenance
  43. 43. reduced development time and risk
  44. 44. harsh environments
  45. 45. FPGAs are generally slower than application-specific integrated circuit (ASIC)
  46. 46. It cannot handle complex designs
  47. 47. draw more power</li></li></ul><li>APPLICATIONS<br /><ul><li>aerospace & defense
  48. 48. automotive
  49. 49. broadcast
  50. 50. full-featured consumer applications
  51. 51. fulfilling industrial/ scientific/ medical needs
  52. 52. wireless communications
  53. 53. wired communications</li></li></ul><li>REFERENCE<br /><ul><li>WEB REFERENCE:</li></ul>http://www.cse.iitb.ac.in/~cs330/FPGA-Arch.ppt<br />www.fpgacentral.com <br />http://en.wikipedia.org/wiki/Field_Programmable_Gate_Array<br /><ul><li>BOOK REFERNECE:</li></ul>FPGA ARCHITECTURE Survey and Challenges by Ian Kuon (University of Toronto, Canada), Russell Tessier (University of Massachusetts, Amherst, USA) & Jonathan Rose (University of Toronto, Canada) <br />
  54. 54. THANK YOU<br />

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