FIELD PROGRAMABLE GATE ARRAY<br />PREPARED BY:- <br />NEHA AGARWAL <br />B.TECH(EC) Vth SEM <br />BTBTE08057 <br />
WHAT IS FPGA?<br /><ul><li>a PLD with high density and capable of implementing different functions in a short period of time
silicon chip containing an array of configurable logic blocks (CLB)
can be reprogrammed to perform a different function in a matter of microseconds</li></li></ul><li>WHAT IS FPGA?<br />
WHAT IS PROGRAMMABLE LOGIC DEVICE (PLD)?<br /><ul><li>is an electronic component used to build reconfigurable digital circuits
has an undefined function at the time of manufacture
before using in a circuit it must be programmed or reconfigured
can be customized as per needs of the user by programming
can be reprogrammed in case of problems</li></li></ul><li>ARCHITECTURE OF FPGA<br /><ul><li>There are three key parts of a FPGA structure: </li></ul>I/O BLOCKS: it forms a ring around the outer edge of the structure<br />INTERCONNECTS: connects logic blocks to logic blocks and I/O blocks to logic blocks<br />LOGIC BLOCKS: Inside the ring of I/O blocks lies a rectangular array of logic blocks.<br />
ARCHITECTURE OF FPGA:I/O BLOCKS<br /><ul><li>FPGAs provide support for I/O standards providing interface bridge in a system.
I/O in FPGAs is grouped in banks with each bank independently able to support different I/O standards.</li></li></ul><li>ARCHITECTURE OF FPGA:LOGIC BLOCKS<br /><ul><li>The logic blocks in an FPGA are generally nothing more than a couple of logic gates or a look-up table and a flip-flop.
Its purpose is to implement combinational and sequential logic functions.
Logic blocks can be implemented by:-</li></ul>Transistor pairs<br />Multiplexers <br />Look up tables( LUT)<br />Wide fan-in AND-OR structure. <br />
ARCHITECTURE OF FPGA: ROUTING MATRIX<br /><ul><li>An FPGA device contains flexible programmable routing matrix which is used to connect logic blocks with each other.
There are various type of connection lines in FPGA:</li></ul>long lines are used to connect distant logic blocks<br />short lines connect neighboring blocks with each other<br />dedicated clock trees are used to distribute synchronization signals<br />dedicated set/reset lines are used to reset all flip-flops in the FPGA<br />
HOW FPGA WORKS?<br /><ul><li>When a wire enters a switch box, there are three programmable switches that allow it to connect to three other wires in adjacent channel segments</li></li></ul><li>PROGRAMMING A FPGA<br /><ul><li>Understand and define design requirements
Programming, Test and Debug</li></li></ul><li>PROGRAMMING A FPGA<br /><ul><li>This is how a program in any HDL is loaded on the FPGA or any other PLD.</li></li></ul><li>PROGRAMMING METHODOLOGY<br /><ul><li>Electrically programmable switches are used to program FPGA
Properties of programmable switch determine: resistance, volatility, reprogrammability, size etc.
Advantage</li></ul>No external permanent memory is needed to program it at power-up<br />Re-programmable by exposing to UV radiation or high voltage<br /><ul><li>Disadvantage</li></ul>Consumes static power<br />Not in-system re-programmable<br />
PROGRAMMING METHODOLOGY: ANTIFUSE PROGRAMMING METHODOLOGY<br /><ul><li>two terminal device with an un-programmed state present very high resistance
By applying high voltage create a low resistance link
Advantage</li></ul>Small size<br />Retain configuration after power off<br /><ul><li>Disadvantage</li></ul>One Time Programmable<br />
ADVANTAGE DISADVANTAGE<br /><ul><li>faster response times
wired communications</li></li></ul><li>REFERENCE<br /><ul><li>WEB REFERENCE:</li></ul>http://www.cse.iitb.ac.in/~cs330/FPGA-Arch.ppt<br />www.fpgacentral.com <br />http://en.wikipedia.org/wiki/Field_Programmable_Gate_Array<br /><ul><li>BOOK REFERNECE:</li></ul>FPGA ARCHITECTURE Survey and Challenges by Ian Kuon (University of Toronto, Canada), Russell Tessier (University of Massachusetts, Amherst, USA) & Jonathan Rose (University of Toronto, Canada) <br />