Good afternoon I am Nazrul Anuar Bin Nayan of Sekine and Takahashi Lab.. The title of my presentation is Two Phase Clocked Adiabatic Static CMOS Logic : Analysis, Application and LSI Implementation.
The presentation is divided into 6 parts as in the chapters of the graduate thesis. Chapter 1- Introduction, Chapter 2 – Principle of Adiabatic, 3 – Two-phase clocked adiabatic static CMOS logic (2PASCL), 4- Application Circuits, 5- LSI Implementation, and finally Chapter 6 – Summary and Future works.
As the motivation, designers dream can be divided into 2 : 1. for portable devices such as iPad – to increase battery life continously. 2. for high-end circuits , such-as processors, to avoid cooling packages and reliability issue due to increasing power.
Some of the approaches for low power circuits. At circuit design level……. Then, to solve the dynamic power the approaches are such as …… as the energy dissipation is wr=1/2ClVdd^2. The lower the Cl and Vdd, the lower the energy dissipation, however the drawbacks are the increase in static power consumption. Finally adiabatic switching, a method to solve dynamic power with less effect on the static power.
By reducing the current flow and by using adiabatic switching, my solution is two phase clocked adiabatic static CMOS logic (2PASCL)
The target device applications for this research are the low power, low frequency devices such as smart cards, sensors and RFIDs.
In CMOS the power dissipation produced from the leakage, short-circuit and dynamic current. Leakage power is dissipated when the turned-off device leaks current. Short circuit occurs when the input is higher than threshold voltage of nMOS, and dynamic power produced during charging and discharging. Short-circuit and dynamic power consumption occupies more than 90% for processes larger than 0.18 micron. However, for 70 nm process and below, the leakage is the dominant. In present research, I am implementing adiabatic switching, a method to reduce dynamic power.
From this CMOS equivalent circuit, ep and en are the step voltage supply, ip, the current flow. For pull up networks, power dissipation at resistive elements is Rpip^2. In present research I am focusing on how to reduce this ip. A little different approach compared to conventional method nowadays being done everywhere emphasizing on reducing Vdd. For pull down networks, same amount of power is dissipated. Since on resistance contributes to the power dissipation, I had done the simulation to estimate the on-resistance value using RC equivalent circuit and to confirm whether this equivalent circuit is appropriate.
Therefore, by simulation using 0.18u CMOS technology and RC equivalent circuit, the on-resistance for pull-up and pull-down network gained is 10 kOhm and 4 kOhm respectively. For 1.2 um technology, the on-resistance achieved from the equivalent circuit is 3.8kohm for pull up network and 2.2 kohm for pull down network. Here, we clearly understand that different process resulting in different on resistance.
Theoretically, for adiabatic charging, charge can be transferred without generating heat. Instead of constant , the power supply is a ramped-step voltage. Tau is the time for the voltage to change from 0 to Vdd vice versa. I have derived the energy dissipation equation and found that at resistive element , the energy dissipation is depending on tau. Therefore, if tau is long, we can reduce the energy dissipation accordingly.
From this analytical study, I plot comparison graphs to demonstrate the current. As the area below the line demonstrates power dissipation or Ri^2, when the current reduced, the total power dissipation is reduced too. Then from energy graph, we can see that energy supplied in CMOS step voltage, wp is increasing but for the adiabatic ramped step voltage, there is a decreasing here when the energy is delivered back to the power source. I understand that the recovery can be increased by making the time for discharging longer. Dissipation at resistive elements are shown in black solid color for adiabatic and dotted for CMOS step voltage. In CMOS, half amount of energy is dissipated during pull up and another half during pull down. While in adiabatic, by increasing the tau, we can reduce the dissipation at resistive elements. From this graph too, I understand that dissipation can be reduced by reducing load capacitance and voltage supplied.
The common techniques used in adiabatic circuits are slowing down the energy transfer by increasing tau. As the result, current flow is reduced. The next technique is the recovering of energy from logic. The important aspect of adiabatic design is that the voltage between current carrying electrodes must be zero when the transistor switched on. Besides, the conductor coupling between load capacitor and driver must exist at any time too. The circuit conditions are : clocked AC power supply with the height of Vdd. GND of CMOS terminal connected to inverted AC power supply and diodes are mainly used for charging and recycling of charges.
So, how low-power is gained in adiabatic circuits. First, during adiabatic switching, all the nodes are charged or discharged at a constant current. Then, from the energy dissipation equation here, when tau is long the dissipation is nearly zero.
In adiabatic logic, we can categorize them into asymptotically (complete) and quasi (incomplete) adiabatic logic. For asymptotically, Based on the method to create three states which are released, zero and unity, we can classified them into differential operation and split-level pulse driving. As for the quasi adiabatic we can further divide it according to static or dynamic. The conventional adiabatic circuits are categorized accordingly here. This is my proposed 2PASCL circuit.
Before ending chapter 2, I have done a power dissipation simulation from the equation here and compared the conventional adiabatic inverters which are easily derived from CMOS at transition frequency of 1 to 100 MHz. My proposed two phase clocked adiabatic static CMOS logic, 2PASCL shows a little higher dissipation compared to 1n1p slp and 1n1p quasi. However 1n1p circuits cannot be used as pipelining.
2PASCL was first introduced in the Journal of Semiconductor Technology and Science last year. This is the inverter circuit of my 2PASCL. It is powered by the split level sinusoidal V-phi and Vphi- as in these equations. Simulation is carried out using standard 0.18u CMOS technology. The energy dissipation per cycle is measured by E2-E1. EI is the energy injected to the circuit and ER is the energy received. The difference of 2PASCL as compared to other adiabatic circuits is that no diode is used at the charging path, therefore the logic swing can be increased and power dissipation can be reduced. ITC-CSCC 2010 2010
The circuit operation is shown here. During evaluation mode, when phi swings up and phi- swings down, and M2 transistor is ON, CL is charged. When output is High and M1 is ON, discharging occurs. During hold mode, there is no transition.
I have also done analytical study on the power dissipation of 2PASCL according to equation here. The parameters used are 0.01 pF CL, Vp threshold -0.58, Vn threshold 0.24, Vp-p as 0.9 V. n is the number of power supply, xi is the constant shape factor where for sine shaped current, it is 1.23. This is the power dissipation axis and this is transition frequency. The result using triangle waveforms is plotted here. In this graph, I manage to achieve the almost identical result of triangle plus shape factor to the results in the simulations.
From the SPICE simulation too, the comparison between CMOS and 2PASCL is carried out. The first graph is the input, next is the power supply clock and this is the output waveforms. The final graph demonstrates the energy supplied and energy dissipation in 2PASCL and CMOS. Here, we can clearly see the energy recovery phenomenon of 2PASCL.
Next, by using the output waveforms and energy dissipations of 2 different nMOS diodes, I managed to figure out the equivalent circuit of 2PASCL inverter. This circuit, the nMOS diode is using W/L of 40/40u and here it is 0.6/0.18u.
These are the fundamental logics of 2PASCL NOT, NOR, NAND and XOR. As the power dissipation of XOR is the highest, I have done further evaluation to select the best performance 2PASCL XOR.
In these screening, I evaluate by simulation the power dissipation and the output waveforms of these 4 designs.
On the basis of the evaluation, I found that 4 th design exhibits the least glitch output. Furthermore, compared to others, the no. of gates is the least. And produce the smallest power dissipation. Therefore 4 th design is selected for 2Pascl XOR.
This slide is the power dissipation comparison of the final fundamental logic of 2PASCL 4-inverter chain, NAND, XOR and NOR to CMOS. All show significant lower dissipation compared to CMOS at 1 to 100 MHz. I also see that the higher the frequency, the bigger the difference.
The overview, I will begin with the introduction, then CMOS vis-à-vis adiabatic circuit, 2input 2PASCL XOR evaluation, 4x4-bit array 2PASCL multiplier and I will conclude my presentation with the summary.
Application circuits using 2PASCL topology are 4-bit 2PASCL Ripple carry adder and 4x4-bit 2PASCL multiplier. We run for the functionality check and evaluate their energy dissipation compared to CMOS.
This is the evaluated 4-bit ripple carry adder using 2PASCL topology which consist of 4 full adders. The 4-bit RCA SPICE diagram which simulated utilizing 0.18um CMOS technology is shown here.
The input, power clocks and the output achieved from the simulation are shown here. The circuit is functioning correctly and the average power dissipation reduction is 35%.
This is the block diagram of 4x4 bit 2PASCL multiplier, which consist of 16 ANDs, 4 HAs, 8 FAs land 8 Dynamic flip flop at the outputs. The input a0-a3 and b0-b3.
The simulation results using 1.2 um CMOS technology demonstrate that the circuit is functioning accordingly.
Using 1.2 um technology simulation, for 4x4 bit 2PASCL multiplier, I have reduced 55% of power dissipation compared to CMOS of the same W/L, at the transition frequency of 1 to 12 MHz. Signal degradation occurs for more than 12 MHz. This is due to the charging time ,T, which is much slower than conventional CMOS. T is also proportional to RCL i.e. the longer the path, the larger T is needed.
These are the photo of my layout design of fundamental logic gates of 2PASCL, D-flip flop, 1-bit half adder and 1-bit full adder .
This slide shows the complete design of the 2pascl multiplier.
The chip is then fabricated at ON semiconductor using motorola’s 80 input / output 2.3x2.3cm Quad flat package
This slides shows my 4x4 bit 2PASCL multiplier chip. The chip summary is as this.
This slide demonstrates how I test the chip using DUT board and case.
The test equipment consist of 3 signal generators for input, voltage clocks and d-flip flop signal, DC voltage source and 1 4-channel oscilloscope.
The measurement test results started by examining the functionality of the 4x4bit 2PASCL multiplier at 1 MHz. The input of a0 until a3 and b0 until b3 are connected together. Therefore we have the 8 bit of high and 8 bit of low here. The results are divided into signal without Dflipflop and signals through the flipflops. The output signals using flipflops shows a significant better results.
In this slide, the power dissipation of 2PASCL multiplier is compared by simulation to CMOS and 2PADCL multiplier. From the transition frequency of 50 kHz to 5 MHz, 2PASCL topology reduced 77% of the power dissipated by CMOS and 55% of the 2PADCL . On the chip measurement results, 2PASCL demonstrate 55% reduction compare to 2PADCL. By the trend in the simulation, I can expect that CMOS has 77% more than my 2PASCL. By the way, the difference for the simulation and the actual measurement are due to wire resistance, parasitic capacitance and the transistor parameter.
As the conclusion
1. Two-Phase Clocked Adiabatic Static CMOS Logic: Analysis, Application and LSI Implementation Nazrul Anuar Bin Nayan Sekine and Takahashi Lab., Electronics and Information System Division Graduate School of Engineering Gifu University
2. <ul><li>Introduction </li></ul><ul><li>Principle of Adiabatic </li></ul><ul><li>Two-Phase Clocked Adiabatic </li></ul><ul><li>Static CMOS Logic (2PASCL) </li></ul><ul><li>Application Circuits </li></ul><ul><li>LSI Implementation </li></ul><ul><li>Summary and Future Works </li></ul>Slide
3. Slide <ul><li>Introduction </li></ul><ul><li>Principle of Adiabatic </li></ul><ul><li>Two-Phase Clocked Adiabatic </li></ul><ul><li>Static CMOS Logic (2PASCL) </li></ul><ul><li>Application Circuits </li></ul><ul><li>LSI Implementation of 4x4-Bit Multiplier </li></ul><ul><li>Conclusion and Future Works </li></ul>
4. Designer’s dream 1. Portable –increase battery life continuously 2. High-end – avoid cooling packages and reliability issue due to power Slide Chapter 1 Introduction
5. <ul><li>At circuit design level </li></ul><ul><ul><li>Power down the functional blocks </li></ul></ul><ul><ul><li>Minimize sequential elements </li></ul></ul><ul><ul><li>Downsize all non-critical path circuits </li></ul></ul><ul><ul><li>Reduce loading on the clock </li></ul></ul><ul><ul><li>Parallelism </li></ul></ul><ul><li>To solve dynamic power (drawback: static power) </li></ul><ul><ul><li>Process shrink </li></ul></ul><ul><ul><li>Voltage scaling </li></ul></ul><ul><ul><li>Transistor sizing </li></ul></ul><ul><li>To solve dynamic power (less static power) </li></ul><ul><ul><li>Adiabatic (switching) circuits </li></ul></ul>Slide Chapter 1 Introduction
6. Slide Chapter 1 Introduction Two-phase Clocked Adiabatic Static CMOS Logic (2PASCL) Using adiabatic switching Reduce current flow
7. Slide charismathics.com topnews.in Smart cards RFID nec.co.jp Sensors nextbigfuture.com Target: Low power, low frequency devices Chapter 1 Introduction
8. Static (leakage) ~10% Short circuit 10~20% Dynamic 70~80% (>0.18 m tech.) Abdollahi, A., Fallah, F., Pedram, M.: Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control. IEEE Transactions on VLSI Systems 12 (2), 140–154 (2004) Slide Chapter 1 Introduction Adiabatic switching --Technology to reduce dynamic power
9. CMOS and its equivalent circuit V dd and V ss of CMOS V dd V ss Slide Chapter 2 Principle of Adiabatic e n (t)
10. Slide Chapter 2 Principle of Adiabatic MOS R N MOS R 1 Pull-up network Pull-up network Pull-down network Pull-down network 0.18 process 1.2 process Pull-up network 10 kOhm 3.8 kOhm Pull-down network 4 kOhm 2.2 kOhm
11. Charge transfer without generating heat. V and V - of adiabatic circuit. V Slide Chapter 2 Principle of Adiabatic V w r : Energy dissipated at R
12. Adiabatic charging/discharging reduce the amount of current flow in the circuit The energy recovery phenomenon is demonstrated in w p ramped voltage supply Slide Chapter 2 Principle of Adiabatic w p : Supplied energy at P w C : Energy accumulated at C Pull up Pull down Pull up Pull down
13. <ul><li>slow down energy transfer. ( ) </li></ul><ul><li>Reduce the current flow through transistor </li></ul><ul><li>recovering energy from logic (charge recycling) </li></ul>Slide Chapter 2 Principle of Adiabatic <ul><li>Clocked AC power supply (height V dd ) </li></ul><ul><li>GND of CMOS connected to AC power </li></ul><ul><li>Diode s used mainly for recycling charges </li></ul>Technique <ul><li>Voltage between current carrying electrodes -> zero when transistor switch on . </li></ul><ul><li>Conductor coupling between load capacitor and driver must exis t at any time. charges </li></ul>Requirement Condition
14. <ul><li>During adiabatic switching, all the nodes are charged or discharged at constant current. </li></ul><ul><li>If the time for the driving voltage to change from 0 V to Vdd , τ is long, power dissipation is nearly zero . </li></ul>Slide Chapter 2 Principle of Adiabatic
15. 2n2p-2n Method used to create three states; (released, zero, unity) 1n1p The approach 1n1p 2n2n2p ECRL ADL ADCL 2PADCL HCnMOS 2n-2n2D Slide Chapter 2 Principle of Adiabatic (2PASCL) Adiabatic logic dynamic static Differential Operation Quasi Asymptotically Split-level pulse driving
16. Slide Chapter 2 Principle of Adiabatic Adiabatic inverters which are easily derived from CMOS T: period of primary signal N: no. of power supply V P & I P : voltage & current supply
17. Slide <ul><li>Introduction </li></ul><ul><li>Principle of Adiabatic </li></ul><ul><li>Two-Phase Clocked Adiabatic </li></ul><ul><li>Static CMOS Logic (2PASCL) </li></ul><ul><li>Application Circuits </li></ul><ul><li>LSI Implementation of 4x4-Bit Multiplier </li></ul><ul><li>Conclusion and Future Works </li></ul>
18. <ul><li>Inverter circuit and the waveforms, simulation using 0.18 m CMOS process </li></ul>Nazrul Anuar , Y. Takahashi, T. Sekine, “Two phase clocked adiabatic static CMOS logic and its logic family,” J. Semiconductor Technology and Science , vol. 10, no. 1, pp. 1–10, Mar. 2010. E i : Energy injected to the circuit E r : Energy received (recovery) 0.6 / 0.18 0.6 / 0.18 0.6 / 0.18 40 / 40 Split level sinusoidal to reduce the voltage potential of logic while maintaining the Vp-p Slide Chapter 3 2PASCL Diodes eliminated at the charging path to increase the amplitude and reduce dissipated energy
19. <ul><li>1. Evaluation Mode </li></ul><ul><li>V Y LOW - M2 ON C L is charges; output HIGH ( ). </li></ul><ul><li>V Y HIGH – M1 ON discharging via M1 & M4; </li></ul><ul><ul><ul><li>output LOW ( ). </li></ul></ul></ul><ul><li>2. Hold Mode </li></ul><ul><ul><li>V Y LOW - M2 ON no transition occurs; Y, as previous state. </li></ul></ul>V X V Y V V Slide Chapter 3 2PASCL Evaluation and Hold Mode
20. Slide <ul><li>n : number of power supply, </li></ul><ul><li>: constant shape factor </li></ul><ul><li>( for sine-shaped current), </li></ul><ul><li>T i: period for one cycle. </li></ul>C L =0.01 pF, V tp = – 0.58 V, V tn =0.24 V, V p− p = 0.9 V Power dissipation without shape factor (theory) Energy dissipation for triangle Chapter 3 2PASCL
27. Slide <ul><li>Introduction </li></ul><ul><li>Principle of Adiabatic </li></ul><ul><li>Two-Phase Clocked Adiabatic </li></ul><ul><li>Static CMOS Logic (2PASCL) </li></ul><ul><li>Application Circuits </li></ul><ul><li>LSI Implementation of 4x4-Bit Multiplier </li></ul><ul><li>Conclusion and Future Works </li></ul>
28. <ul><li>Objectives To evaluate the functionality of 4-bit 2PASCL Ripple Carry Adder , and 4x4-bit 2PASCL Multiplier which has long propagation path. To evaluate their energy dissipation compared to CMOS. </li></ul>Slide Chapter 4 Application Circuits
38. Tech. 1.2 μm CMOS 2-metal, 2-poly Power Voltage: 5.0 V Core Size : 1354 (W) × 997 (H) μm2 No. of transistors : 992 Dynamic Operating : Frequency 50 kHz – 5 MHz Dynamic Power Dissipation: 5.8 mW @ 5 MHz mulitiplier 4-inverter chain Slide Chapter 5 LSI Implementation
39. Slide Chapter 5 LSI Implementation
40. Measurement equipment to examine the functionality of 4x4-bit array 2PASCL Multiplier Slide Chapter 5 LSI Implementation
41. Measurement result to examine the functionality of 4x4-bit array 2PASCL Multiplier @ 1 MHz Slide Chapter 5 LSI Implementation (a) Output signals without D-Flipflop (b) Output signals with D-Flip flop 1 1 1 1 0 0 0 0 1 (1111) 2 X (1111) 2 = (11100001) 2
42. Slide Chapter 5 LSI Implementation
43. Slide <ul><li>Introduction </li></ul><ul><li>Principle of Adiabatic </li></ul><ul><li>Two-Phase Clocked Adiabatic </li></ul><ul><li>Static CMOS Logic (2PASCL) </li></ul><ul><li>Application Circuits </li></ul><ul><li>LSI Implementation of 4x4-Bit Multiplier </li></ul><ul><li>Summary and Future Works </li></ul>
44. <ul><li>From simulation results, 4-bit 2PASCL ripple carry adder (RCA) and 4x4-bit 2PASCL multiplier dissipates 35% and 77% lower power than CMOS respectively. </li></ul><ul><li>As for the measurement results, compared to the 2PADCL multiplier, the 2PASCL multiplier reduces the power dissipation by 55%. </li></ul><ul><li>Dynamic power dissipation was reduced using 2PASCL topology and it is advantageous for low-power digital application </li></ul>Slide Chapter 5 Conclusion & Future Works
45. <ul><ul><li>Chip design and fabrication using 45nm process to focus on the leakage power dissipation. </li></ul></ul><ul><ul><li>Smart card prototype as the application. </li></ul></ul><ul><ul><li>Prototype RISC CPU using 0.18 m 2PASCL topology which targeting 0.23 mW/MHz. </li></ul></ul>Slide Chapter 5 Conclusion & Future Works