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Fpga technology

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  • 1. FPGA Technology Overview Carl Lebsack* Some slides are from the “Programmable Logic” lecture slides by Dr. Morris Chang
  • 2. What’s an FPGA?FPGA – Field Programmable Gate Array
  • 3. Logic Standard ASIC LogicProgrammable Gate Cell-Based Full customLogic Devices Arrays ICs ICs SPLDs CPLDs FPGAs FPICs
  • 4. How do you make a“Programmable” circuit?One time programmable  Fuses (destroy internal links with current)  Anti-fuses (grow internal links)  PROMReprogrammable }  EPROM  EEPROM non-volatile  Flash  SRAM - volatile
  • 5. How do you program an FPGA?Create a circuit design Graphic circuit tool Verilog VHDL AHDLCompile the design for the selecteddeviceDownload the compiled configuration
  • 6. FPGAs offer manyadvantages over ASICsSmall development overheadNo NRE (non-recurring engineering)costsQuick time to marketNo minimum quantity orderReprogrammable
  • 7. What are the Guts of an FPGA?Basic Components LUT (look-up-table) Flip-Flops Multiplexors I/O Blocks Programmable switching matrices Interconnect Clocks
  • 8. Xilinx FPGA Structure Configurable Logic Blocks I/O Blocks Programmable Interconnects
  • 9. CMOS SRAM Cell QRead orWrite Q Data
  • 10. 3-LUT config_outinput[0:2] 0 1 1 0 output 1 0 0 clock 1config_in
  • 11. 2 Slice CLB
  • 12. LE
  • 13. LAB
  • 14. Dir ect Connections DI CE A DI CE A B X B X C CLB 0 C CLB1 K Y K Y E D R E D RHor iz ontalLong Line Switching MatrixGeneralPurpose Line s DI CE A DI CE A B X B X C CLB2 C CLB3 K Y K Y E D R E D R Globa l Vertic al Long Line
  • 15. IOB
  • 16. More GutsAdditional components RAM blocks Dedicated multipliers Tri-state buffers Transceivers Processor cores DSP blocks
  • 17. Dedicated Arithmetic Structures in FPGAs QuickLogicAltera Xilinx
  • 18. Power PC in Virtex-II Pro• Embedded 300+ MHz Harvard Architecture Core• Low Power Consumption: 0.9 mW/MHz• Five-Stage Data Path Pipeline• Hardware Multiply/Divide Unit• Thirty-Two 32-bit General Purpose Registers• 16 KB Two-Way Set-Associative Instruction Cache• 16 KB Two-Way Set-Associative Data Cache• Memory Management Unit (MMU) - 64-entry unified Translation Look-aside Buffers (TLB) - Variable page sizes (1 KB to 16 MB)• Dedicated On-Chip Memory (OCM) Interface• Supports IBM CoreConnect™ Bus Architecture• Debug and Trace Support• Timer Facilities
  • 19. Excalibur Embedded Solution• Integrates Embedded Processors With Programmable Logic Device• Delivers System-on-a-Programmable-Chip (SOPC) ─ Programmable Flexibility • PLD Hardware • Embedded Software Excalibur ─ Compute Performance Memory Processor • High Performance Processor High • Data Path Hardware Performance I/O ─ Customer Configuration Logic • Microprocessor Peripherals • Hardware Logic Complete SOPC Solution ─ Faster Time-to-Market
  • 20. ARM in Excalibur• Industry-standard ARM922T 32-bit RISC processor core operating up to 200MHz ─ ARMv4T instruction set with Thumb extensions ─ Memory management unit (MMU) included for real-time operating systems (RTOS) support ─ Harvard cache architecture with 64-way set associative separate 8- Kbyte instruction and 8-Kbyte data caches• Embedded programmable on-chip peripherals ─ ETM9 embedded trace module to assistant software debugging ─ Flexible interrupt controller ─ Universal asynchronous receiver/transmitter (UART) ─ General-purpose timer ─ Watchdog timer
  • 21. Altera DSP-Block-Configuration Options and Features
  • 22. FPGAs come in a wide variety Numbers of subcomponents varies Special features vary Manufacturers use own terminologyXilinx Altera Slices/CLBs  LEs/LABs PowerPC cores  ARM cores/Softcores
  • 23. Stratix Device OverviewFeature EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80 EP1S120Logic Elements (LEs) 10,570 18,460 25,660 32,470 41,250 57,120 79,040 114,140M512 RAM Blocks 94 194 224 295 384 574 767 1,118( 512 Bits + Parity)M4K RAM Blocks 60 82 138 171 183 292 364 520(4 Kbits + Parity)M512 RAM Blocks 1 2 2 4 4 6 9 12(512 Kbits + Parity)Total RAM bits 920,448 1,669,248 1,944,576 3,317,184 3,423,744 5,215,104 7,427,520 10,118,016DSP Blocks 6 10 10 12 14 18 22 28Embedded Multipliers 48 80 80 96 112 144 176 224PLLS 6 6 6 10 12 12 12 12Maximum User I/O Pins 426 586 706 726 822 1,022 1,238 1,314Engineering Sample Use Use Now N/A Now N/A Now 2003Availability Production Production AprilProduction March March January Now Now Now 2003Device Availability 2003 2003 2003 2003
  • 24. FPGA DesignMain components are generally doneas custom designsLayout is very regular and automationcould assist in cell placement
  • 25. Stratix FPGA Layout
  • 26. PLD device density and VLSI technology year 1995 1996 1997 2000 2003 2004 ?Technology 0.6µ 0.35 µ 0.25 µ 0.18 µ 0.13 µ 0.07µ 100K LC* 8Mb RAMGate count 25K 100K 250K 1M 400 18X18 multipliers Transistor 3.5M 12M 23M 75M 430M 1B count *note: Xilinx Virtex-II Pro XC2VP100 (9/16/2003)
  • 27. More Informationwww.xilinx.comwww.altera.com