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Host Simulation
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Host Simulation



Developing embedded applications natively on Desktop computers

Developing embedded applications natively on Desktop computers



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Host Simulation Host Simulation Presentation Transcript

  • Developing embedded applications natively on desktop computers Pawankumar Hegde Organization Guide:G.D.Nagendra System Modeling and Simulation Texas Instruments India Dt:12/12/2007
  • Host Simulation
    • What it is ?
      • Host simulation is a methodology of creating a framework on host platforms to develop embedded applications which can supersede the traditional application development on system simulated platforms .Advantages of host simulation includes harnessing the power of the multi-GHz processors, utilization of host resources and ease of adopting the application in the native host environment.
  • Motivation
    • What is the problem?
      • The needs are:
        • Very high simulation performance.
        • Do not wait until IP specifications are available
        • Realization of a complete SOC platform .
        • Micro architectural details of the IP hard to obtain at early stages of SOC design phase.
        • These factors motivate a need for a very high abstraction simulation framework.
  • Prior Work in this area 1.What exists in the literature in this area?
    • Building Fast and Accurate SW Simulation Models Based on Hardware Abstraction Layer and Simulation Environment Abstraction Layer
    • Introduction to Hardware Abstraction Layers for SoC
  • 3.What is missing?
    • Following are the gaps which needs to be filled to achieve host simulation
    • Realization of a complete chip to execute a full fledged SOC application on the host system – Upcoming chip architectures are complex which are heterogeneous multi-core processors coupled with numerous peripherals. Hence hand-coded simulation of such architectures to functionally validate an application currently consumes considerable amount of time.
    • Usage of third party libraries built for a SOC device on host system – Existence of multiple software layers above the hardware layers makes it difficult to achieve unified hardware abstraction layer.(1)
    • Consideration of source files written in target assembly language during software development.
    • Consideration of the compiler options to be appropriately realized on the host system.
  • 2.What has TI done in this area?
    • A prototype for one of the components present in SOC has been modeled using the principles of host simulation.EDMAv.3 present in the DaVinci DSP and functioning as DMA provides CSL(Chip support Libraries) APIs to program its registers and be used in the application. Re-implementing the CSL APIs for EDMA on the host translated the application development using EDMA to be possible on the host system debuggers.
  • Proposed Approach: What do we want do and why? :
    • Motivation
    • The complexity of SOCs are increasing, comprising of multiple cores along with numerous peripherals. Validation of a chip architecture at such a large order through traditional simulation and to simulate it on desktop computers is becoming more and more challenging.
        • Time to model numerous IPs of SOC to work in the simulation environment.
        • Integration of numerous IPs to create a SOC functional simulator is not lightweight and holds up the performance.
  • Motivation(contd)….
    • Functional validation provides the initial conformance about the application requirements for a given chip architecture specification. Functional correctness of the application at nascent stages through simulation is one of the key phases not only to refine the chip specifications, but also aids in developing the complete software for the embedded system much before the silicon samples arrive.
    The time between traditional(hand-written) simulation and functional validation of the software increases further as the complexity of SOCs increases.This time gap should not be allowed to increase. cycles of revisions Specification Simulation Functional Validation Spec Revision Samples Arrival Final validation Ready-to-market
  • Motivation(contd)….
    • Time to confirm the functional validation is an important requirement. In the existing scenario, construction of a functional model based simulator encounters following time consuming factors
      • IP specifications of all the peripherals are needed to construct the functional models of such IPs.
      • A lot of decision making criteria is required in considering the level of micro-architectural details to be used for constructing the functional model for the simulator.
      • Construction of such functional model simulator also demands high simulation performance.
  • b. Uniqueness (not done in Prior work section)
      • 1. Virtualization of an entire system on chip(SOC) is realized on a host debugger, even without simulating a single piece of IP model.
    Traditional simulation implements only a subset of the architecture
      • 2. Usage of host device drivers like USB, network system can be put into use in the application context in real time.
    Peripherals Peripherals Peripherals Peripherals Ethernet Timer Video Peripheral Video Port DDR USB JTAG PLL CPU CACHE CO-PROCESSORS BUS DMA
  • Technical elaboration:
    • Details of proposed approach.
    • Software development over TI DSPs adopts a layered approach .
    • Application layer executes on the DSPs by pervading through layers such as codecs, device drivers, libraries.
    • The common layer existing just over the target in the case of TI DSP software development refers to CSL(chip support libraries).
    • This common layer existing over the device can be used to port the entire DSP software development on the host.
    • DSP Software development and validation then can be realized on the host by identifying this common layer and structuring such an identified common layer to the host system.
  • How should it look? Application S/w + OS + drivers HW Libraries APIs(eg:-CSL) Application S/w + OS + drivers Traditional simulation App written on a Pentium machine debugger Simulator IP 1 IP 2 IP k Core 1 Core 2 Core n Use_USB() Codec_decode() Connect_network()
  • Expected benefits
    • Reducing time to market for Software – Validation of the software application for a given SOC can be achieved at a very early stage by the following factors
      • Familiarity with the host system debuggers facilitates speedy completion of the software development.
      • Execution on host machine increases the performance of the application per se compared to execution on hand written simulators.
      • More importantly , realization of the complete application software that has been developed can be accomplished, because
        • Complete spec details of an IP is not required.
        • Usage of host resources like USB, ethernet, video terminal can be utilized to behave as the board components if necessary.
  • References/Related Literature
    • A framework for developing embedded applications on host platform, Swaminathan Ramachandran, G.D.Nagendra , TIITC 2007