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VLSI Based Robust Router Architecture

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  • 1. VLSI Based Robust Router Architecture1.Channamallikarjuna Mattihalli 2.Suprith Ron 3.Naveen KollaDepartment of Electrical and Computer EngineeringDebre Berhan University, Ethiopiackmattihalli@gmail.com, suprit.ron@gmail.com, naveenkolla@yahoo.comAbstract - In his paper we attempt to give a networkingsolution by applying VLSI architecture techniques torouter design for networking systems to provide intelligentcontrol over the network. Networking routers today havelimited input/output configurations, which we attempt toovercome by adopting bridging loops to reduce the latencyand security concerns. Other techniques we exploreinclude the use of multiple protocols. We attempt toovercome the security and latency issues with protocolswitching technique embedded in the router engine itself.The approach is based on hardware coding to reduce theimpact of latency issues as the hardware itself is designedaccording to the need. We attempt to provide amultipurpose networking router by means of Verilog code,thus we can maintain the same switching speed with moresecurity as we embed the packet storage buffer on chip andgenerate the code as a self-independent VLSI Basedrouter. Our main focus is the implementation of hardwareIP router. The approach enables the router to processmultiple incoming IP packets with different versions ofprotocols simultaneously, e.g. for IPv4 and IPv6. Theapproach will results in increased switching speed ofrouting per packet for both current trend protocols, whichwe believe would result in considerable enhancement innetworking systems.Keywords: Robust Router, packets, FPGA, RTL, IPI. INTRODUCTIONOur approach here is to design a variable hardwarerouter code by using Verilog and the same to beimplemented for the SOC (System On Chip) level router.In this paper we are making a VLSI design for theimplementation at the synthesizable level the same can befurther enhanced to SOC level, but our main aim islimited to the NetList generation level which would givethe result prediction and workable module vision. Ourfocus being in this is to make this router as much variableas we can which will give the robustness for the design tobe called even as a Robust Router in which we can makethe same router to not only go for N number ofconnections but also to detect all variety of packets androute the same. To do so we have to add the code withspecific case’s for every type of packets we want to add toour router to route, with this paper of hardware code ourapproach is to get the basic packets routing with multipleprotocols starting with the IPv4 and IPv6.II. LITERATURE SURVEYIn this we are comparing the existing generic routerarchitecture and our new robust router architecture. Thiswill give the difference in the designing and would reflectour paper enhancements that we are upgrading in ourrobust router paper.A. Generic Router ArchitectureFigure 1 Generic architectureIn the architecture we can look that the genericarchitecture is processing a single packet of a specificprotocol at a given time and the output queue buffer alsoone for one egress channel ring by which there is the!000111!      TTThhhiiirrrddd      IIInnnttteeerrrnnnaaatttiiiooonnnaaalll      CCCooonnnfffeeerrreeennnccceee      ooonnn      IIInnnttteeelllllliiigggeeennnttt      SSSyyysssttteeemmmsss      MMMooodddeeelllllliiinnnggg      aaannnddd      SSSiiimmmuuulllaaatttiiiooonnn!777888-­-­-000-­-­-777666!555-­-­-444666666888-­-­-111///111222      $$$222666...000000      ©©©      222000111222      IIIEEEEEEEEEDDDOOOIII      111000...111111000!///IIISSSMMMSSS...222000111222...333222444333
  • 2. overloading of the queue buffer and will result in thecongestion. The congestion flow is as shown below.Figure 2 Congestion flowIII. A NEW ROBUST ROUTER ARCHITECTUREThe architecture of robust router is totally based onthe Verilog code which would enable our design in theimplementation of parallel packet processing for Nnumber of channels. This intern enables the multi packetprocessing at the same time. With the Verilog code beingthe base of design we have an option for the addition ofprotocol case and respective look-up table makes us gofor the Multi-protocol processing at the same time. Bywhich we are unable to provide the multi-packet multi-protocol routing at the same time with same speed.Figure 3 Multi-protocal Multi packet processing at a treeWhile designing the robust router a special concern iskept in the mind of the switching speed issue to give themaximum speed with parallelism being added.The egress output buffer queuing problem was alsosolved by providing a separate queue for every ingresschannel in the egress channel with N vertical queue bywhich we can avoid the congestion to a remarkable levelwhich is as shown below.Figure 4 Congestion flow with vertical queueThe size issue is another special feature of our robustrouter which makes our robust router a unique system. Asdiscussed earlier in the paper we are trying to make theRobust router on to the chip level design so we furtheradvance it to the level of Ethernet based router which willmake the router to be implemented on the standalonesystems, which will be a revolutionary enhancement insize matter from room full of router to just the PCI slotoperating Router and will make network work morefaster. It looks something like this below.Generally, the router can be interfaced with ‘N’number of I/O devices. Block diagram given below.Figure 5 Block diagramThe paper design has the following modules.444444
  • 3. A.Input Interface BlockThis block is mainly responsible for receiving theincoming IP packets over multiple input channels. Thisblock asserts the necessary response signals in order tocommunicate with the IP packet driver modules. Afterreceiving the IP packets, this block forward the same tothe Ingress Block for the further process. This blockforwards the same to packet store block as well as parserblock.B.Packet Store BlockThis is responsible for storing the error free receivedpackets. This module receives the packet contents fromIngress block and dispatches the same based on therequest from Egress block.C.Parser BlockThis block is mainly responsible for parsing thecomplete packet into multiple set of data according to itsfield. The parsed contents will be inputted to the filerblock.The above three blocks are merged all together asIIB in code to single file.D. Filer BlockThis block is responsible for selecting the egress ring.The block receives the parsed data from the parser block.The parsed data will be forwarded to the filer table. Inresponse to this, the filer table provides the output ringnumber. Then, the received output from the filer table willbe forwarded to the egress block.E.Filer TableIt is a user configurable table. This table contains aset of data in its each slot, against which the data sent bythe filer block will be compared. If the filer block inputteddata matches with the data of any slot of filer table, thenthat slot’s data will be used as egress ring through whichreceived packet will be forwarded.F.Egress BlockThis block receives the data from filer block as egressring number through which the received packet shall beforwarded. Upon receiving the egress ring number, thisblock initiates the communication with packet store blockto fetch the packet to be forwarded. Then, the fetched IPpacket will be forwarded to the output interface blockwith the output channel details, over which the packet hasto be transmitted.G. Output Interface BlockUpon receiving the packet with output port detailsfrom the egress block, this block forwards the IP packetover mentioned output channel. This block is alsoresponsible for asserting all the necessary handshakingsignals for the receiving device while transmitting thepackets. The Egress Block and Output Interface Block aremerged together in code as single file.Figure 6 Forwarding IP packetIV. SYSTEM FLOW DIAGRAMThe system flow diagram is as shown below whichmakes us to understand the flow of the signals through thesystem from each block by block and transaction carriedbetween the blocks to accomplish the task of the robustrouter. The flow diagram described here is a brief one,which helps us to understand the flow of every block.Every block have the state machine cycle included inthem to enhance the system logical transaction to the levelof parallelism. The flow diagram is as shown in Figure 7below.First the packet is received from the ingress channelring to the input interface block the packet is parsed todata packet and header packet, the data packet is stored inthe parser queue and the header is sent to the filer block.The flier block then checks weather the packet is IPv4 orIPv6 and accordingly send the request to the filer table torouter the packet to required destination. The filer tablecross verifies the egress ring channel with it Dest-IPaddress and send the egress ring ID to the filer block. The444555
  • 4. filer block send and enables the particular egress ring inegress blocks and gives the command to the particularegress ring in egress block. Then in egress block thestored data packet in the parser queue is added back withheader and is sent out with the specified egress ringchannel. In this way the every packet is processed androuted in robust router.Figure 7 System flow diagramV. SIMULATION AND DISCUSSIONA.Net List of the Robust RouterThe Net List is RTL level of the robust router system,which is syntasizable and can be extracted on the Xilinxtool. By which we can get preface look of the system anda transition from the frontend of the VLSI designing tobackend of the VLSI designing. Which means the samecan run on FPGA kit and test its robustness and errors ofthe system can be debugged before it is taken to SOCLevel and to Fab-Labs.The snap below is the Pin configuration of theproposed Robust Router.Figure 8 Net ListThe NetList level can further go after I/O Padding getthe exact pin configuration which can be derivedaccordingly but will be similar one.The Snap below is the Top level system view of thesystem at the RTL.Figure 9 View of the system at the RTLB.SOC DesigningThe further movements of the VLSI Designing willrequire the sharp knowledge of the VLSI backenddesigning and can be fabricated at the 45 nano technologyusing the Cadence Encounter Tool which will enable us totake the system to SOC level the steps are as shownbelow.444666
  • 5. Figure 10 System to SOC level the stepsThe RTL level of design which we get from the NetList of the system will have gate delay, propagation delayand wire delays included in them. These are all calculatedand made into an optimization level. Then the design isfixed into LUT’S and the mapped between the LUT’Sfurther the placement of the LUT’S are prissily donekeeping mind the power utilization and the delaycalculated earlier. Then the routing is done between theCLB’S. Further the bit-stream is generated to test thesystem and verification done across the Net List output toget the exact design. Then the system design is maskedand made to the GDSSI Level further to be sent on to theFab-Labs for fabrication.C. Design under TestThe design under test [DUT] is made to test thesystem robustness under different cases. The DUTarchitecture includes the Test case which will define thetest. The input driver block will generate the test inputsignals for the system testing. The input and outputtransacted will make the system get the input and outputaccording to the system core requirement. The input andout monitor are placed to compare the system testing. Atlast the Response checker is to give the system testingpass or fail. The DUT is as shown below.Figure 11 DUT architectureFor the testing of the robustness here we are mixingtheIPv4 and IPv6 packets and we testing the system indifferent cases.VI. CONCLUSIONSWe summarise the advantages and applicationsbelow.A. Advantages• General purpose router• Router hardware code is variable• High switching speed with any no. of Io pinconnection• More secured• Robust router can handle all type of packets(Implemented on IPv4 and IPv6)B. Application• Can be used as public internetworking router• Can be used as corporate router• Software company private router (client to client,developer to client)• Router for networking research• In other words one point networking solution444777
  • 6. B. System Test AnalysisNumber of gates :- 59855Total Run time:- 9.018 nsSwitching speed:- 662.5 TbpsSystem Frequency:- 0.11 GHzCan be fabricated:- by 45 nano technology with CadenceEncounter tool( cost 12000$)In this paper the code given in the output for IPv4 andIPv6 packets is put in the router at the same time. TheRobust Router will route both packets at the same time atthe same speed. The Robustness is simulated with Model-Sim Tool with different Test Cases and the same code’sNetList is extracted with Xilinx Tool for the synthesizablecode. The same can be taken to the SOC (System on chip)level with Cadences Encounter Tool.• The same Verilog code design can be taken to theimplementation of MPLS (Multi-Protocol LabelSwitching).• The some code design can be taken to the SOC(System on chip) level and can be implemented as theEthernet Standalone System Router.• The same code can be made variable with TCP andUDP Protocols.REFERENCES[1] Y. Katsube, K. Nagami, and H. Esaki, “Toshiba’s RouterArchitecture Extensions for ATM: Overview,” IETF RFC2098, April 1997.[2] Y. Rekhter, B. Davie, D. Katz, E. Rosen, and G. Swallow,“Cisco Systems’ Tag Switching Architecture Overview,”IETF RFC 2105, Feb. 1997. Amir.Palnitkar. 2ndEdition[3] J. Moy, OSPF: Anatomy of an Internet Routing Protocol,1998[4] Tobias Bjerregaard and Shankar Mahadevan. A survey ofresearch and practices of network-on-chip. ACM Comput.Surv., 38(1):1, 2006.[5] Charles.H.Roth,Jr Digital System Design Using VHDL[6] Jenkins,jesse H.Designing with FPGAs and CPLDs[7] Abromovici,M,Breuer Digital System Testing and TestableDesign.[8] James Balfour and William J. Dally. Design tradeoffs fortiled cmp on-chip networks. In ICS ’06: Proceedings of the20th annual international conference on Supercomputing,pages 187–198, 2006.444888

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