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Viterbi based efficient test data compression
Viterbi based efficient test data compression
Viterbi based efficient test data compression
Viterbi based efficient test data compression
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Viterbi based efficient test data compression

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  • 1. Viterbi-Based Efficient Test Data Compression AIM: The main aim of the project is to design and implement “Viterbi-Based Efficient Test Data Compression”. ABSTRACT: This paper presents a Viterbi-based test compression algorithm/architecture that provides high encoding efficiency and scalability with respect to the number of test channels. The proposed scheme finds a set of compressed test vectors using the Viterbi algorithm instead of solving linear equations. By assigning a cost function to the branch metric of the Viterbi algorithm, an optimal compressed vector is selected among the possible solution set. This feature enables high flexibility to combine various test requirements such as low-power compression and/or improving capability to repeat test patterns. The proposed on chip de compressor follows the structure of Viterbi encoders which require only one input channel. Experimental results on test volume show improvement on all ISCAS89 benchmark circuits (19.32% reduction on the average) compared to previous test data compression architectures. The proposed scheme also yields efficient powerdissipation/volume tradeoff. Proposed method: At Present the viterbi decoder implemented in this project has a bit rate of 0.025. so due to this speed is limited . in the proposed method we can increae the speed by increasing bit rate upto 0.25. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 2. BLOCK DIAGRAM: Fig: Proposed test data compression architecture TOOLS: Xilinx 9.2ISE, Modelsim 6.4c. APPLICATION ADVANTAGES: V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 3.  By defining proper branch metrics, the proposed technique can include and optimize different test constraints, and selects a set of compressed vectors that has the best cost function among all possible sets.  The cost function can also be optimized by other algorithms, such as the maximum a posteriori algorithm also known as the Bahl–Cocke–Jelinek– Raviv algorithm.  The proposed architecture does not require special control signals or modification to the circuit under test. As a result, simple test interface of the proposed scheme significantly reduces the test cost. REFERENCES: • N. A. Touba, “Survey of test vector compression techniques,” IEEE Des. Test Comput., vol. 23, no. 4, pp. 294–303. • G. D. Forney, “The Viterbi algorithm,” Proc. IEEE, vol. 61, no. 3, pp. 268– 278. • B. Koenemann, “LFSR-coded test patterns for scan designs,” in Proc. Eur. Test Conf., 1991, pp. 237–242. • J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee, “Embedded deterministic test,” IEEE Trans. Comput.-Aided Des. Integr. Circuit Syst., vol. 23, no. 5, pp. 776–792. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 4. • K. J. Balakrishnan and N. A. Touba, “Improving linear test data compression,” IEEE Trans. Very Large Scale Integr. Syst., vol. 14, no. 11, pp. 1227–1237. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur

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