Novel chip last method for embedded actives in

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Novel chip last method for embedded actives in

  1. 1. IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 1, JANUARY 2012 63 Novel Chip-Last Method for Embedded Actives in Organic Packaging Substrates Baik-Woo Lee, Venky Sundaram, Scott Kennedy, Dirk Baars, and Rao Tummala, Fellow, IEEE Abstract— Embedded actives are to bury thinned active chips into package substrates, as opposed to surface mounted devices (SMDs), which can achieve smaller form factor, better electrical performance and higher functionality than the SMD technology. While many embedded actives have been explored so far, they are based on chip-first and -middle approaches, in which the active chips are embedded before and during the build-up processes of package substrates, respectively. The most concern with those two current approaches is the loss accumulation associated with the build-up layer processes carried out right on top of the embedded chips, which is highly likely to lose the embedded chips during their packaging process. The reworkability to replace the faulty chips embedded with good ones and thermal management of the embedded chips are also issues since the embedded chips are totally surrounded by hard-cured polymers. In this paper, chip-last embedded active has been proposed to address some of the issues that are reported in current chip-first and -middle approaches, in which chips are embedded after all the package substrate processes including the build-up layers are completed, just like conventional SMD packaging. In the chip-last approach, a cavity is introduced within the build-up layers of package substrate and a chip is directly embedded into the cavity. A first proto-type of the chip-last embedded active will be demonstrated by developing various cavity formation processes within the buildup layers and then embedding 100 µm thick chips into the defined cavities. Index Terms— Chip scale packaging, electronics packaging, embedded actives, flip-chip, organic laminate. I. I NTRODUCTION G REATLY increasing demand for highly integrated and microminiaturized convergent electronic systems require effective system integration solutions to incorporate the necessary technologies, including digital, analog, radio frequency (RF), optical and bio-sensing. System-on-package (SOP) concept has been a strong contender in facilitating the effective system integration, which realizes all the system functions on an ultraminiaturized, multi-functional, and high-performance Manuscript received February 17, 2011; revised July 2, 2011; accepted August 19, 2011. Date of publication November 29, 2011; date of current version January 5, 2012. This work was funded by the EMAP consortium members at Packaging Research Center, Georgia Institute of Technology, Atlanta. Recommended for publication by Associate Editor C. Gurumurthy upon evaluation of reviewers’ comments. B.-W. Lee is with Samsung Institute of Technology, Suwon 440-600, South Korea (e-mail: baikwoo@gmail.com). V. Sundaram and R. Tummala are with 3-D Systems Packaging Research Center, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332-0560 USA (e-mail: vsunda@ece.gatech.edu; rao.tummala@ece.gatech.edu). S. Kennedy and D. Baars are with the Rogers Corporation, Rogers, CT 06263 USA (e-mail: scott.kennedy@rogerscorporation.com; dirk.baars@rogerscorporation.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2011.2167013 package, by integrating both active and passive components into a single high-density package substrate [1]–[2]. Embedded actives, in which thinned active chips are directly buried into package substrates, not merely mounted on their surface, are of great interest for next generation advanced SOP. Currently, active chips can be embedded in many different ways within categories of chip-first and -middle, depending on the approaches involved. Although the first demonstration of chip-first embedded active technology dates back to 1975 [3], more recent chip-first embedded actives have been developed by General Electric [4], Intel [5], Fraunhofer [6], and others [7]–[11] since the early 1990s. In the chip-first embedded actives, chips are first buried into various types of organic core and then build-up layers, which are alternating layers of patterned metal forming signal or power/ground plane layers and organic dielectric to electrically isolate the metal layers, are disposed on top of the chips and the core. For the chip-middle embedded active, where chips are embedded in the middle of build-up layer processes, Shinko Electric Industries Co., Ltds approach is a representative example [12]. A chip is placed face down onto a build-up layer like the surface mount technology process and fully embedded after subsequent build-up layers. While current chip-first and chip-middle embedded active approaches offer many advantages such as small form factors, increased functionality, and better electrical performance, they also have a few drawbacks: 1) lower package process yields and higher costs; 2) poor reworkability; and 3) thermal management problems. To address some of these issues for chip-first and -middle embedded actives, we have proposed a chip-last approach for embedded actives, in which a cavity is formed to accommodate active integrated circuits within the build-up layers of package substrates and then a chip is embedded directly into the cavity with appropriate electrical interconnections to the build-up layers. In fact, chips are embedded after all substrate processes are finished. The chip-last approach for embedded actives thus offers many advantages over chip-first or -middle ones from the standpoints of process and yield, reworkability, and thermal management since its processes are more similar to conventional packaging processes. In this paper, an emphasis is especially put on the process development of cavity formation and chip assembly into the cavities for the first demonstration of chip-last embedded active. II. C HIP -L AST E MBEDDED ACTIVE Fig. 1 shows the schematic cross-section of the embedded actives by noble chip-last approach, which has been proposed 2156–3950/$26.00 © 2011 IEEE
  2. 2. 64 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 1, JANUARY 2012 Embedded Underfill inductor Embedded Embedded resistor chip Chip Solder Blind-via interconnects Fig. 1. Build-up dielectric Organic core Plated through holes Metal traces (a) Embedded capacitor Schematic of chip-last embedded actives and passives. by the authors at Packaging Research Center of Georgia Institute of Technology. The chip-last embedded active processes are realized on typical organic build-up package substrates, in which one or more of build-up layers are laminated on either side of a single- or multi-laminated core. The base core materials can be a glass-fiber reinforced epoxy resin like bismaleimide triazine (BT) or FR-4. The core has circuitry on its surface and plated through holes for connecting circuitry on one side of the core to the opposite side. The build-up layers are accomplished by repeating dielectric lamination and metallization processes on the core, as needed. Fig. 1 also shows that thin-film passive components such as capacitors, resistors, and inductors can be embedded during the buildup processes, enabling higher functionalized module package, even though it will not be demonstrated in this paper. In order to embed or bury active chips into the organic build-up package substrates, a cavity structure is introduced within the buildup layers during or after the build-up processes. This cavity structure is the unique aspect enabling the chip-last embedded actives. While the cavity is defined, the metal pads patterned on the core or inner build-up layers are exposed inside the cavity. Embedded chips are connected to the metal pads with various low-profile interconnect technologies including solder and metal pillar bumps, followed by filling with underfill and engineered adhesive materials. If needed, heat spreaders or sinkers can be placed on the exposed back side of chips. The chip-last approach for embedded actives offers many advantages over chip-first or -middle technologies from the standpoints of process yield, reworkability, and thermal management. 1) Lower loss accumulation and higher process yield are expected in the chip-last embedded actives because chips are embedded after all the package substrate processes are completed just like conventional surface mounted device packaging. The build-up layer processes that are carried out after chip embedding in chip-first and -middle embedded actives accumulate their process losses on the embedded chips, ultimately leading to losses of the chips. In addition, high-pressure build-up lamination processes on top of the embedded chips have been reported to induce chip cracking [13]. In our chiplast approach, no complex processing after chip embedding is needed that could otherwise damage the chip. 2) Defective chips can be replaced in the chip-last embedded actives if reworkable interconnects and appropriate selection of underfill and encapsulation materials are employed. 3) Because the backside of chip-last embedded active is exposed to air, many conventional thermal management solutions can be applied. (b) (c) (d) Fig. 2. Schematic process flow of photolithography defined cavity substrates. (a) Circuitized BT core. (b) Solder mask layer. (c) First cavity layer. (d) Second cavity layer. To realize these chip-last embedded actives, there are, however, some challenging issues like cavity formation, embedding of chip into the cavities and reworkable ultrathin interconnections with fatigue resistance. This paper focuses mainly on the cavity formation process and chip assembly into the cavity for the first prototype of chip-last embedded actives. III. C AVITY S UBSTRATES A. Fabrication of Cavity Substrates Three different kinds of cavity formation processes in packaging substrates are explored including photolithography, plasma-etching, and laser-drilling. All of these processes are based on micro-via formation processes, thereby enabling the use of existing equipments with well-verified materials and processes. 1) Photo-Cavity Substrates: Photolithography is expected to be among low-cost and mass cavity-generation processes. Photoimageable dielectric (PID) Probelec-81/7081 (Huntsmann–Vantico Inc.) was used for build-up dielectric layers and copper-clad BT of 500 µm thickness was used for cores. The Probelec dielectric materials were diluted to be 75% with propylene glycol methyl ether acetate. Fig. 2 shows the schematic cavity formation process flow through photolithography. First, the Cu-clad BT was curcuitized [Fig. 2(a)] and then the PID materials were spin-coated on the circuitized BT core for a solder mask layer. Then, the solder mask and vias opening needed were made through photolithography processes, comprising drying of coated PID materials, pattern exposure, post-baking, developing, and last curing. The overall
  3. 3. LEE et al.: NOVEL CHIP-LAST METHOD FOR EMBEDDED ACTIVES IN ORGANIC PACKAGING SUBSTRATES (a) (b) (c) (d) Fig. 3. Schematic process flow of plasma defined cavities. (a) Dielectric and metal mask layer lamination. (b) Metal mask patterning. (c) Plasma–etching. (d) Via metallization. photolithography process was conducted according to manufacturer’s process recommendation. The thickness of solder mask layer coated could be controlled by the viscosity, spincoating speed, and number of spin-coatings of PID materials. The solder mask layer here was 25 µm in thickness. Once via and solder mask openings were finished, the open vias were metallized by conventional semi-additive Cu plating (SAP) [Fig. 2(b)]. The metal layers were 10 µm thick. On top of this solder mask layer, the PID materials were again coated and cavities together with vias needed were then defined through photolithography [Fig. 2(c)], similar to the solder mask and via openings in Fig. 2(b). The cavity dielectric layer was 50 µm in thickness. The opened vias around cavities were again metallized by SAP process. The exposed metal pads within the cavities were protected from the via metallization with photoresist films. Then, a second cavity layer was built-up over the first cavity layer, resulting in about 100 µm in total cavity depth [Fig. 2(d)]. The second cavity layer was fabricated to be slightly larger than the first cavity layer since photolithography process tolerances between layers need to be considered. In this paper, 50 µm were given to all four edges of the cavities as the tolerances. Depending on the required cavity depth, the cavity layer processes can be further repeated. The photocavities could be basically created without any additional cost increase while the vias were formed in the build-up layers. 65 2) Plasma-Cavity Substrates: Plasma-etching is also assumed to be cost-effective in generating high volumes of cavities in dielectric layers since panels are loaded into a plasma chamber and etched simultaneously. Fig. 3 shows the schematic process flow of cavity formation by plasmaetching. Two layers of RXP-4 dielectric (Rogers Corporation) were laminated on a circuitized BT core, leading to 100 µm thick build-up layers on the core. During the RXP-4 layer lamination, 18 µm thick copper layer was also placed on top of the RXP-4 layers, as shown in Fig. 3(a). The plasmaetching mask was created on the copper by applying typical lithography processes [Fig. 3(b)]. The metal mask defines the position and size of cavities as well as vias and unmasked dielectrics are eroded by the plasma. Plasma was generated in a partial vacuum filled with a mixture of oxygen and chlorofluoro (CF4 ) gases. Because plasma cavity formation is based on an etching process, careful process conditioning is needed to minimize undercutting. It was confirmed that the undercut could be minimized with a 3:1 ratio of oxygen to CF4 at a substrate temperature of 100 °C and the RF power of 450 W. With these plasma conditions, the plasma-etching rate was about 1 µm/min. Once cavities were formed by plasma-etching, as shown in Fig. 3(c), the copper metal mask could be easily peeled off by hand since any surface treatments on the RXP-4 materials were not made before the copper lamination. Good lamination between copper and the RXP-4 materials requires some special surface treatments on the RXP-4 materials [14]–[18]. The vias formed during plasma-etching were filled by SAP plating [Fig. 3(d)]. The plasma-cavities could also be created without any additional cost increase while the vias were formed in the build-up layers. 3) Laser-Cavity Substrates: Laser drilling, which uses a focused laser beam to create small vias, is considered to be the most promising via-formation technology and its equipments are also well-established for high-volume production. Several laser processes, including excimer, YAG, and CO2 , have been developed to generate small vias. The smallest feature size depends primarily on the laser wavelength, beam energy density, and thickness of the drilled materials. In this paper, UV laser has been used for the cavity process, which was confirmed to be able to ablate large area of RXP-4 buildup materials with cost competiveness. The application of laser drilling to cavity formation in build-up layers is very straightforward. The laser removes the dielectric materials to form cavities. Better cavity shape can be achieved without the undercut, which was one of main concerns in the plasma-cavity formation methods. The laser-cavity process is also relatively simple because it needs neither a complicated photolithography process in photo-cavities nor metal mask patterning/removal in plasma-cavities. Fig. 4 shows the schematic process flow for laser-cavity formation. Laser-cavity was formed on the RXP-4 layers laminated on a patterned BT core like plasma-cavity substrate. Laser drilling was performed in two steps. Cavity area was first laser-drilled until the laser beam reached about 90 µm. Then the second laser-drilling was applied only over the copper pads, generating about 10 µm thick solder mask layer,
  4. 4. 66 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 1, JANUARY 2012 (a) (b) (a) (c) Fig. 4. Schematic process flow of laser defined cavities. (a) Dielectric layer lamination. (b) Laser drilling of cavity and via. (c) Via metallization. as shown in Fig. 4(b). During cavity process, vias were also created around the cavities and later metallized by SAP process [Fig. 4(c)]. (b) B. Fabricated Cavity Substrates Fig. 5 shows all three kinds of the cavity substrates fabricated by photolithography, plasma-etching, and laser-drilling, respectively. They were all well defined according to each process detail described in the previous section, measuring about 100 µm in depth. The photo-sensitive dielectric used for photo-cavity substrates is shown in dark brown color [Fig. 5(a)], while the low loss dielectric RXP-4 materials used for both plasma- and laser-cavity substrates are shown in a light green color [Fig. 5(b) and (c)]. As can be seen in Fig. 5, the metal pads, on which the solder bumps of chips will be placed, are clearly seen inside all the fabricated cavities. The patterned pads on BT Cu clad laminate had been covered by either photo-sensitive or RXP-4 dielectric materials while the dielectric materials were coated or laminated. When the dielectric materials were removed to form cavities by either photolithography, plasma-etching or laser-drilling, the metal pads buried under the dielectric layers were successfully again exposed. Each cavity-substrate contains 32 cavities on it. Half of them are rectangular shaped for embedding 4.5 × 9.0 mm chips and the other half is square shaped for 7.0 × 7.0 mm chips. For the cavities of each shape, four different sizes of cavities were fabricated by giving the four cavity edges an equal clearance varying from 50, 100, 200 to 400 µm to consider various tolerances, such as chip size tolerances, cavity process tolerances, and chip placement tolerances inside the cavities. The electrical connection of vias, metal traces, and (c) Fig. 5. Cavities on 6 × 6 inch BT substrates fabricated by (a) photolithography, (b) plasma-etching, and (c) laser etching. pads on all the cavity substrates was confirmed by daisy chain testing. Fig. 6(a)–(c) shows the shape of cavity edges depending on the cavity formation processes. No cavity shape distortion was observed in all the cases. Photo-cavities had the smoothest and sharpest edges. The edges of plasma-cavities were not as
  5. 5. LEE et al.: NOVEL CHIP-LAST METHOD FOR EMBEDDED ACTIVES IN ORGANIC PACKAGING SUBSTRATES 67 (a) (a) (b) (b) (c) (c) Fig. 6. Enlarged view of cavity edge shape (a) photo-cavities, (b) plasmacavities, and (c) laser-cavities. Fig. 7. Pad openings inside of the cavity (a) photo-cavities, (b) plasmacavities, and (c) laser-cavities. sharp as those of photo-cavities, since the plasma undercut was inevitable even though the undercut was minimized by optimizing plasma processing parameters. In the laser-cavities, two of four edges were relatively smooth, while the other two edges were saw-toothed, as shown in the horizontal cavity edges of Fig. 6(c). It was found that laser drilling started or ended at either of these two saw-toothed edges. Fig. 7(a)–(c) shows the inside of each cavity. Solder mask layer could be formed on the photo- and laser-cavity substrates, while it could not be created on the plasma-cavities with current plasmacavity process scheme. Fig. 8 compares the sizes of the cavities fabricated for 7.0 × 7.0 mm chip embedding with those designed on masks. It is observed that the photo-cavities had almost the same dimension with the ones drawn on the mask (<5 µm in size difference). The laser-cavities were, on average, 50 µm larger than the cavities designed on the mask. The plasma-cavities were always much larger than the ones on the mask (about 190 µm in size difference, almost double of the laminated layer thickness) due to plasma-etching undercut, as described earlier. It can be summarized that most accurate and precise cavity dimension control is possible with photo-lithography process, followed by laser-drilling and plasma-etching. IV. E MBEDDING OF C HIPS INTO C AVITY S UBSTRATES A. Embedding Process Details Thin chips of two different sizes were embedded and assembled into their corresponding sized/shaped cavities: rectangular chips of 4.5 × 9.0 mm in size with two-side peripheral I/Os and square chips of 7.0 × 7.0 mm in size with full-area array I/Os. As interconnections, solder bumps of 70–80 µm in height were used for both chips. Chips were fabricated by conventional wafer bumping processes. Table I shows the details of chips used in this paper. Both chips had daisy chains and were thinned to 100 µm by mechanical back grinding. The chips were placed onto the metal pads within all the fabricated cavities with Fineplacer (Finetech GmbH & Co.),
  6. 6. 68 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 1, JANUARY 2012 8.4 Designed Photo Plasma Laser 8.2 Cavity size [mm] 8.0 7.8 7.6 7.4 7.2 (a) (b) 7.0 Fig. 9. Photo-cavities (a) before chip embedding and (b) after chip embedding. 6.8 6.6 Fig. 8. 50 µm clearance 100 µm clearance 200 µm clearance 400 µm clearance Solder bumps Cavity size comparison. TABLE I C HIPS U SED IN T HIS PAPER Size Chip size tolerance Solder bump pitch Solder bump height No. of I/Os Rectangular chips 4.5 mm × 9.0 mm ±2.5 µm 200 µm 70–80 µm 60 Daisy chain test pads Square chips 7.0 mm × 7.0 mm ±2.5 µm 150 µm 70–80 µm 1936 Vias (a) which is known to provide placement accuracy of ±0.5 µm. No-clean flux (NR200, Alpha metals) was used to reduce possible flux residue in the gap between chips and substrates within the cavities. Solder was reflowed in a conventional solder reflow oven with a Sn-3.5Ag solder reflow profile (a peak temperature of 250 °C). Solder bumps Daisy chain test pads B. Embedded Chips in Cavity Substrates Fig. 9(a) shows the fabricated photo-cavity substrates. Chips were embedded within the photo-cavities, as shown in Fig. 9(b). With no disturbances from cavity structures, chips could be successfully placed into any sized photo-cavities that have the chip-cavity clearances varying from 50 to 400 µm. The X-ray images of Fig. 10 shows both rectangular and square chips assembled within the photo-cavities having the smallest chip-cavity clearance of 50 µm. The rectangular chips have two rows of peripheral solder bumps with 200 µm pitches, while the square chips have area array solder bumps with 150 µm pitches. The X-ray images also show that no solder bridge or missed balls have been observed in both cases. Daisy chain testing also confirmed that the electrical interconnections from chips to cavity-substrates have been successfully made. While chips could be assembled into the plasma-cavities, solder bridge was observed (not shown here) since solder mask layer could not be introduced during plasma cavity formation process. For the successful chip embedding into the plasmacavity substrates, it is thought that the plasma-cavity process to be able to introduce a solder mask layer needs to be developed. Vias (b) Fig. 10. X-ray images of the chips placed within the photo-cavities. (a) 4.5 × 9 mm2 rectangular chips with peripheral solder bumps. (b) 7 × 7 mm2 square chips with area array solder bumps. Similar to the chip embedding within the photo-cavities, successful chip embedding into the laser-cavities was achieved with all the chip-cavity clearances varying 50 µm to 400 µm. Since solder mask layer could be created inside the lasercavities, the solder bridge that was observed in the plasmacavities did not occur. V. C ONCLUSION The concept of chip-last embedded actives, in which active chips were embedded into package substrates after the fabrication of the package substrates was completed, has been
  7. 7. LEE et al.: NOVEL CHIP-LAST METHOD FOR EMBEDDED ACTIVES IN ORGANIC PACKAGING SUBSTRATES proposed and its first prototype has also been demonstrated. To enable these noble chip-last embedded actives, cavities have been introduced within the build-up layers of package substrates and the active chips have been placed into the cavities and electrically interconnected with circuits in them. Three different cavity formation processes have been developed by applying commonly used micro-via drilling technologies including photolithography, plasma-etching, and laser-drilling. The photolithography could define best shape of cavities and have good cavity-dimensional controllability, while it always requires the usage of photo-sensitive dielectric for the buildup layers. The plasma- and laser-cavities do not need the photosensitivity in the dielectric materials used. The plasmacavity revealed considerable undercut during cavity formation, which resulted in bad controllability of cavity dimension. The laser drilling process was confirmed to enable to moderately control the cavity shape and dimension. Chip embedding into all these three kinds of fabricated cavities was not so much different with conventional surface mount flip-chip assembly. Chip assembly could be successfully achieved within the photo-cavities and the laser-cavities, while solder bridge has been observed in the plasma-cavities since they do not contain solder mask layer within the cavities. Reliability evaluation for these chip-last embedded actives was under study including underfilling process development within the cavities. ACKNOWLEDGMENT The authors would like to thank the Institute of Microelectronics, Singapore, for providing the chips used for this paper. R EFERENCES [1] R. Tummala and M. Swaminathan, Introduction to System-on-Package. New York: McGraw-Hill, 2008, pp. 3–37. [2] R. Tummala, “Moore’s law meets its match (system-on-package),” IEEE Spectrum, vol. 43, no. 6, pp. 44–49, Jun. 2006. [3] S. Yokogawa, “Method of manufacturing the same,” U.S. Patent 3 903 590, Sep. 9, 1975. [4] R. Fillion, C. Woychik, T. Zhang, and D. Bitting, “Embedded chip buildup using fine line interconnect,” in Proc. 57th Electron. Comp. Technol. Conf., May–Jun. 2007, pp. 49–53. [5] R. Mahajan, R. Nair, V. Wakharkar, J. Swan, J. Tang, and G. Vandentop, “Emerging directions for packaging,” Intel Technol. J., vol. 6, no. 2, pp. 62–75, May 2002. [6] L. Boettcher, D. Manessis, A. Ostmann, S. Karaszkiewicz, and H. Reichl, “Embedding of chips for system in package realization - technology and applications,” in Proc. 3rd Int. Microsyst., Packag., Assembly Circuits Technol. Conf., Taipei, Taiwan, Oct. 2008, pp. 383–386. [7] R. J. Wojnarowski, T. B. Gorczyca, and S. E. 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May–Jun. 2005, pp. 356–361. 69 [12] M. Sunohara, K. Murayama, M. Higashi, and M. Shimizu, “Development of interconnect technologies for embedded organic packages,” in Proc. 53rd Electron. Comp. Technol. Conf., May 2003, pp. 1484–1489. [13] D. Manessis, S.-F. Yen, A. Ostmann, R. Aschenbrenner, and H. Reichl, “Technical understanding of resin-coated-copper (RCC) lamination processes for realization of reliable chip embedding technologies,” in Proc. 57th Electron. Comp. Technol. Conf., Reno, NV, May–Jun. 2007, pp. 278–285. [14] G. Krishnan, F. Liu, V. Sundaram, R. Pucha, S. Kennedy, D. Baars, J. Dobrick, D. Guo, J. Neill, S. Paul, and R. Tummala, “High performance organic dielectrics and high density substrates for next generation system on a package (SOP) technology,” in Proc. 58th Electron. Comp. Technol. Conf., Lake Buena Vista, FL, May 2008, pp. 2101–2104. [15] S. Kennedy, A. Horn, G. Bull, F. Liu, H. Chan, V. Sundaram, and R. Tummala, “An overview of material options suitable for today’s commercial millimeter wave designs,” Circuitree, vol. 22, no. 5, pp. 16–21, May 2009. [16] S. Hwang, S. Min, M. Swaminathan, V. Sundaram, H. Chan, F. Liu, S. Kennedy, D. Barrs, B. Lacroix, Y. Li, and J. Papapolymerou, “Characterization of next generation thin low-K and low-loss organic dielectrics from 1 to 110 GHz,” IEEE Trans. Adv. Packag., vol. 33, no. 1, pp. 180–188, Feb. 2010. [17] S. Hwang, S. Min, H. Chan, V. Sundaram, and M. Swaminathan, “A compact third-order 5 GHz bandpass filter with enhanced stopband characteristics in ultrathin organic substrate,” in Proc. IEEE Radio Wireless Symp., New Orleans, LA, Jan. 2010, pp. 452–455. [18] D. Athreya, V. Sundaram, M. Iyer, and R. Tummala, “Ultrahigh Q embedded inductors in highly miniaturized family of low loss organic substrates,” in Proc. 58th Electron. Comp. Technol. Conf., Lake Buena Vista, FL, May 2008, pp. 2073–2080. Baik-Woo Lee received the Ph.D. degree in material science and engineering from Seoul National University, Seoul, Korea, in 2004. He has been a Researcher with the Samsung Institute of Technology (SAIT), Suwon, South Korea, since 2009, working on the advanced packaging structural designs, materials and processes for bio, medical, and energy power applications. Prior to joining SAIT, he was a Research Engineer with the Packaging Research Center, Georgia Institute of Technology, Atlanta, focusing on system-on-package technology, which includes embedded active integrated circuits, fine-pitch interconnects, 3-D chip stacking, and embedded capacitors. He has several U.S. patents and has authored over 30 publications in refereed journals and conferences. Venky Sundaram (M’10) received the B.S. degree in metallurgical engineering from the Indian Institute of Technology, Mumbai, India, and the M.S. and Ph.D. degrees in materials science and engineering from the Georgia Institute of Technology (Georgia Tech), Atlanta. He is the Director of Research with the Packaging Research Center (PRC), Georgia Tech, and also serves as the Program Manager for the Silicon and Glass Package Consortium. He has been with PRC since 1997, focusing on system-on-package technology, ultra-high density substrates, and systems integration research. He is advising iNEMI on the new wiring density initiative. He is a Co-Founder of Jacket Micro Devices, Atlanta, GA, a radio frequency substrate and module Georgia Tech PRC Spin-off Company acquired by AVX. He has several U.S. and international patents and has more than 100 publications in the systems packaging technology space. Dr. Sundaram has won several Best Paper and Poster Awards and serves as Session Chair for advanced packaging topics at international conferences. He is a member of the IEEE Components, Packaging, and Manufacturing Technology Technical Committee of High Density Substrates. Scott Kennedy photograph and biography not available at the time of publication. Dirk Baars photograph and biography not available at the time of publication.
  8. 8. 70 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 1, JANUARY 2012 Rao Tummala (M’88–SM’90–F’94) received the B.S. degree from the Indian Institute of Science, Bangalore, India, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, Urbana. He is a Distinguished and Endowed Chair Professor and the Founding Director of the National Science Foundation Engineering Research Center, Georgia Institute of Technology (Georgia Tech), Atlanta, the most comprehensive academic center in microsystems packaging pioneering system-onpackage vision since 1994. Prior to joining Georgia Tech, he was an IBM fellow, pioneering major technologies such as the first plasma flat panel display based on gas discharge, the first and next three generations of multichip packaging. He is known as the Father of low-temperature co-fired ceramic (LTCC) having developed 61-layer LTCC with copper and copper-polymer thin film materials. He has published 426 technical papers, holds 74 patents, and inventions. He has authored the first modern packaging reference book Microelectronics Packaging Handbook (Van Nostrand, 1988), the first undergraduate textbook Fundamentals of Microsystems Packaging (McGraw Hill, 2001), and first book introducing the System-on-Package technology. Prof. Tummala has received many industry, academic, and professional society awards including the Industry Week’s Award for improving U.S. competitiveness, the IEEEs David Sarnoff, Major Education, and Sustained Technical Awards, the Dan Hughes Award from International Microelectronics and Packaging Society (IMAPS), the Engineering Materials Achievement Award from DVM and ASM-International, the Total Excellence in Manufacturing Award from SME, the John Jeppson’s Award from the American Ceramic Society, as well as the Distinguished Alumni Awards from the University of Illinois and Georgia Tech. In 2011, he received the ISA Technovisionary Award from the Indian Institute of Science and the highest IEEE Award in packaging at the 61st Electronic Components and Technology Conference for his contributions in package integration research, cross-disciplinary education, and globalization of packaging. He is a fellow of IMAPS and the American Ceramic Society, and a member of the National Academy of Engineering in U.S. and India. He is a past President of both the IEEE Components, Packaging, and Manufacturing Technology Society and IMAPS Society.

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