VLSI IEEE PROJECTS LIST- (2014 – 2015) 
CODE TITLE YEAR 
NVD-01 32 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage ...
NVD-15 Low-Complexity Low-Latency Architecture for Matching of Data 
Encoded With Hard Systematic Error-Correcting Codes 
...
NVD-33 Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter 
Based on Distributed Arithmetic 
2013(T) 
NVD-34 Effi...
Dadda Algorithm 
NVD-51 Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product 
Code 
2012(T) 
NVD-52 High-Speed Lo...
on Radix-2 Modified Booth Algorithm 
NVD-68 FPGA Implementation of Network on Chip Framework using HDL 2010 
NVD-69 Design...
NVL13 Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring 
Efficient Embedded Logic 
2013(T) 
NVL14 Minimizing E...
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M.tech m.e vlsi projects list 2014 2015

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M.tech m.e vlsi projects list 2014 2015

  1. 1. VLSI IEEE PROJECTS LIST- (2014 – 2015) CODE TITLE YEAR NVD-01 32 Bit×32 Bit Multi precision Razor-Based Dynamic Voltage Scaling Multiplier With Operands Scheduler 2014(T) NVD-02 A 16-Core Processor With Shared-Memory and Message-Passing Communications 2014(T) NVD-03 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator 2014(T) NVD-04 High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic 2014(T) NVD-05 Improved 8-Point Approximate DCT for Image and Video Compression Requiring Only 14 Additions 2014(T) NVD-06 Area–Delay–Power Efficient Carry-Select Adder 2014(T) NVD-07 Multifunction Residue Architectures for Cryptography 2014(T) NVD-08 Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter With Low Adaptation-Delay 2014(T) NVD-09 Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic 2014(T) NVD-10 Fast Sign Detection Algorithm for the RNS Moduli Set {2n+1 − 1, 2n − 1, 2n} 2014(T) NVD-11 Efficient Integer DCT Architectures for HEVC 2014(T) NVD-12 Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation 2014(T) NVD-13 Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata 2014(T) NVD-14 Reverse Converter Design via Parallel-Prefix Adders: Novel Components, Methodology, and Implementations 2014(T) (AN ISO 9001: 2008 CERTIFIED COMPANY) CONTACT: MALLIKARJUN – 08297578555 / 09640648777 EMAIL US : INFO@NANOCDAC.COM
  2. 2. NVD-15 Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes 2014(T) NVD-16 Energy-Efficient High-Throughput Montgomery Modular Multipliers for RSA Cryptosystems 2014(T) NVD-17 Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes 2013(T) NVD-18 Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic 2013(T) NVD-19 Pipelined Radix- Feedforward FFT Architectures 2013(T) NVD-20 A Single-Channel Architecture for Algebraic Integer Based 88 2-D DCT Computation 2013(T) NVD-21 Radix-4 and radix-8 booth encoded multi-modulus multipliers 2013(T) NVD-22 High performance hardware implementation for RC4 stream cipher 2013(T) NVD-23 Pipeline radix 2^ k feed forward FFT architecture 2013(T) NVD-24 Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip 2013(T) NVD-25 Multi operand Redundant Adders on FPGAs 2013 NVD-26 Global built-in self-repair for 3D memories with redundancy sharing and parallel testing 2013 NVD-27 A Practical NoC Design for Parallel DES Computation 2013 NVD-28 Parallel AES Encryption Engines for Many-Core Processor Arrays 2013 NVD-29 VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog 2013 NVD-30 A VLIW Architecture for Executing Multi-Scalar/Vector Instructions on Unified Datapath 2013 NVD-31 A Novel Modulo Adder for 2n-2k- 1Residue Number System 2013(T) NVD-32 Low-cost FIR filter designs based on faithfully rounded truncated multiple constant multiplication/accumulation 2013(T) (AN ISO 9001: 2008 CERTIFIED COMPANY) CONTACT: MALLIKARJUN – 08297578555 / 09640648777 EMAIL US : INFO@NANOCDAC.COM
  3. 3. NVD-33 Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic 2013(T) NVD-34 Efficient VLSI Architectures of Split-Radix FFT using New Distributed Arithmetic 2013 NVD-36 Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic 2013 NVD-37 BIST Based Test Applications Enhanced with Adaptive Low Power RTPG and LFSR Reseeding Techniques 2013 NVD-38 Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA 2013 NVD-39 Enhanced Area Efficient Architecture for 128 bit Modified CSLA 2013 NVD-40 High Performance Hardware Implementation of AES Using Minimal Resources 2013 NVD-41 High Performance Pipelined Design for FFT Processor based ON FPGA 2013 NVD-42 Implementation of I2C Master Bus Controller on FPGA 2013 NVD-43 Novel High Speed Vedic Mathematics Multiplier using Compressors 2013 NVD-44 Period Extension and Randomness Enhancement Using High- Throughput Reseeding-Mixing PRNG 2013 NVD-45 VLSI Implementation of a High Speed Single Precision Floating Point Unit Using Verilog 2013 NVD-46 VLSI implementation of Fast Addition using Quaternary Signed Digit Number System 2013 NVD-47 Design of High Performance 64 bit MAC Unit 2013 NVD-48 FPGA Architecture for OFDM Software Defined Radio with an optimized Direct Digital Frequency Synthesizer 2013 NVD-49 Implementation of UART with BIST Technique in FPGA 2013 NVD-50 A High Speed Binary Floating Point Multiplier Using 2013 (AN ISO 9001: 2008 CERTIFIED COMPANY) CONTACT: MALLIKARJUN – 08297578555 / 09640648777 EMAIL US : INFO@NANOCDAC.COM
  4. 4. Dadda Algorithm NVD-51 Soft-Error-Resilient FPGAs Using Built-In 2-D Hamming Product Code 2012(T) NVD-52 High-Speed Low-Power Viterbi Decoder Design for TCM Decoders 2012(T) NVD-53 Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications 2012(T) NVD-54 Product Code Schemes for Error Correction in MLC NAND Flash Memories 2012(T) NVD-55 Scalable digital cmos camparator using a parallel prefix tree 2012(T) NVD-56 Low-Power and Area-Efficient Carry Select Adder 2012(T) NVD-57 A Non binary LDPC Decoder Architecture With Adaptive Message Control 2012(T) NVD-58 Low-Cost Binary128 Floating-Point FMA Unit Design with SIMD Support 2012(T) NVD-59 Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications 2012(T) NVD-60 Viterbi-Based Efficient Test Data Compression 2012(T) NVD-61 Design and Implementation of 64-Bit Execute Stage for VLIW Processor Architecture on FPGA 2012 NVD-62 Design and FPGA-based Implementation of a High Performance 32- bit DSP Processor 2012 NVD-63 FPGA Implementation of Sine and Cosine Generators using CORDIC Algorithm 2012 NVD-64 Reconfigurable Routers for Low Power and High Performance 2011(T) NVD-65 Configurable Multimode Embedded Floating-Point Units for FPGAs 2011(T) NVD-66 Data Encoding Schemes in Networks on Chip 2011(T) NVD-67 A New VLSI Architecture of Parallel Multiplier–Accumulator Based 2010(T) (AN ISO 9001: 2008 CERTIFIED COMPANY) CONTACT: MALLIKARJUN – 08297578555 / 09640648777 EMAIL US : INFO@NANOCDAC.COM
  5. 5. on Radix-2 Modified Booth Algorithm NVD-68 FPGA Implementation of Network on Chip Framework using HDL 2010 NVD-69 Design and Implementation of Multi-mode QC-LDPC Decoder 2010 NVD-70 Data Encoding for Low-Power in Wormhole-Switched Networks-on- Chip 2009 LOWPOWER VLSI NVL01 Area-Delay Efficient Binary Adders in QCA 2014(T) NVL02 14 GSps Four-Bit Noninterleaved Data Converter Pair in 90 nm CMOS With Built-In Eye Diagram Testability 2014(T) NVL03 Power Efficient Class AB Op-Amps with High and Symmetrical Slew Rate 2014(T) NVL04 An Optimized Modified Booth Recoder for Efficient Design of the Add-Multiply Operator 2014(T) NVL05 Area–Delay–Power Efficient Carry-Select Adder 2014(T) NVL06 Carbon Nanotubes Blowing New Life Into NP Dynamic CMOS Circuits 2014(T) NVL07 Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison 2014(T) NVL08 Novel Class of Energy-Efficient Very High-Speed Conditional Push– Pull Pulsed Latches 2014(T) NVL09 Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme 2014(T) NVL10 Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits 2014 NVL11 Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator 2014(T) NVL12 Constant Delay Logic Style 2013(T) (AN ISO 9001: 2008 CERTIFIED COMPANY) CONTACT: MALLIKARJUN – 08297578555 / 09640648777 EMAIL US : INFO@NANOCDAC.COM
  6. 6. NVL13 Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic 2013(T) NVL14 Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique 2013(T) NVL15 A 65 nm Low-Power Adaptive-Coupling Redundant Flip-Flop 2013(T) NVL16 A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS 2013(T) NVL17 Efficient Multiternary Digit Adder Design in CNTFET Technology 2013(T) NVL18 Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-μm CMOS Technology 2013(T) NVL19 Design of Testable Reversible Sequential Circuits 2013(T) NVL20 A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor 2013 NVL21 Comparative Analysis and Optimization of Active Power and Delay of 1-Bit Full Adder at 45 nm Technology 2013 NVL22 A Low-Power Single-Phase Clock Multiband Flexible Divider 2012(T) NVL23 Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks 2012(T) NVL24 Four bit CMOS full adder in submicron technology with low leakage and ground bounce noice reduction 2012 NVL25 Design of Low Power TPG Using LP-LFSR 2012 NVL26 Design of Sequential Elements for Low Power Clocking System 2011(T) (AN ISO 9001: 2008 CERTIFIED COMPANY) CONTACT: MALLIKARJUN – 08297578555 / 09640648777 EMAIL US : INFO@NANOCDAC.COM

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