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Design of Ultra-Wide Band Physical Layer (PHY) Transceiver for WBAN (802.15.6) Baseband

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  • 1. Design of Ultra-Wide Band Physical Layer (PHY) Transceiver for WBAN (802.15.6) Baseband A REPORT SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE AWARD OF THE DEGREE Master of Technology By R Kameswara Naga Mahesh Roll no. 11410203 Supervisor Prof. Roy P Paily Department of Electronics and Electrical Engineering INDIAN INSTITUTE OF TECHNOLOGY GUWAHATI ASSAM - 781039, INDIA June, 2013.
  • 2. D E C L A R A T I O N This is to certify that the thesis entitled “Design of Ultra-Wide Band Phys- ical Layer (PHY) Transceiver for WBAN (802.15.6) Baseband”, submitted by me to the Indian Institute of Technology Guwahati for the award of degree of Master of Technology is a bonafide work carried out by me under the supervision of Prof. Roy P Paily. The contents of this thesis, in full or in parts, have not been submitted to any other Institute or University for the award of any degree or diploma. R Kameswara Naga Mahesh June, 2013 Dept. of Electronics and Electrical Engineering, Guwahati. Indian Institute of Technology Guwahati, Assam- 781039, India.
  • 3. C E R T I F I C A T E This is to certify that the work contained in this thesis entitled “Design of Ultra-Wide Band Physical Layer (PHY) Transceiver for WBAN (802.15.6) Baseband” by R Kameswara Naga Mahesh, Roll No. 11410203, has been carried out in the VLSI Design lab, Department of Electronics and Electrical Engi- neering, Indian Institute of Technology Guwahati under my supervision and that it has not been submitted elsewhere for a degree. Prof. Roy P Paily June, 2013 Dept. of Electronics and Electrical Engineering, Guwahati. Indian Institute of Technology Guwahati, Assam- 781039, India.
  • 4. Dedicated to My Parents and My Friends
  • 5. Acknowledgements It gives me immense pleasure to express my deepest and most sincere feeling of gratitude to Prof. Roy Paily who as my supervisor has extensively helped me with his constant guidance, encouragement and valuable suggestions during the course of the thesis, without which this work would not have seen the light of the day. I would also like to thank the Head of the Department and the other faculty members for their kind help in carrying out this work. I am very grateful to the non-teaching staff and seniors of the department who has always been my side from the very beginning of my work. Special thanks to my family members for their tremendous support and love all through. I have received lots of help and cooperation from my friends Seshu Babu, Sathish Babu, Sushant Pandey and Shravan Kumar and all my freinds of M.Tech 2013 batch, who made my stay at Guwahati, a memorable period of my life and special thanks to Pavan Kumar Manchi, and Akash Ganeshan, who have helped me through the project. I would also like to thank Rahul Shrestha, for giving us valuable insights into design, as well as giving me a tutorial on the synthesis tools. Finally I would like to thank the almighty God for enabling me to achieve all that I have achieved. R Kameswara Naga Mahesh IIT Guwahati June, 2013. 4
  • 6. Abstract In this age of wireless technology, Wireless Body Area Networks (WBAN) is revolutionizing the concept of patient care and health monitoring. WBAN can provide medical, assisted living, sports and entertainment for human beings and is gradually matching the needs of society. IEEE 802 Task Group has published a new IEEE 802.15.6 standard in February 2012. The standard defines a Medium Access Control (MAC) layer supporting three Physical (PHY) layers. The three PHY layers are narrowband (NB) PHY, ultra wideband (UWB) PHY and human body communication (HBC) PHY. This thesis work presents UWB-PHY baseband transceiver design for wireless body area networks (WBAN) as specified in the IEEE 802.15.6 standard. We estimated the power using Synopsys Design Compiler using 0.13 µm technology library operated at 487.5 kHz system clock, 1.08 V supply and observed a power of 26.04 µW occupying design area of 35244.8 µm2 in default mode of operation for the transmitter, and power of 47.74 µW, area of 50170.8 µm2 for the receiver. i
  • 7. Contents 1 Introduction 1 1.0.1 Advantages of WBAN . . . . . . . . . . . . . . . . . . . . . 3 1.0.2 Applications of WBAN . . . . . . . . . . . . . . . . . . . . . 3 1.0.3 Design Issues . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 Development of WBAN (802.15.6) Standard . . . . . . . . . 6 1.1.2 Baseband Architectures for WBAN . . . . . . . . . . . . . . 7 1.2 A WBAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.3 Scope of the work . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 WBAN Standard (802.15.6) [1] 10 2.1 Ultra wideband PHY specification . . . . . . . . . . . . . . . . . . . 11 2.2 UWB-PHY Frame format . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 Synchronization header (SHR) . . . . . . . . . . . . . . . . . 13 2.2.2 Physical layer header (PHR) . . . . . . . . . . . . . . . . . . 14 2.2.3 Physical layer service data unit (PSDU) . . . . . . . . . . . 15 3 Ultra Wideband Baseband Transmitter Design 16 3.1 PHR Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1.1 Head Check Sequence Generation . . . . . . . . . . . . . . . 18 3.1.2 Shortened BCH Encoder . . . . . . . . . . . . . . . . . . . . 19 3.2 PSDU Construction . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.2.1 Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ii
  • 8. 3.2.2 BCH encoder . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.3 Pad Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.4 Bit-Interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.3 Transmitter Controller . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.4 Results and discussion . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.4.1 Synthesis Report . . . . . . . . . . . . . . . . . . . . . . . . 27 4 Ultra Wideband Baseband Receiver Design 29 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 Receiver Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.3 Decoder HCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.4 BCH Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4.1 Basics of BCH code . . . . . . . . . . . . . . . . . . . . . . . 32 4.4.2 Galois fields . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4.3 Manipulating Field Elements . . . . . . . . . . . . . . . . . 34 4.4.4 Decoding BCH codes . . . . . . . . . . . . . . . . . . . . . . 35 4.4.5 Computation of Syndrome . . . . . . . . . . . . . . . . . . . 36 4.4.6 The Error Locator Polynomial . . . . . . . . . . . . . . . . . 37 4.4.7 Chein Search . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4.4.8 Architecture of BCH Decoder . . . . . . . . . . . . . . . . . 44 4.5 De-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.6 De-scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.7 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.7.1 Synthesis Report . . . . . . . . . . . . . . . . . . . . . . . . 48 5 Conclusion and Future Direction 50 iii
  • 9. List of Figures 1.1 A WBAN System [2] . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 A WBAN System Transmitter . . . . . . . . . . . . . . . . . . . . . 8 2.1 Ultra wideband Physical layer Frame Format . . . . . . . . . . . . . 13 2.2 SHR [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Physical header [1] . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 PHR frame structure [1] . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 MPDU frame format [1] . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6 PSDU construction [1] . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Block diagram of UWB baseband transmitter Architecture . . . . . 17 3.2 Block diagram for PHR Construction . . . . . . . . . . . . . . . . . 18 3.3 Block diagram of HCS implementation [1] . . . . . . . . . . . . . . 19 3.4 Output of PHR block . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Block diagram of a side-stream scrambler [1] . . . . . . . . . . . . . 20 3.6 Output of Scrambler . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.7 Block diagram of a BCH encoder . . . . . . . . . . . . . . . . . . . 21 3.8 Output of BCH encoder . . . . . . . . . . . . . . . . . . . . . . . . 22 3.9 Output of Pad bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 Output of Bit-Interleaver . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11 Flowchart of transmitter controller . . . . . . . . . . . . . . . . . . 26 4.1 General block diagram of Receiver . . . . . . . . . . . . . . . . . . . 29 4.2 Block diagram of UWB baseband transmitter Architecture . . . . . 30 4.3 Output of Decoder HCS . . . . . . . . . . . . . . . . . . . . . . . . 32 iv
  • 10. 4.4 Hardware implementation of the syndrome . . . . . . . . . . . . . . 37 4.5 Output of Syndrome block . . . . . . . . . . . . . . . . . . . . . . . 37 4.6 Proposed Multiplication for Galois field polynomials . . . . . . . . . 41 4.7 Output of proposed multiplier block . . . . . . . . . . . . . . . . . . 42 4.8 Output of Error Locator Polynomial Block . . . . . . . . . . . . . . 43 4.9 Implementation of Chein Search Algorithm . . . . . . . . . . . . . . 44 4.10 Output of Chein Search Algorithm . . . . . . . . . . . . . . . . . . 44 4.11 Overall architecture of the BCH decoder . . . . . . . . . . . . . . . 45 4.12 Output of the BCH decoder . . . . . . . . . . . . . . . . . . . . . . 46 4.13 Algorithm for De-interleaver address generation . . . . . . . . . . . 47 v
  • 11. List of Tables 1.1 In-body and on-body WBAN applications [3] . . . . . . . . . . . . 4 2.1 Parameters of UWB-PHY [4] . . . . . . . . . . . . . . . . . . . . . 12 3.1 Scrambler seed selection [1] . . . . . . . . . . . . . . . . . . . . . . 20 3.2 Performance Characteristics of Baseband Transmitter . . . . . . . . 28 4.1 Construction of GF(23 ) . . . . . . . . . . . . . . . . . . . . . . . . 34 4.2 Inversion-less version of Berlekamp-Massey alogorithm [5] . . . . . . 39 4.3 Performance Characteristics of Baseband Receiver . . . . . . . . . . 48 5.1 Comparisons of various Architectures . . . . . . . . . . . . . . . . . 51 vi
  • 12. Chapter 1 Introduction In this chapter, the applications of body area network (BAN), literature review, a generic wireless body area network (WBAN) system, the scope and organization of this thesis will be presented. The advent of miniaturized sensors and actuators for monitoring, diagnostic, and therapeutic functions, and advances in wireless technology, supporting infras- tructure provide unprecedented opportunity for ubiquitous real-time health-care and fitness monitoring without constraining the activities of the user [6]. Wireless connected miniaturized sensors and actuators placed in, on, and around the body form a body area network for continuous, automated, and unobtrusive monitoring of physiological signs to support medical, lifestyle and entertainment applications. This class of networks is paving the way for the deployment of innovative health care monitoring applications. A WBAN allows continuous monitoring of the phys- iological parameters. Strategically placed wearable or implanted (in the body) wireless sensor nodes sample, process, and transmit vital signs (e.g., heart rate, blood pressure, tem- perature, pH, respiration, oxygen saturation) without constraining the activities of the wearer. The gathered data can be forwarded in real time to a hospital, clinic, or central repository over a local area network (LAN), wide area network (WAN), cellular network, and the like. Physicians and care givers can remotely access this data to assess the state of the health of the patient. Additionally, the patient can be 1
  • 13. 2 alerted using SMS, alarm, or reminder messages. WBAN technology could provide the connectivity to support the elderly in managing their daily life and medical conditions [2]. Typical such network shown in Figure 1.1. Figure 1.1: A WBAN System [2] WBAN technology is in early stage of development, and several research chal- lenges have to be overcome for it to be widely accepted. WBAN node typically consists of sensor and readout, analog-digital interface, power management unit, and a wireless transceiver. The complete system is powered by a small sized energy source. Energy consumption can be divided into three domains: sensing, (wireless) communication and data processing. The wireless communication is likely to be the most power consuming [2]. In some applications like implanted devices, a WBAN’s sensor/actuator node should operate while supporting a battery life time of months or even years without in- tervention. Therefore power budget is quite strict for the WBAN nodes since the node is driven by battery supply and also to protect human tissues while commu- nicating. Compared with traditional wire-based monitoring system, WBAN based body monitoring system has the following advantages
  • 14. 3 1.0.1 Advantages of WBAN Although many protocols and standards have been proposed for traditional wire- less sensor networks (WSNs) before WBAN (802.15.6) Standard, they are not well suited to the unique features and application requirements of BAN [7]. The main advantages of WBAN are listed below: 1. Flexibility: The first significant advantage is the mobility of patients/users of WBAN due to the use of portable monitoring devices. Non-invasive sensors can be used to automatically monitor physiological readings, which can be forwarded to nearby devices, such as a cell phone, a wrist watch, a headset, a laptop, or a robot, based on the application needs. 2. Effectiveness and Efficiency: The second advantage is the location in- dependent monitoring facility. A WBAN node being an autonomous device can search and find a suitable communication link ad transmit data. The signals that body sensors provide can be effectively processed to obtain reliable and accurate physiological estimations. In addition, their ultra-low power consumption makes their batteries long-lasting due to their ultra-low power consumption. 3. Cost-effective: With the increasing demand of body sensors in the consumer electronics market, more sensors will be mass-produced at a relatively low cost, especially in gaming and medical environments. 1.0.2 Applications of WBAN Initially the main purpose of BAN is to make possible for patients who need perma- nent monitoring to be fully mobile. Later on WBANs promote the tiny, lightweight, ultra-low-power monitoring devices that can be used in wide spectrum of applica- tions in health-care, fitness and entertainment. They have great potential for several applications including remote medical diagnosis, interactive gaming, and military applications. Table 1.1 [3] shows some of the in-body and on-body applications.
  • 15. 4 Table 1.1: In-body and on-body WBAN applications [3] Application Sensor Data Rate Power Privacy Type Node Consumption In-body Applications Glucose Sensor Few Kbps Extremely Low High Pace Maker Few Kbps Low High Endoscope Capsule >2Mbps Low Medium On-body Applications ECG 3 Kbps Low High Blood Pressure <10bps Relatively High High SpO2 32bps High High On-body Non-Medical Applications Music for Headsets 1.4Mbps High Low Forgotten things Monitor 256kbps Low Low Social Networking <200kbps Low High In-body applications include, monitoring and program changes for pacemakers and implantable cardiac defibrillators, control of bladder function, and restoration of limb movement. On-body medical applications include monitoring ECG, blood pressure, temperature, and respiration. Furthermore, on-body non- medical ap- plications include monitoring forgotten things, establishing a social network, and assessing soldier fatigue and battle readiness. 1. Remote health/Fitness monitoring: Health and motion information are monitored in real time, and delivered to near by diagnosis or storage devices, through which data can be forwarded to off-site doctors for further processing. 2. Military and sports training: For example, motion sensors can be worn at both hands and elbows, for accurate feature extraction of sports players movements. 3. Interactive gaming: Body sensors enable game players to perform actual body movements, such as boxing and shooting, that can be fedback to the corre- sponding gaming console, there by enhancing their entertainment experiences. 4. Personal information sharing: Private or business information can be stored in body sensors for many daily life applications such as shopping and infor-
  • 16. 5 mation exchange. 5. Secure authentication: This application involves resorting to both physi- ological and behavioral biometrics schemes, such as facial patterns, Finger prints and iris recognition. The potential problems, e.g., proneness to forgery and dupli- cability, however, have motivated the investigations into new physical/behavioral characteristics of the human body, e.g., Electroencephalography( EEG) and gait (the rate of moving), and multimodal biometric systems. 6. Human Computer Interaction (HCI): Traditional computer interfaces, like keyboards, mice, joysticks, and touch screens, are all replaceable by potential WBAN devices capable of automatically recognizing human motions, gestures (Mo- tion of hands or body to emphasize or help to express a thought or feeling), and activities. 1.0.3 Design Issues WBAN is an emerging technology but we should take care of certain issues while designing a WBAN system [8]. Some of the issues addressed below : (i) Power Source: Sensors have to extremely power efficient, because most of the WBAN sensors are battery operated and are required to last long without any need of maintenance. If the sensor is implantable, low power consumption is very important ideally to be self powered using energy extracted from environment. (ii) Interference: Almost all the short range networks operate in industrial, scientific and medical (ISM) range. The wireless link used for body sensors should reduce the interference and increase the co-existence of sensor node devices with other network devices available in the environment. A WBAN should be configured to listen to only devices which are part of network by using device authentication. (iii) Node Size: Node size need to be small, essentially low on complexity, light in weight, power efficient, easy to use, non-intrusive and reconfigurable as the nodes are deployed on the surface of the person’s body. The size and weight of sensors pre-dominantly determined by the size & weight of batteries. (iv) Consistent Performance: The performance of WBAN should be consistent.
  • 17. 1.1. Literature Review 6 Sensor measurements should be accurate and calibrated, even after the BAN device is switched off and on again. The wireless link should be robust and work under various user environments. (v) Intuitive and simple user interface: The end users of WBAN are not technicians or scientists, the users may be a normal person where the BAN is used for entertainment purposes or for rehabilitation purposes. So the interface should be user-friendly to understand and handle it properly. Apart from the above, the wide applications of WBAN will continue to encounter many challenging issues, such as scalability, interference cancelation, network coex- istence, privacy and energy efficiency. 1.1 Literature Review The development of WBAN technology started around 1996, which is written by T. G. Zimmerman around the idea of using wireless personal area network (WPAN) technologies to implement communications on, near, and around the human body [4]. 1.1.1 Development of WBAN (802.15.6) Standard The IEEE 802.15 Task group 6 (BAN) developed a communication standard opti- mized for low power devices and operation on,in or around the human body (not limited to human body) to serve a variety of applications including medical, con- sumer electronics / personal entertainment and others. IEEE Task Group 6 (TG6) was formed in November 2007 and began operations as TG6 in January 2008 in Taipei. It has received 34 proposals, merged into a single draft of the standard in March 2009. The draft undergone significant editing approved on 6th February 2012 and finally released final draft of standard as IEEE 802.15.6 on 29th February 2012 in Newyork, USA.
  • 18. 1.2. A WBAN System 7 1.1.2 Baseband Architectures for WBAN To the best of our knowledge, it is the first time an architecture for the WBAN according to WBAN (802.15.6) standard is implemented. There are some papers available for baseband implementation of WBAN before the standard was released. So the literature available was not exact to the said standard. Yuanjin Zheng et.al [9] proposed baseband transceiver for WBAN and is fab- ricated in an 0.18-µm CMOS process. With a 1.1 V supply and 4 MHz system clock, it consumes only 34 µW for Transmitter and 39.6 µW for Receiver. Yuanjin Zheng et.al [9] used Hamming encoder, Manchester encoder instead of BCH en- coder and scrambler. Liu et.al [10] implemented baseband transceiver for WBAN in a 0.18-µm CMOS technology, the baseband chip consumes 240.24 µW for Tx. mode and 202.34 µW for Rx. mode when working at a 250 kHz system clock and 1.8V supply. Liu et.al [10] also included Serial peripheral interface (SPI) in their design and did not include BCH encoder and scrambler. Nandagopal et.al [11] implemented a low power baseband Transceiver IC with different coding schemes like Hamming, BCH, LDPC codes and their power consumption are measured and compared. Nandagopal et.al [11] did not implement 192-bit interleaver in their design. 1.2 A WBAN System Each wireless node in WBAN must be capable of sending and receiving informa- tion. So the hardware of each node must contain both transmitter and receiver. Some hardware processing blocks are shared between transmitter and receiver. The receiver blocks, transmitter blocks and shared hardware blocks between them col- lectively is called transceiver. A Microcontroller unit (MCU) is needed to switch the transceiver to transmit and receive modes for transmission and reception of signal respectively. The central node receive the data sent by sensor nodes and stores in the memory. The receiver in central node has to comply with PHY layer specifications of WBAN. The transmitter of central node has to comply with PHY
  • 19. 1.2. A WBAN System 8 specifications of WBAN standard. A WBAN consists of small, intelligent devices attached on or implanted in the body or spread around the body which are capable of establishing a wireless com- munication link. These devices provide continuous health monitoring and real-time feedback to the user or medical personnel to implement intelligent perception and remote monitoring functions. Bio- Medical Sensors Low-Noise Amplifier A/D Converter MAC Physical Layer RF Front End Baseband Processing Figure 1.2: A WBAN System Transmitter A general block diagram of WBAN system Transmitter is shown in the Figure 1.2. A biosensor is an analytical device which converts a biological response into an electrical signal. A WBAN can include a number of physiological sensors de- pending on the end-user application. An extensive set of physiological sensors may include sensors as an ECG (electrocardiogram) sensor for monitoring heart activity, an EMG (electromyography) sensor for monitoring muscle activity, an EEG (elec- troencephalography) sensor for monitoring brain electrical activity, a tilt sensor for monitoring trunk position etc. [12]. These physiological sensors typically generate weak analog signals. The wireless sensor nodes should satisfy the following require- ments: minimal weight, miniature form-factor, low-power operation to permit pro- longed continuous monitoring, seamless integration into a WBAN, standard-based interface protocols, and patient-specific calibration, tuning, and customization. A Low power amplifier must be used to boost the weak signal measured by sensor and should be passed through band-pass. After amplification in many cases also involves digitization, as digital transmission can be made relatively robust through the proper use of source coding and carrier modulation. Finally, the serial signal is sent to baseband processing unit and then to a radio frequency (RF) modulator. After receiving the data, the receiver will demodulate, process the received data
  • 20. 1.3. Scope of the work 9 and then sent to a D/A converter to trace back the original data. 1.3 Scope of the work In this thesis, we will mainly focus on the physical layer baseband processing of the WBAN system according to the 802.15.6 WBAN standard. The standard sup- ports three physical layers (PHYs) namely narrowband (NB) PHY, ultra wideband (UWB) PHY and human body communication (HBC) PHY. In this thesis, our emphasis will be on UWB-PHY layer implementation as it has a large scope for implementation opportunities for high performance, robustness, low complexity, and ultra low power operation. There are two modes of operation in UWB-PHY, Default mode and High Quality of Service (QoS) mode. We are emphasizing the UWB-PHY in default mode because it is used in normal medical and non-medical applications, whereas high Quality of Service (QoS) mode is used only for high- priority medical applications. The baseband processing for the UWB-PHY default mode receiver implementation details are discussed in this thesis. 1.4 Thesis Organization This report starts explaining general understanding of WBAN. Chapter 1 briefly discusses the introduction, various applications of WBAN, issues with WBAN and its literature survey and the scope of the work. Chapter 2 discusses 802.15.6 WBAN standard physical layers specifically the Ultra Wide Band physical layer (UWB- PHY) and its specification in detail. Chapter 3 discusses the baseband transmitter architecture for UWB-PHY and the challenges with the design of transmitter, the proposed controller for transmitter and the results of the transmitter are discussed. Chapter 4 discusses the architecture of the receiver and focusses on its main blocks BCH decoder and the de-interleaver design and the results of receiver are discussed. Chapter 5 gives the conclusion and gives the future direction of the work.
  • 21. Chapter 2 WBAN Standard (802.15.6) [1] With the decreasing size and increasing capability of electronic devices, it was in- evitable that small and portable devices would be developed for communications around human bodies. IEEE Standard 802.15.6 is for short-range, wireless commu- nications in the vicinity of, or inside, a human body (but not limited to humans) are specified in this standard [1]. It uses existing industrial scientific medical (ISM) bands as well as frequency bands approved by national medical and/or regulatory authorities. It also supports for quality of service (QoS), extremely low power, and data rates up to 10 Mbps is required while simultaneously complying with strict non-interference guidelines where needed. Previous personal area networks (PANs) do not meet the medical (proximity to human tissue) and relevant communication regulations for some application envi- ronments. They also do not support the combination of reliability, QoS, low power, data rate, and noninterference required to broadly address the breadth of body area network (BAN) applications. The standard defines a Medium Access Control (MAC) layer supporting three Physical (PHY) layers. The three PHY layers are narrowband (NB) PHY, ul- tra wideband (UWB) PHY and human body communication (HBC) PHY. In this thesis we will discuss ultra wideband physical layer (UWB-PHY) because of its a large scope for implementation opportunities for high performance, robustness, low complexity, and ultra low power operation. 10
  • 22. 2.1. Ultra wideband PHY specification 11 2.1 Ultra wideband PHY specification The design of UWB PHY is not only in order to improve the robustness of the WBAN, but also provides opportunities for implementation of high performance, low complexity and low power consumption operation. The interest of UWB lies in the fact that the signal power levels are in the order of those used in the MICS band, therefore providing safe power levels for the human body and low interference to other devices. The operating frequency bands of UWB PHY layer divided into two band groups: low band (3.244 to 4.742 GHz) and high band (6.240 to 10.23 GHz). The low band is divided into 3 channels (channel 0-2), high band divided into 8 channels (channel 3-10) and each channel bandwidth is of 499.2 MHz. An UWB device shall transmit in at least one of the specified band groups. A UWB device that implements the low band shall support channel 1, center frequency at 3.993 GHz and that implements the high band shall support channel 6, center frequency at 7.987 GHz. Remaining low bands and high bands are optional. The UWB PHY provides three levels of functionality, as follows [1]: • Activation and deactivation of the radio transceivers. • The PLCP constructs the PHY layer protocol data unit (PPDU) by concate- nating the synchronization header (SHR), physical layer header (PHR) and physical layer service data unit (PSDU), respectively. Moreover, the PPDU bits are converted into RF signals for transmission in the wireless medium. • The UWB PHY may provide clear channel assessment (CCA) indication to the MAC in order to verify activity in the wireless medium. There are two different types of UWB technologies included in the UWB PHY. Namely, impulse radio UWB (IR-UWB) and wideband frequency modulation (FM- UWB). The specification defines two modes of operation: default mode and high quality of service (QoS) mode, in which the default mode shall support IR-UWB as mandatory PHY and FM-UWB as optional PHY and the high QoS mode shall support IR-UWB as mandatory PHY. Table 2.1 gives the parameters of UWB-PHY
  • 23. 2.2. UWB-PHY Frame format 12 Table 2.1: Parameters of UWB-PHY [4] Modes of Operation PHY Data Rate Modulation Operation Band Default IR-UWB 487.5 kbps On-Off Signalling Low Band, High Band FM-UWB 250 kbps CP-BPSK, FM-UWB High Band QoS IR-UWB 487.5 DPSK Low Band, High Band There is not a mandatory pulse shape for IR-UWB. However, we can choose a pulse shape from a pool of pulse shapes. Two types of pulse waveforms supported, single pulse option where we transmit single pulse per symbol, burst pulse option where concatenation of pulses transmitted per symbol. 2.2 UWB-PHY Frame format The frame exchange format between the PHY and the MAC layer is specified by the physical layer convergence procedure (PLCP) sub-layer. The PLCP constructs the UWB PHY frame format or physical layer protocol data unit (PPDU) by concate- nating the synchronization header (SHR), physical layer header (PHR) and physical layer service data unit (PSDU) respectively which is shown in Fig. 2.1.
  • 24. 2.2. UWB-PHY Frame format 13 SHR PHR PSDU PHY Frame HCS BCH Parity Bits Rate r r r r r rLength B Pulse type HARQ SS km Transmit order Figure 2.1: Ultra wideband Physical layer Frame Format The SHR is used for timing synchronization and carrier offset recovery at the receiver. The PHR conveys necessary information about a packet that has been received. The last component of PPDU is PSDU which consists of MAC protocol data unit (MPDU) and BCH parity bits. The detailed description of SHR, PHR and PSDU is given in below. 2.2.1 Synchronization header (SHR) The synchronization header (SHR) shall be divided into two parts. The first part is the preamble, intended for timing synchronization, packet detection, and carrier frequency offset recovery. The preamble is generated by using a 63 bit length kasami sequence. Si Si Si Si ¯Si Preamble SHR SFD Figure 2.2: SHR [1] The second part is the start of frame delimiter (SFD) shown in Fig. 2.2 which is
  • 25. 2.2. UWB-PHY Frame format 14 used for frame synchronization [1]. The SFD is chosen to have low cross-correlation with the preamble such that the transition of correlation from preamble to SFD does not degrade the detection of the SFD. 2.2.2 Physical layer header (PHR) The PHR shall be added after the SHR to convey information about the PHY parameters that is needed at the receiver in order to decode the PSDU. The length of the PHR (Nheader) is 40 bits. The PHR consists of 24 bits of PHR frame, 4 bits of Head check sequence and 12 BCH parity bits. The Physical header is shown in the Fig. 2.3. PHY Frame HCS BCH Parity Bits 24 bits 4 bits 12 bits Figure 2.3: Physical header [1] The 24 bits of PHR frame structure is shown in the Fig. 2.4. R1 L0 L1 L2 L3 L4 L5 L6 L7 W1W0 H0 H1 KmR0 R2 r r r rr r B SS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122 23 MAC frame body length Data rate Pulse type HARQ Figure 2.4: PHR frame structure [1] In PHR frame bits 0-2 indicates the data rate. Bits 4-11 indicates the length of the frame body (L0 to L7), where L7 is the MSB and L0 is the LSB. Bit 14 shall en- code whether or not the packet is being transmitted in the burst (streaming) mode. The employed pulse shape for transmission is indicated by bits 15-16. The HARQ retransmission flow is controlled by bits 17-18. Bit 19 shall encode the scrambler seed. Bit 20 represents the constellation mapping used for on-off modulation. All other bits are reserved according to the standard.
  • 26. 2.2. UWB-PHY Frame format 15 2.2.3 Physical layer service data unit (PSDU) The PSDU contains the MAC protocol data unit (MPDU) plus channel code BCH parity bits in the default mode. In case of high QoS mode operation, the PSDU contains either the MPDU or BCH parity bits. The PSDU contains the MAC protocol data unit (MPDU) plus the channel code BCH parity bits. The MPDU shall be defined as the concatenation of the MAC header, MAC frame body, and FCS as illustrated in Figure 2.5. MAC Header MAC frame body FCS MPDU Figure 2.5: MPDU frame format [1] The formation of MPDU is by prepending the 7-octet MAC header to the MAC framebody and appending a 2-octet FCS to the result. The permitted length of the MAC frame body with in one packet should be no larger than 255 octets, and this information is contained in the PHY header in octets. The MPDU is forwarded to the scrambler in order to eliminate the dependency of the signal’s power spectrum upon the actual data. After scrambling the data, the scrambler forwards it to the BCH(63,51) encoder, which will add redundancy to the data in order to enable forward error correction in the receiver. The pad bits are then added in order to align on the symbol boundary. Finally, the resulting bit stream will be interleaved using a bit interleaver that removes burst errors which is shown in Fig. 2.6. Scrambler BCH Encoder Pad bits Bit interleaver PSDUMPDU Figure 2.6: PSDU construction [1]
  • 27. Chapter 3 Ultra Wideband Baseband Transmitter Design The block diagram of a compliant digital baseband transmitter for UWB PHY specification is shown in Fig. 3.1. In the transmitter block, the MPDU from the MAC layer is processed in the proposed transmitter baseband module to generate a PPDU packet. The baseband transmitter module can be divide into two parallel processing blocks. First block is uses for to create physical layer header from PHR frame and second block is for to generate PSDU from MPDU. To construct the PHR frame, the necessary information regarding physical layer parameters will be set based on the information provided by the MAC. At the receiver PHR frame should be recover with zero errors as the physical layer parameters is needed decode the PSDU properly. Generally channel adds some noise to the original message and corrupts some of the bits in the message. Therefore to increase robustness of the PHR frame, baseband transmitter is incorporating the header check sequence calculation (HCS) and BCH channel coding which can detect two errors. The header check sequence will append 4-bits to 24-bit PHR frame for error detection coding to the PHR frame. The BCH(40,28) channel code is derived from a BCH(63,51,t=2) code by appending 23 zero(or shortened) bits to the 28 information bits. After BCH encoding, the shortening bits has to remove and storing the 28 information bits 16
  • 28. 17 plus 12 parity bits which are added by the BCH encoder. The PHR frame is initially processed and then stored in a 40-bit register. The controller generates a PHR enable signal, which when active, pipes the output from the PHR register to the output. Once finished, the PSDU is provided to the next stage. PHR Frame Head Check Sequence MUX MUX Shortened BCH Encoder (40,28) Bit Interleaver MPDU FIFO Additive Scrambler BCH Encoder MUX MUX MUX 40 bit shift registers Pad Bits Shortening bits Shortening bits Transmitter Controller CLK generator 487 KHz Data from MAC layer Figure 3.1: Block diagram of UWB baseband transmitter Architecture The construction of PSDU from MPDU will be as follows. In data transmission state, one packet of the MPDU is generated by the MAC layer, it is fed into TX- FIFO and ready for transmission. From the FIFO the data goes to the scrambler, to eliminate possible long strings of 1s or 0s contained in the MPDU and so elimi- nating the dependency of the signals power spectrum upon the actual data. After scrambling the data goes to the channel coding block to increase robustness to the MPDU data. As the objective is to have low power consumption in WBAN devices, simple block codes are preferable. Therefore a simple BCH channel coding is used according to the standard. After encoding, pad bits shall be appended to the input bit stream to align on a symbol boundary. After adding the Pad bits we have to do interleaving to avoid burst errors. Interleaver distributes the burst errors into random errors.
  • 29. 3.1. PHR Construction 18 3.1 PHR Construction The PHR frame contains information about the data rate of the PSDU, length of the MAC frame body, pulse shape, burst mode, HARQ, and scrambler seed. The PHR frame is generated by the information given by MAC, which further passed to HCS block. The PHR construction is illustrated in Fig. 3.2. PHR frame HCS BCH Parity Bits PHR frame HCS BCH(40,28) Encoder Head check sequence calculation PHR frame Figure 3.2: Block diagram for PHR Construction 3.1.1 Head Check Sequence Generation The header check sequence will append 4-bits to 24-bit PHR frame for error detec- tion coding to the PHR frame. The HCS is implemented by using ones complement of the remainder generated by the modulo-2 division of the PHR information by the polynomial, as shown in equation 3.1. The registers in the HCS shall be initialized to all ones and its implementation is shown in Fig. 3.3. g(x) = 1 + x + x4 After HCS calculation, PHR frame 24 bits and 4-bits of HCS will go to the shortened BCH(40,28) encoder.
  • 30. 3.2. PSDU Construction 19 D D D D HCS3 HCS0 Serial Data Input HCS data output Figure 3.3: Block diagram of HCS implementation [1] 3.1.2 Shortened BCH Encoder The BCH(40,28) channel code is derived from a BCH(63,51,t=2) code by appending 23 zero(or shortened) bits to the 28 information bits. After BCH encoding, the shortening bits has to remove and storing the 28 information bits plus 12 parity bits which are added by the BCH encoder. The output of the PHR is shown in the Fig. 3.4 simulated in Xilinx tool. Figure 3.4: Output of PHR block In Fig. 3.4, f length denotes the MPDU length in octets, b is the burst mode information, m is the constellation mapping used for on-off modulation given by MAC. data out is the total 40 Physical Header (PHR) bits which contains 24 PHR frame bits, 4 HCS bits and 12 BCH parity bits. 3.2 PSDU Construction In data transmission state, one packet of the MPDU is generated by the MAC layer, it is fed into TXFIFO and ready for transmission. From the FIFO the data goes to the scrambler, to eliminate possible long strings of 1s or 0s contained in the MPDU.
  • 31. 3.2. PSDU Construction 20 3.2.1 Scrambler Scrambler eliminates the dependency of the signals power spectrum upon the actual data. An additive or synchronous scrambler with generator polynomial x[n] given in equation 3.2 shall be employed and its typical implementation is shown in Fig. 3.5. x(n) = 1 + x2 + x12 + x13 + x14 (3.1) Serial data outputserial data input D1 D2 D3 D10 D11 D12 D13 D14 Figure 3.5: Block diagram of a side-stream scrambler [1] The scrambler has two seed values which are the initial states of LFSR for each state and the seed used to set by the MAC layer. The MAC shall set the scrambler seed to SS = 0 in the PHR, when the UWB PHY is initialized. The scrambler seed shall be incremented using a 1-bit rollover counter for each frame sent by the UWB PHY. Table 3.1 defines the initialization vector for the additive scrambler as a function of the SS value. Table 3.1: Scrambler seed selection [1] Scrambler seed (SS) Initialization vector 0 0 0 1 0 1 1 1 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 At the receiver, the additive de-scrambler shall be initialized with the same initialization vector, used by the transmitter. The initialization vector is determined from the SS value in the PHY header (PHR) of the received frame. The output of the scrambler is shown in Fig. 3.6. The data in is the input data for the scrambler and the data out is the output data. The long strings of 1’s or 0’s
  • 32. 3.2. PSDU Construction 21 Figure 3.6: Output of Scrambler are eliminated in the data out. After scrambling the data goes to the BCH channel coding block to increase robustness to the MPDU data. 3.2.2 BCH encoder As the objective is to have low power consumption in WBAN devices, simple block codes are preferable. According to standard the channel coding is employed in baseband transmitter is BCH(n= 63, k = 51,t=2) which is low complexity design and able to detect and correct two errors in every 51 number of message bits. The generator polynomial employed for BCH(63,51) is given by equation 3.3, and its implementation is shown in Fig. 3.7. The BCH encoder will give a code- word of length 63 bits, in those 51 bits are message bits and 12 parity bits. The parity bits are determined by computing the remainder polynomial r(x) as shown in equation 3.4, where m(x) is the message polynomial m(x) = 50 i=0 mixi . The message polynomial is created as follows: m50 is the first bit of the message and m0 is the last bit of the message. The order of the parity bits is as follows: r11 is the first parity bit transmitted and r0 is the last parity bit transmitted. MUX D12D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 message bits Code word MUX Figure 3.7: Block diagram of a BCH encoder g(x) = 1 + x3 + x4 + x5 + x8 + x10 + x12 (3.2)
  • 33. 3.2. PSDU Construction 22 r(x) = 11 i=0 rixi = x12 m(x)modg(x) (3.3) The output of the BCH encoder is shown in the Fig. 3.8. In Fig. 3.8, data in is input data and data out is output data. From 3.8, we can observe the output of the first 51 bits are same as input bits. The next 12 bits are the parity bits added by the BCH encoder to correct upto 2 errors. Figure 3.8: Output of BCH encoder The total no of bits in MPDU is shown in equation 3.5. NMP DU = 8(NMACheader + NMACframebody + NF CS) (3.4) where NMACheader is the number of octets in the MAC header, NMACframebody is the number of octets in the MAC frame body, and NF CS is the number of octets of the FCS. The number of codewords (NCW ) in a frame is given by the equation 3.6. NCW = NMP DU k (3.5) The input sequence to the BCH encoder should be always multiple of 51 number of bits, otherwise at the last input sequence bits stuffing has to do to make it to sequence of 51 bits. Mathematically, if the rem(NMP DU ,k)=0, the last codeword requires Nbs bits stuffing which is shown in equation 3.7. Nbs = NCW k − NMP DU (3.6)
  • 34. 3.2. PSDU Construction 23 The transmitter controller has to find number of codewords and it has to find how many no of bits stuffing is required. Hence the total no of bits before encoding is given by equation 3.8. NP SDU = NMP DU + Nbs (3.7) After sending 51 information bits to BCH encoder, it will add 12 parity bits to it during that time the data coming from the FIFO has to stall for 12 clock pulses. After encoding, pad bits shall be appended at the end of every frame to align symbol boundary. 3.2.3 Pad Bits Pad bits shall be appended to the input bit stream to align on a symbol boundary [1]. The number of pad bits is given by equation 3.9, where M is the cardinality of the constellation of a given modulation scheme. The standard defined two constellation mappings, those are M=2,M=16. Npad = log2(M) NP SDU + (n − k)NCW log2(M) −[NP SDU + (n − k)NCW ] (3.8) If M=2, then number of pad bits equal to zero which is implicitly shown in equation 3.10 Npad = ⌈NP SDU + (n − k)NCW ⌉ − [NP SDU + (n − k)NCW ] (3.9) If M=16, using a mathematical deduction the number of pad bits depends only on Nbs because the other factors are multiple of 4. The output of Pad bits is shown in Fig. 3.9 In Fig. 3.9, data in is the incoming data, data out is the output data, and valid in, valid out are the corresponding valid bits. As we can see in the Fig. 3.9, zeros are appended in the end of frame before valid out goes to ’0’. After adding the Pad bits we have to do bit-interleaving.
  • 35. 3.2. PSDU Construction 24 Figure 3.9: Output of Pad bits 3.2.4 Bit-Interleaver Interleaving is to do avoid burst errors. Interleaver is to distribute burst errors into random errors. The address is generated internally with information about the block size from the Controller. The BCH encoder able to rectify only random errors and not the burst errors. The algebraic interleaver is is given in equation 3.11: (n) = nbsModNI (3.10) where NI is interleaver’s length. The interleaver’s length shall be set to 192 and seeding parameter bs set to 37. If Nrem=rem(NT ,NI )= 0, the last interleaver block, NI shall be set to Nrem. The interleaver consists of two banks, each a 192 bit register. At any given instance, one of the banks will act as the input bank and the other will act as the output bank. The input bank will take the input from the BCH coder, while the output is taken from the other bank. The input bank will be fully filled and the output bank will be fully drained at the same instance, and the roles will be reversed. Thus the interleaver introduces a 192 clock pulses latency while filling up the first 192-register bank. The output of the interleaver is shown in the Fig. 3.10. Figure 3.10: Output of Bit-Interleaver In Fig. 3.10, the size indicates the NI that has been sent by the transmitter controller, data in indicates the input data and data out is the output of the bit-
  • 36. 3.3. Transmitter Controller 25 interleaver. As PHR is available and is stored in a 40-bit register, phr signal from transmitter controller enables it and the output is connected to PHR 40-bit register. After PHR transmitted PSDU will be transmitted as the phr disables the register and output connected to PSDU thus reducing the latency to 152 clock pulses. Subsequently, SHR insertion will be done and should be modulated before trans- mission. 3.3 Transmitter Controller A synchronous pipeline is used in this architecture. A low complexity transmitter controller controls all the activities of the PHY layer. It controls the dataflow in the pipeline. The dataflow control is achieved by running enable lines to the various blocks with set of counters from the controller. It stalls the scrambler while the BCH coder generates the parity bits. The functions of the controller are stated below • Getting information about the MPDU to be transmitted, from the MAC. • Generating stall signals for the pipeline. • Calculation of interleaver’s block size. • Calculation of number of pad bits to be inserted and pad bit enable signal generation. • PHR and PSDU sequencing is controlled by this block.
  • 37. 3.3. Transmitter Controller 26 Counter=0,N=63,K=51,Scount=0 datalength=length of MPDU Start length=length-1 counter=counter+1 Counter==192 length=length+1 control==1 NO YES YES NO Scount==K Scount=Scount+1 control=0 Scount=Scount+1 Scount==N Scount=0 control=1 YES YES NO NO brem=K-Scount size=N-Scount brem=0 brem≤0 YES NO length≥3K Counter=0 YES length≥2K Scount≥K Scount≥60 YES NO YES NO intrsize=3N+size Nbs=3K-length YES length-brem ≤2K NO intrsize=3N+size Nbs=2K+brem-length Scount≥K length≥K length-brem ≤K YES YES YES NO NO YES NO intrsize=3N+size Nbs=2K+brem-length length≤brem Scount≥K intrsize=size Nbs=brem-length YES YES NO NO NO NO Figure 3.11: Flowchart of transmitter controller The working of the front-end controller is shown in the flowchart Fig 3.11. The flowchart shows how various stall signals are generated by the transmitter controller. The length in the flowchart has to be initialized with the total length of MPDU. As the BCH encoder in the PSDU construction (Fig. 2.6) adds 12 parity bits for every 51 data bits, a stall signal for data path should be generated for no loss of data. In the left part of flow chart, the Scount is a mod-63 counter that sets control to ’1’ when Scount is greater than 51. When control=1, the output of the scrambler will be stalled, while the BCH encoder outputs the parity bits. The bit interleaver size NI is not fixed, as the last block of the interleaver is set to Nrem, we have to pre-calculate the last block size from the data length to ensure the continuous flow of data. The right part of the flow chart calculates the last
  • 38. 3.4. Results and discussion 27 interleaving block length from the data length. counter signal checks the remaining data to be processed for the calculation of last interleaver block size from length after every 192 bits. The intrsize represents the size of the last interleaving block. The data is always not multiples of 51, so the last BCH block of the frame may stuff some zeros for the last BCH block to be completed. Nbs represents number of bits to be stuffed in the last BCH block. 3.4 Results and discussion The transmitter architecture is described in Verilog hardware descriptive language (HDL) and simulated in Xilinx software for functional verification. In this archi- tecture, the interleaver block has a latency of 192 clock cycles and therefore 40 bit PHR is inserted before the interleaver output such that the overall latency of the design reduces to 152 clock cycles. Once the designs are functionally verified, the designs are synthesized in Synopsys Design Compiler (DC). For synthesis, 130nm CMOS technology library is used. 3.4.1 Synthesis Report Technology=0.13 µm CMOS, Global Operating Voltage = 1.08V, Operating Frequency=487.5 kHz. The performance characteristics of transmitter architecture is tabulated in the Table 3.2.
  • 39. 3.4. Results and discussion 28 Table 3.2: Performance Characteristics of Baseband Transmitter Scrambler BCH Pad Inteleaver PSDU PHR PSDU & Encoder bits PHR Cells 42 80 16 1378 1649 356 2305 Area (µm2) 730.88 1050.88 235.52 22795.52 28719.36 4496.64 35244.8 Slack (ns) 5.66 6.30 2.33 7.99 8.22 6.13 8.22 Power (µW) 0.677 1.011 0.076 16.38 20.89 3.76 26.04 In the total power consumption of 26.04 µW, leakage power is 19.77 µW and the dynamic power is 6.27 µW. Since we are operating at a much low frequency (487.5 kHz) the leakage power is dominating dynamic power. If we use higher operating fre- quency, the dynamic power will increase. The interleaver consumes the most power (around 16 µ W) due to the two 192-bit banks and its associated address generation logic. It accounts for about 70 % of the total power consumption as in Table 3.2. Also the critical path delay 8.2 nsec is also for the address generation logic. The total design area estimation by synopsys design compiler is 35244.8µm2 of which Combinational area is 14886.41µm2 and Non-combinational area is 20358.39µm2
  • 40. Chapter 4 Ultra Wideband Baseband Receiver Design 4.1 Introduction Generally any signal after transmission gets erroneous because the channel adds some noise. The receiver ideally should get the original data from the erroneous signal. A general block diagram for receiver is shown in Fig. 4.1. RF Demodulator Synchronization Baseband Processing DA Converter Figure 4.1: General block diagram of Receiver An RF demodulator after receiving from the antenna converts the Radio fre- quency(RF) input to the baseband output. The baseband output from RF demod- ulator given to synchronization block to track the start of the frame. Using the Synchronous Header (SHR) inserted in the transmitter before RF modulator the synchronization block detects the start of the frame. Once the frame is detected the baseband processor of the receiver process the data and gives it to DA converter to 29
  • 41. 4.2. Receiver Architecture 30 get back the original transmitted data signal. 4.2 Receiver Architecture The block diagram of a compliant digital baseband Receiver for UWB PHY speci- fication is shown in Fig. 4.2. BCH De- coder(2) Receiver Controller CLK generator 487 KHz Data from Synchroniza- tion MUX De- MUX1 23-bit Register De- MUX2 HCS Length De- Interleaver & De-Padding BCH De- coder(1) De- Scrambler Scrambler Seed Figure 4.2: Block diagram of UWB baseband transmitter Architecture The first 40 bits of a every frame in the received data will be the Physical header (PHR). Therefore the first 40 bits should be processed separately to find the physical layer parameter information present in the PHR. And also those 40 bits (28 PHR-frame data bits and 12 BCH parity bits) should be given to BCH decoder (BCH Decoder (2) in Fig. 4.2) which needs 63 bits input (where in transmitter 0’s are stuffed & removed before transmission after calculation of its parity bits) to correct up to 2 errors. Thus a 23-bit shift register is used, which acts as FIFO initialized to 0 and is enabled after first 28 bits (PHR frame). So, the shift register appends the stuffed bits of the transmitter in the receiver and delays the actual data. A De-Multiplexer (De − MUX1 in Fig. 4.2 ) enabled by receiver controller, is used to enable that shift register after first 28 PHR bits. After BCH decoder,
  • 42. 4.3. Decoder HCS 31 the errors if any (not more than 2) will get corrected in 28 PHR frame bits and then given to Head check sequence (HCS) block for the error detection. If there is any error after BCH decoder, this HCS will detect the error but can not correct it. Therefore it will communicate back to the transmitter. If there are no errors after HCS, the important information like length, burst mode, constellation mapper etc. will be sent back to the receiver controller to generate other important control signals. After 40 bits the PSDU information starts, therefore it should be given to De- interleaver. Thus a again a De-Multiplexer (De − MUX2 in 4.2) is used after the 23-bit shift register used to enable the de-interleaver after first 40 bits. Again this De-Multiplexer is enabled by the receiver controller. De-padding also done in the same block. The De-interleaved data will be sent to BCH decoder (BCHDecoder(1) in 4.2) that can correct 2 bits in every 51 bits of data. If there are more than 2 errors in a set of 51 bits, then receiver communicate back to transmitter for re- transmission. The corrected data after the BCH decoder will be given back to the scrambler. The scrambler seed information is given the PHR after the HCS block. Thus the original data before the transmission can be retrieved in the receiver and given to a DA converter for the original signal. The details of all the blocks are discussed in the further sections in detail. 4.3 Decoder HCS The first 28 bits of the BCH decoder is given as input to the HCS block. The Head Check Sequence is same block as the transmitter (see 3.1.1). After the first 24 data- input bits passed through HCS block, the remainder stored in the registers of the HCS block should be done ex-or with the remaining 4 data-input bits. If the result of that ex-or is zero, then there is no error in the PHR frame and we can safely give out the physical layer parameters. If the result of that ex-or is non − zero, there is an error in PHR frame. Since HCS cannot correct the error it will indicate the error message to the transmitter. The output of the decoder HCS is shown in the Fig. 4.3. After 28 bits of PHR
  • 43. 4.4. BCH Decoder 32 the in enable went ’0’. And since there is no error in the given data, e is ’0’ and the parameters like length, ss are given as output. Figure 4.3: Output of Decoder HCS Thus the HCS block detects the error if any, and gives out the physical layer parameters to the controller and scrambler seed to the De-scrambler block. 4.4 BCH Decoder In coding theory the BCH codes form a class of cyclic error-correcting codes that are constructed using finite fields. BCH codes were invented in 1959 by Hocquenghem, and independently in 1960 by Bose and Ray-Chaudhuri. The abbreviation BCH comprises the initials of these inventors’ names. BCH codes operate over finite fields or Galois fields (GFs). BCH codes can be defined by two parameters that are code size n with k message bits and can correct t number of errors, in this case n=61 k=51 and t=2. 4.4.1 Basics of BCH code A t error correcting q-ary BCH code of length qm − 1 is a cyclic code whose roots include 2t consecutive powers of α, the primitive element of GF(qm ). There will be Binary BCH codes of q = 2 and Reed Solomon codes of m = 1 [5]. Therefore the BCH codes are summarized as follows: Block length n = 2m − 1 Number of parity check Bits n − k ≤ mt
  • 44. 4.4. BCH Decoder 33 Minimum Distance dmin ≥ 2t + 1 The generator polynomial (GP) of BCH codes is specified in terms of its roots from the Galois field GF(2m ) [13]. Let α be a primitive element of GF(2m ). The generator polynomial g(X) of the t-error correcting BCH code is the lowest-degree polynomial over GF(2) that has α, α2 , α3 , α4 , ......., α2t (4.1) as its roots (i.e., g(αi ) = 0for1 ≤ i ≤ 2t). Let φ(X) be the minimal polynomial of αi . Then, g(X) must be the least common multiple (LCM) of φ1(X), φ2(X), φ3(X), ........φ2t(X). g(X) = LCM(φ1(X), φ2(X), φ3(X), ........φ2t(X)) (4.2) For (63,51,2) BCH codes, let α be the primitive element of GF(26 ) , 1+α+α6 = 0 is primitive polynomial. The generator polynomial (GP) by g(X) = LCM(φ1(X), φ3(X)) because φ1(X), φ3(X) are two distinct irreducible polynomials g(X) = φ1(X) ∗ φ3(X) = (1 + x + x6 ) ∗ (1 + x + x2 + x5 + x6 ) = 1 + x3 + x4 + x5 + x8 + x10 + x12 same as 3.3 Before going into the details of BCH decoding one need to know basics of Galois fields as the BCH codes operate over Galois fields. 4.4.2 Galois fields Finite fields are often referred to in the form GF(2n ). The G stands for Galois who originated much of field theory, while F stands for field. The 2 means that the field is described over binary number while n is the degree of the Generator Polynomial (GP). Such a field has 2n elements in it [14]. We will understand the Galois fields by seeing the following example of GF(23 ): The primitive polynomial of GF(23 ) is α3 + α + 1 = 0. What’s special about these fields is that the elements obey normal laws of maths insofar as they can be
  • 45. 4.4. BCH Decoder 34 added, multiplied or divided to yeild another member of the field. Table 4.1 shows how the field is constructed. Table 4.1: Construction of GF(23 ) α calculation Numeric value α2 α1 α0 α0 1 0 0 1 (1) α1 α 0 1 0 (2) α2 α2 1 0 0 (4) α3 α + 1 1 1 0 (6) α4 α ∗ (α + 1) = α2 + α 0 1 1 (3) α5 α ∗ (α2 + α) = α3 + α2 = α2 + α + 1 1 1 1 (7) α6 α2 ∗ α4 = α2 ∗ (α2 + α) = α2 + 1 1 0 1 (5) α7 α ∗ (α2 + 1) = (α + 1) + α = α 0 0 1 (1) α8 α ∗ 1 = α 0 1 0 (2) There is no α3 term but, from the primitive polynomial α3 + α + 1 = 0, we can see that α3 = α + 1 remembering in GFs 1 = −1. Substituting ’folds’ α3 back into bottom 3 bits. Notice that α7 = α0 (= 1) and the sequence starts to repeat (i.e. α8 = α1 ). A reducible or non-primitive polynomial does not produce this maximal sequence. 4.4.3 Manipulating Field Elements In order to do useful things with finite fields it is necessary to understand how to use them. Addition : To add two elements, we have to do simple bit-wise ex-or (XOR) op- eration. Considering same example of GF(23 ) in the Table 4.1 α2 + α5 = α2 + α2 + α + 1 = α + 1 = α3 or in binary
  • 46. 4.4. BCH Decoder 35 1 0 0 1 1 1 ⊕ 0 1 1 Multiplying with α, α2 : Multiplying is a just a matter of adding indices or powers in modulo-2n−1 . However, sometimes we have to multiply an element with α or α2 without actually knowing the element index in Galois field. For multiplying with α, we have to right shift the entire polynomial by one bit and then we have to create a polynomial according to the last bit of the original polynomial and ex-or (XOR) with the shifted polynomial. Considering same exam- ple of GF(23 ) now Say we have to multiply 101 with α Right shift 101 by one bit gives 010 and since the last bit is ’1’,so we have to ex-or it with α + 1 (110) 1 0 1 * α 0 1 0 1 1 0 ⊕ 1 0 0 From Table 4.1, 101 corresponds to α6 and α6 ∗ α = α7 = 100 Similar procedure to be followed if we have to multiply with α2 , shift by two bits and create polynomial with necessary positions according to last two bits of the original polynomial and ex-or it with the shifted polynomial. 4.4.4 Decoding BCH codes There are many algorithms which have been developed for decoding BCH codes. A general approach of decoding BCH is as follows: 1. Computation of Syndrome 2. Determination of Error Locator Polynomial, whose roots is an indication of where roots are. 3. Finding roots of the Error Locator Polynomial. This is actually done using
  • 47. 4.4. BCH Decoder 36 Chein Search algorithm, which is an exhaustive search over all the fields of elements. 4.4.5 Computation of Syndrome The syndrome calculator is the first module at the decoder also, the design of this module is almost same for all the BCH code decoder architecture. The input to this module is corrupted codeword. We start with the codeword, received word polynomial and error equations c = (c0, c1, ......cn−1) (4.3) c(x) = c0 + c1x + ......cn−1xn−1 , (4.4) c(α) = ...... = c(α2t ) = 0, (4.5) r(x) = r0 + r1x + ......rn−1xn−1 , (4.6) e(x) = e0 + e1x + ......en−1xn−1 , (4.7) And the received polynomial r(x) = c(x) + e(x), we will have syndromes gener- ated as the received polynomial r(x) is corrupted with error e(x) Sj = r(αj ) = c(αj ) + e(αj ), where j = 1, 2, ....2t (4.8) but from Eqn.(4.5) c(αj ) = 0 Therefore, Sj = e(αj ) = n−1 k=0 ekαjk , where j = 1, 2, ....2t (4.9) The hardware implementation of the syndrome is shown in the Fig. 4.4. From the Eqn. 4.8 the syndromes are nothing but r(αj ), that can be imple- mented as follows: Sj = r(αj ) = r63(α63 ) + r62(α62 ) + ............... + r1(α) + r0 = [[[r63(α) + r62]α + r61]α + .......... + r1]α + r0
  • 48. 4.4. BCH Decoder 37 D αi r0,r1,r2,........rn−1 Si Figure 4.4: Hardware implementation of the syndrome For generating S1, α is multiplied i number of times for rith bit, the multiplica- tion with α is discussed in the previous section. Since (63,51) BCH code is double error correcting code (t = 2), four syndromes can be generated. Ideally syndromes should be 0 with out any error. The output of the syndrome is shown in the Fig. 4.4.5. For our understanding, we have given the received polynomial without any error so that the syndromes generated will be ′ 0′ . Figure 4.5: Output of Syndrome block Therefore the syndromes S1, S2, S3, S4 are available only after all the 63 bits. Thus the first bit has the delay of 63 clock pulses for the calculation of syndromes. 4.4.6 The Error Locator Polynomial The syndromes are non zero only due to error polynomial (4.9). Then, we have Sj = v l=0 Xj l (4.10)
  • 49. 4.4. BCH Decoder 38 where Xl are Error Locators, v is the number of errors in the received polynomial (4.6). S1 = X1 + X2 + .......Xv S2 = X2 1 + X2 2 + .......X2 v . . (4.11) . S2t = X2t 1 + X2t 2 + .......X2t v The above equations are said to be power-sum symmetric functions. This gives us 2t equations in the v unknown error locators. In principle this set of non-linear equa- tions could be solved by exhaustive search, but this is computationally unattractive. Rather than attempting to solve these non-linear equations directly, a new poly- nomial is introduced, the error locator polynomial, which casts the problem in a different, and more tractable. The error locator polynomial is defined as [15]: λ(x) = v l=1 (1 − Xlx) = λvxv + λv−1xv−1 + ....... + λ1x + λ0 (4.12) By Eqn. 4.12, if x = X− l 1 then λ(x) = 0; that is, the roots of the error locator polynomial are at the reciprocals of the error locators. There are two commonly used methods for solving the key equation in this form. They are Euclid’s Algorithm and the Berlekamp Massey Algorithm. The latter is more efficient for hardware implementation is effective than previous one. Inversion-less Berlekamp Massey Algorithm The Berlekamp Massey Algorithm needs polynomial inversion, and polynomial in- version will be a power hungry block. So we have chosen Inversion-less version of Berlekamp Massey Algorithm given below [5]:
  • 50. 4.4. BCH Decoder 39 Table 4.2: Inversion-less version of Berlekamp-Massey alogorithm [5] begin l := 0; n := 0; k := −1; λ(z) := 1; D(z) := zλ(z); δ∗ := 1; while(n<2t)do begin δ := l l=0 λiSn−i; if(δ = 0)then begin λ∗ (z) = δ∗ ∗ λ(z) + δ ∗ D(z); if(l<n − k) begin l∗ := n − k; k := n − l; δ∗ := δ; D(z) := λ(z); l := l∗ ; end λ(z) := λ∗ (z); end D(z) := zD(z); n = n + 1; end end By substituting n = 63, k = 51, t = 2 and l varies from 0 to 3 in the inversion-
  • 51. 4.4. BCH Decoder 40 less Berlekamp Massey algorithm in Table 4.2, we will get the error correcting polynomial as: λ2(z2 ) + λ1(z) + λ0 = (S3 + S1S2)(z2 ) + S2 1 (z) + S1 (4.13) =⇒ λ2 = S3 + S1S2 (4.14) λ1 = S2 1 (4.15) λ0 = S1 (4.16) Therefore, now we have to calculate S1S2 and S2 1 (from 4.14, 4.15)which requires polynomial multiplication. One simple solution is to store all the 63 6-bit polynomial values in Read only memory (ROM) and adding the indices of multiplicands gives the multiplied value. But for our WBAN applications, system should be power efficient and again ROM may consume a lot of power. Proposed Galois polynomial multiplication For (63, 51, 2) BCH codes, α is the primitive element of GF(26 ), the 1 + α + α6 = 0 is the primitive polynomial. Using the primitive polynomial, we implemented the polynomial multiplication of Galois Fields by our proposed multiplication method which is shown in Fig. 4.4.6.
  • 52. 4.4. BCH Decoder 41 a5a4a3a2a1a0 b5b4b3b2b1b0 y5 y4 y3 y2 y1 y0 b0a3 b1a2 b2a1 b0a2 b3a0 b1a1 b0a4 b0a4 b2a0 b0a1 b1a3 b1a3 b0a3 b1a0 b2a2 b2a2 b1a2 b0a1 b0a0 b3a1 b3a1 b2a1 b1a1 b0a1 b4a0 b4a0 b3a0 b2a0 b1a0 b0a0 b5a5 b4a5 b3a5 b2a5 b1a5 b0a5 b5a4 b4a4 b3a4 b2a4 b1a4 b0a4 b5a3 b4a3 b3a3 b2a3 b1a3 b0a3 b5a2 b4a2 b3a2 b2a2 b1a2 b0a2 b5a1 b4a1 b3a1 b2a1 b1a1 b0a1 b5a0 b4a0 b3a0 b2a0 b1a0 b0a0 Figure 4.6: Proposed Multiplication for Galois field polynomials Let the syndromes S1 = a5a4a3a2a1a0, S2 = b5b4b3b2b1b0 are the syndromes generated from the syndrome block and if Y = y5y4y3y2y1y0 = S1 ∗ S2, From Fig. 4.4.6, Y calculated as if p1 = b0 ⊕ b5 p2 = b0 ⊕ b1 p3 = b1 ⊕ b2 p4 = b2 ⊕ b3 p5 = b3 ⊕ b4
  • 53. 4.4. BCH Decoder 42 then, y5 = a5b5 ⊕ a4b0 ⊕ a3b1 ⊕ a2b2 ⊕ a1b3 ⊕ a0b4 y4 = a5b4 ⊕ a4p1 ⊕ a3p2 ⊕ a2p3 ⊕ a1p4 ⊕ a0p5 y3 = a5b3 ⊕ a4b4 ⊕ a3p1 ⊕ a2p2 ⊕ a1p3 ⊕ a0p4 y2 = a5b2 ⊕ a4b3 ⊕ a3b4 ⊕ a2p1 ⊕ a1p2 ⊕ a0p3 (4.17) y1 = a5b1 ⊕ a4b2 ⊕ a3b3 ⊕ a2b4 ⊕ a1p1 ⊕ a0p2 y0 = a5b0 ⊕ a4b1 ⊕ a3b2 ⊕ a2b3 ⊕ a1b4 ⊕ a0p1 The output of the proposed multiplier is shown in the Fig. 4.4.6. We have given α18 (6′ b111100) as one input and α21 (6′ b110111) as the other. The output should be α(18+21) and the output from the simulation results is showing exactly thee same 6′ b011011 (α39 ). Figure 4.7: Output of proposed multiplier block Thus 64 ∗ 6 ROM is reduced to AND gates, OR gates and EX − OR gates and thereby decreasing power consumption. Likewise we should calculate S2 1 for λ1 (from Eqn. 4.15) by substituting S2 by S1 S2 1 = S1 ∗ S1 = y5y4y3y2y1y0,
  • 54. 4.4. BCH Decoder 43 Substituting S1 for S2 in Eqn. 4.18 y5 = a5 ⊕ a2 y4 = a2 y3 = a4 ⊕ a1 y2 = a1 (4.18) y1 = a3 ⊕ a0 y0 = a0 The output of the error location polynomial is shown in the Fig. 4.4.6. Figure 4.8: Output of Error Locator Polynomial Block Let the syndromes generated by the Syndrome Generator block are S1 = 6′ b000010 = α4 , S2 = 6′ b001100 = α8 and S3 = 6′ b000001 = α5 . From Eqn.s 4.14, 4.15, 4.16, the output should be α31 (6′ b101001), α8 (6′ b001100), α4 (6′ b000010) respectively which is same from the simulation results also from Fig. 4.4.6. Finally the error correcting polynomial coefficients (Eqns. 4.14, 4.15, 4.16) are generated with the use of proposed Galois field multiplier and sent for finding its roots to Chein Search. 4.4.7 Chein Search The next step is to find the roots of the error locator polynomial. Being a finite field, we can examine every element of the field to determine if it is a root or not. This is the basic idea of the chein search algorithm and is most efficient for finding roots.
  • 55. 4.4. BCH Decoder 44 The hardware implementation of the chein search algorithm is shown in Fig. 4.9 MUX D MUX D MUX Dα λ1 α2 λ2 αt λt λ0 Figure 4.9: Implementation of Chein Search Algorithm The output of the Chein Search block is shown in the Fig. 4.10. Figure 4.10: Output of Chein Search Algorithm In Fig. 4.10, r1 and r2 are the root location of the error locator polynomial. As the chein search algorithm searches each and every element in the finite field, a counter initialized with the chein search block itself. Therefore if a root is encoun- tered in the search, the root location will be the counter value. As the chein search algorithm checks for each and every element of the field, the delay for the entire search will be n clock pulses after the error locator polynomial coefficients is given, which is 63 clock pulses in this case. 4.4.8 Architecture of BCH Decoder The overall architecture of the BCH decoder is shown in Fig. 4.11.
  • 56. 4.4. BCH Decoder 45 BCH Control Syndrome Generator Key Equation Solver Chein Search Error Correction BCH FIFO buffer R D e S1,S2,S3 λ1,λ2,λ3 r1,r2 Figure 4.11: Overall architecture of the BCH decoder The data received R is sent serially to the Syndrome Generator block. It outputs syndrome values (S1, S2, S3) for each 63 bits, so the syndrome values passed to Key Equation Solver once after every 63 bits controlled by BCH Control block. The Key Equation Solver block outputs error locator polynomial coefficients (λ1, λ2, λ3). The Chein Search block calculates the roots of error locator polynomial (r1, r2) and sends it to Error Correction block for error correction. The Syndrome Generator find syndromes only after a delay of 63 clock pulses and Chein Search find its roots after another 63 clock pulses. So the data should be stored until it is corrected. So there is BCH FIFO Buffer to store the corrupted data and errors are corrected, we will pass the data to output. If there are more than 2 errors, as the decoder cannot correct the errors, an error message e is generated. The output of the BCH decoder is shown in the Fig. 4.12.
  • 57. 4.5. De-interleaver 46 Figure 4.12: Output of the BCH decoder In Fig. 4.12 d out is the output data that has a delay of 126 clock pulses alto- gether. For every 63 clock pulses syndromes (S1, S2, S3), error locator polynomial coefficients (λ1, λ2, λ3) gets updated. The output of the BCH decoder is given to the de-interleaver. 4.5 De-interleaver The De-interleaver block is similar to the Interleaver block in the transmitter (see 3.2.4). The algorithm for the address generation for the de-interleaver block is shown in Fig. 4.13.
  • 58. 4.6. De-scrambler 47 Counter==192 NOYES Counter=0,update=0 Start counter=counter+1 update=0 Addr=Addr+bs Addr>NI NOYES NI Addr= Addr-NI Addr= Addr update==1 Update bs YES NI>37 NOYES bs=37 bs>NI YES NO bs=bs-NI Counter=0; update=1 Figure 4.13: Algorithm for De-interleaver address generation From the Fig. 4.13 the address increments bs every clock pulse. If the address is greater than NI then address reduces by NI. The address increment bs will get updated after every 192 bits. 4.6 De-scrambler The de-scrambler is also the same block as the transmitter (see 3.2.2). As the scrambler is nothing but ex-or operation of data with a polynomial; again the ex-or operation of polynomial with received data gives back the original data. This can be explained simply by following property of ex-or: a ⊕ b = c
  • 59. 4.7. Results and Discussion 48 c ⊕ b = a 4.7 Results and Discussion The receiver architecture is described in Verilog hardware descriptive language (HDL) and simulated in Xilinx software for functional verification. In this archi- tecture, the de-interleaver block has a latency of 192 clock cycles and BCH decoder has latency of 126 clock cycles and therefore the overall latency of the design is 318 clock cycles. Once the designs are functionally verified, the designs are synthesized in Synopsys Design Compiler (DC). For synthesis, 130nm CMOS technology library is used. 4.7.1 Synthesis Report Technology=0.13 µm CMOS, Global Operating Voltage = 1.08V, Operating Frequency=487.5 kHz. The performance characteristics of receiver architecture is tabulated in the Table 4.3. Table 4.3: Performance Characteristics of Baseband Receiver Decoder BCH De-Inteleaver De-Scrambler Total HCS Encoder Decoder Cells 215 2262 1977 58 4215 Area µm2 2849.28 24277.76 21797.12 901.24 50170.78 Slack ns 3.3 9.32 6.05 1.05 9.32 Power µW 2.26 13.17 19.92 0.84 47.78 In the total power consumption of 47.78 µW, leakage power is 34.94 µW and the dynamic power is 12.83 µW. Since we are operating at a much low frequency (487.5
  • 60. 4.7. Results and Discussion 49 kHz) the leakage power is dominating dynamic power. If we use higher operating frequency, the dynamic power will increase. The interleaver consumes the most power (around 20 µ W) due to the three 192-bit banks and its associated address generation logic. The three 192 bit registers are used to ensure no loss of data at the start of the frame. We read start of frame data into 3rd 192 bit register as the first two 192-register banks may be busy in processing the previous frame. It accounts for about 45 % of the total power consumption as in Table 4.3. The BCH decoder is also one of the major power consuming block. The BCH FIFO of 126 bits depth and also complexion of logic is the reason of its high power. As there are two BCH decoder blocks as shown in Fig. 4.2, BCH decoder consumes about 40 % of total power consumption. Also the critical path delay 9.2 nsec is also for the BCH decoder due to its combinational logic of key equation solver. The total design area estimation by synopsys design compiler is 50170.78µm2 of which Combinational area is 23729.44µm2 and Non-combinational area is 26440.79µm2
  • 61. Chapter 5 Conclusion and Future Direction Architectures for UWB-PHY layer transmitter-receiver baseband processor for 802.15.6 WBAN standard were designed and synthesized. Also, their performance charac- teristics were extracted from the synthesis tool (Synopsys DC). To the best of our knowledge it is the first time a baseband architecture for UWB-PHY for 802.15.6 standard is designed. Therefore a fair comparison is difficult but a comparison with the architectures where one can find similar blocks is carried out. The comparison of this work with the available architectures is presented in table 5.1. The power estimates of various architectures in the literature and also gives the differences between the 802.15.6 WBAN standard and that architecture is given. As the literature available is not according to the standard, we gave the blocks that are included and excluded w.r.t standard in Table 5.1. The power consumption of the transmitter is the smallest of all the architectures even though it has a 192-bit interleaver and designed according to standard, but the receiver power consumption is a bit higher than some of the architectures. This receiver power consumption is high as it has to meet the timing constraints of the 802.15.6 standard requirements. In the receiver de-interleaver uses three 192-bit register banks and two BCH decoder blocks as explained in the previous chapter. 50
  • 62. 51 Table 5.1: Comparisons of various Architectures Paper Technology Supply Data Power Included Excluded Used Voltage Rate Consumption [9] 0.18 µm 1.1 V 4 MHz 34 µW for Tx. Hamming Encoder Scrambler 39.6 µW for Rx. Manchester Encoder BCH Encoder [10] 0.18 µm 1.8 V 250 kHz 240.24 µW for Tx. Hamming coding Scrambler 202.34 µW for Rx. SPI Interface BCH Encoder [11] 0.13 µm 1.1 V 250 kHz 35 µW for Tx. Manchester Coding PHR 42 µW for Rx. 192-bit interleaver [11] 0.13 µm 1.1 V 250 kHz 34 µW for Tx. Manchester Coding PHR 38 µW for Rx. LDPC encoding 192-bit interleaver [16] 0.13 µm 1.08 V 487 kHz 25.46 µW for Tx. All the 30.34 µW for Rx. blocks in standard None This 0.13 µm 1.08 V 487 kHz 26.04 µW for Tx. All the Work 47.7 µW for Rx. blocks in standard None As one can observe from the designs the interleaver, de-interleaver and BCH decoder are the most power consuming blocks. Therefore in future, we should focus more on those blocks to reduce the power of those blocks.
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