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Implementation of hybrid wave pipelined 2 d dwt using asic

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  • 1. Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC AIM: The main aim of the project is to design and implement “Implementation of Hybrid Wave-pipelined 2D DWT Using ASIC”. ABSTRACT: In the literature, pipelined systems require clock routing complexity and clock skews between different parts of the system. A circuit design technique such as wave-pipelining achieves high speed without the above limitations. Wavepipelined circuit dispenses with the need for registers for storing the intermediate results and instead uses the inherent capacitance at the input to the various blocks. This results in lower power at the cost of speed. Hybrid scheme is aimed at combining the advantages of both pipelining and wave-pipelining. Hence, we proposed the design and implementation of hybrid wave pipelined 2D-DWT using lifting scheme in this paper. For the purpose of comparison, non pipelined scheme as well as the scheme with pipelining within the blocks and between the blocks is implemented. From the results, it is concluded that the hybrid WP is faster than non-pipelined and requires less area, less clock routing complexity and lower power than pipelined. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 2. BLOCK DIAGRAM: Fig: Overall block diagram of one level 2D DWT TOOLS: Xilinx 9.2ISE, Modelsim 6.4c. APPLICATION ADVANTAGES:  The 9/7 bi-orthogonal filters implemented on Xilinx SOC device using the lifting scheme with the following three multipliers: with BW-PKCM, BWKCM and hybrid WP-P BW-KCM. From the implementation results, it is verified that hybrid WP-P BW-KCM is faster compared to non pipelined BW-KCM and is register efficient, and less clock routing complexity compared to BW-PKCM. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 3.  The one level 2D DWT scheme is also implemented, in ASICs using pipelining and non-pipelining. It can be extended for whybrid WP for future work. REFERENCES: • G. Martin and H. Chang, “System-on-Chip design,” Proc. of Intl. conf. on ASIC, pp.12. • B. A. Draper, J. R. Beveridge, A. P. W. Bohm, C. Ross, and M. Chawathe, “Accelerated image processing on FPGAs,” IEEE 8 VLSI Design Transactions on Image Processing, vol. 12, no. 12, pp. 1543– 1551. • G. Lakshminarayanan, B. Venkataramani, J. S. Kumar, A. K. Yousuf, and G. Sriram, “Design and FPGA implementation of image block encoders with 2D-DWT,” in Proceedings of IEEE Conference on Convergent Technologies for Asia-Pacific Region (TENCON ’03), vol. 3, pp. 1015–1019, Bangalore, India. • K. K. Parhi, VLSI Signal Processing Systems, JohnWiley&Sons, New York, NY, USA. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 4. • J. Nyathi and J. G. Delgado-Frias, “A Hybrid wave-pipelined network router,” IEEE Transactions on Circuits and Systems-I, Fundamental Theory and Applications, vol. 49, no. 12, pp. 1764–1772. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur