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signals to determine the sign extension signals. Fig. 2 showsan overview of the partial product array for an 8 × 8multiplier. The sign extension circuitry developed in [22]and [23]. The conventional MBE partial product array hastwo drawbacks: 1) an additional partial product term at the(n-2)th bit position; 2) poor performance at the LSB-part. Toremedy the two drawbacks, the LSB part of the partialproduct array is modified. Referring to Fig. 2a, the Row_LSB(gray circle) and the Neg_cin terms are combined and furthersimplified using Boolean minimization. The new equationsfor the Row_LSB and Neg_cin can be written as (1) and (2),respectively.TABLE 1: Truth Table of MBE Scheme.Row_ LSBi = yLSB (x2i-1 ⊕ x2i ) (1)(2)Fig. 1. The Encoder and Decoder for the new MBE scheme. (a) Simpleencoder (b) Decoder.The Fig. 2(a) has widely been adopted in parallelmultipliers since it can reduce the number of partial productrows to be added by half, thus reducing the size andenhancing the speed of the reduction tree. However, asshown in Fig. 1(a), the conventional MBE algorithmgenerates n/2 + 1 partial product rows rather than n/2 due tothe extra partial product bit (neg bit) at the least significantbit position of each partial product row for negativeencoding, leading to an irregular partial product array and acomplex reduction tree. Therefore, the Modified Boothmultipliers with a regular partial product array [2] produce avery regular partial product array, as shown in Fig. 3. Notonly each negi is shifted left and replaced by ci but also thelast neg bit is removed. This approach reduces the partialproduct rows from n/2 + 1 to n/2 by incorporating the lastneg bit into the sign extension bits of the first partial productrow, and almost no overhead is introduced to the partialproduct generator. More regular partial product array andfewer partial product rows result in a small and fast reductiontree, so that the area, delay, and power of MBE multiplierscan further be reduced.0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1bi+1 bi bi-1 value0112-2-1-10X1_a10011001X2_b01100110Z11000011Neg00001111Neg_cini = x2i+1 (x2i-1 + x2i ) (x2i-1 +yLSB ) (x2i + yLSB )Fig.3.The partial product array for 8×8 multiplier.p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p02 1 0 p07 p06 p05 p04 p03 p02 p01 001 s1 p17 p16 p15 p14 p13 p12 p11 10 c01 s2 p27 p26 p25 p24 p23 p22 p21 10 c11 s3 p37 p36 p35 p34 p33 p32 p31 20 c2Fig. 2. 8× 8 MBE partial product array. (a) Traditional MBE partialproductarray. (b) New MBE partial product array.yj yj-1PijNegX1_aX2_bZx2i-1X2_bX2_aZx2ix2ix2i+1x2i-1x2i(a) (b)666555000666555000
3.
III. PROPOSED SUMBE MULTIPLIERThe main goal of this paper is to design and implement8×8 multiplier for signed and unsigned numbers using MBEtechnique. Table 2 shows the truth table of MBE scheme.From table 2 the MBE logic diagram is implemented asshown in Fig. 4. Using the MBE logic and considering otherconditions the Boolean expression for one bit partial productgenerator is given by the equation 3.TABLE 2: Truth Table of MBE Scheme.Equation 3 is implemented as shown in Fig. 5. TheSUMBE multiplier does not separately consider theencoder and the decoder logic, but instead implementedas a single unit called partial product generator as shownin Fig. 5. The negative partial products are converted into 2’scomplement by adding a negate (Ni) bit. An expression fornegate bit is given by the Boolean equation 4. This equationis implemented as shown in Fig. 6. The required signedextension to convert 2’s complement signed multiplier intoboth signed-unsigned multiplier is given by the equations 5and 6. For Boolean equations 5 and 6 the correspondinglogic diagram is shown in Fig. 7.a8 = s_u a7 (5)b8 = s_u b7 (6)The working principle of sign extension that convertssigned multiplier signed-unsigned multiplier as follows. Onebit control signal called signed-unsigned (s_u) bit is used toindicate whether the multiplication operation is signed(3)Pij= (ai⊕ bi+1+bi-1⊕ bi ) ( bi-1⊕ bi+1+bi⊕ bi+1+ bi-1⊕ bi )s_ub7a7b8a8Fig. 7. Logic diagram of sign converter.0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1bi+1 bi bi-1 value0112-2-1-10X1_a10011001X2_a01100110Z11000011Neg00001110Fig. 5. Logic diagram of 1-bit partial product generatorPijbi-1 biai bi+1 bi bi+1ai-1 bi+1bi-1 biNibi+1bi-1biFig. 6. Logic diagram of negate bit generater.bi bi-1 bi bi+1 bi bi-1X1_a X2_bZFig. 4. Logic diagram of MBE.Ni = bi+1 ( bi-1 bi ) (4)666555111666555111
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number or unsigned number. When Sign-unsign s_u) = 0, itindicates unsigned number multiplication, and when s_u = 1,it indicates signed number multiplication. It is required thatwhen the operation is unsigned multiplication the signextended bit of both multiplicand and multiplier should beextended with 0, that is a8 = a9 = b8 = b9 = 0. It is requiredthat when the operation is signed multiplication the signextended bit depends on whether the multiplicand is negativeor the multiplier is negative or both the operands arenegative. For this when the multiplicand operand is negativeand muitplier operand is positive the sign extended bitsshould be generated are s_u = 1, a7 =1, b7 = 0, a8 = a9 =1,and b8 = b9 =0. And when the multiplicand operand ispositive and muitplier operand is negative the sign extendedbits should be generated are s_u = 1, a7 =0, , b7 = 1, a8 = a9=0, and b8 = b9 =1. Table 3 shows the SUMBE multiplieroperation.Fig. 8 shows the partial products generated by partaialproduct generater circuit which is shown in Fig. 5. There are5-partial products with sign extension and negate bit Ni. Allthe 5-partial products are generated in parallel.In Fig. 8 there are 5-partial products namely X1, X2, X3,X4 and X5. These partial products are added by the CarrySave Adders (CSA) and the final stage is Carry Lookahead(CLA) adder as shown in Fig. 9. Each CSA adder takesthree inputs and produse sum and carry in parallel. There arethree CSAs, five partial products are added by the CSA treeand finally when there are only two outputs left out thenfinally CLA adder is used to produce the final result.Assuming each gate delay an unit delay, including partialproduct generator circuit delay, then the total through theCSA and CLA is 3+4 = 7 Unit delay. Thus with present VeryLarge Scale Integration (VLSI) the total delay is estimatedaround 0.7 nanosecond and the multiplier operates at gigahertz frequency.IV. SIMULATION RESULTSVerilog code is written to generate the required hardwareand to produce the partial product, for CSA adder, and CLAadder. After the successful compilation the RTL viewgenerated is shown in Fig.10.Fig. 10: RTL view of 8×8 signed-unsigned multiplier.Table 3: SUMBE operationSign-unsign Type of operation0 Unsigned multiplication1 Signed multiplicationCSA1CSA2CSA3CLAP = A×BX3 X2 X1X4X5Fig. 9. Partial product adder logic.X1X4X5X2X3Fig. 8. 8×8 multiplier for signed-unsigned number.p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0a7 a6 a5 a4 a3 a2 a1 a0b7 b6 b5 b4 b3 b2 b1 b0p08p08 p08 p07 p06 p05 p04 p03 p02 p01 p001 p18p17 p16 p15 p14 p13 p12 p11 p10 N01 p28p27 p26p25 p24p23 p22p21 p20 N11 p38 p37p36p35 p34 p33 p32 p31 p30 N2P47p46 p45 p44 p43 p42 p41p40 N3666555222666555222
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Fig. 11 shows the simulation result of signed-unsignednumbers. Fig. 11(a) shows the simulation result of signed-unsigned number in binary. Here when the control signal s_u= 0, the 8-bit operands are considered as unsigned and theproduct of 11111111 × 11111111 = 1111111000000001.And when the control signal s_u = 1, the 8-bit operands areconsidered as signed and the product of 11111111 ×11111111 = 0000000000000001. Fig. 11(b) shows thesimulation result of unsigned operands in decimal i.e whenthe control signal s_u = 0, the 8-bit operands are consideredas unsigned and the product of 11111111 (255) × 11111111(255) = 1111111000000001 (65025), and when the controlsignal s_u = 1, the 8-bit operands are considered as signedand the product of 11111111 (-1) × 11111111 (-1) =0000000000000001 (+1).Fig. 11(c) and Fig. 11(d) shows the simulation result ofsigned- unsigned number in binary and decimal respectively.When s_u = 0, the 8-bit operands are unsigned and theproduct of 01111111 (127) × 01111111 (127) =0011111100000001 (16129). And when the control signals_u = 1, the 8-bit operands are signed and the product of11111111 (-1) × 00000001 (+1) = 1111111111111111 (-1).Fig. 11(e) and Fig. 11(f) shows the simulation result ofsigned- unsigned number in binary and decimal respectively.When s_u = 0, the 8-bit operands are unsigned and theproduct of 10000000 (128) × 10000000 (128) =0100000000000000 (16384). And when the control signals_u = 1, the 8-bit operands are signed and the product of10000000 (-128) × 01111111 (+127) = 1100000010000000(-16256).(a)(b)(c)(d)(e)(f)Fig. 11. Simulation results.666555333666555333
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