FPGA Design and Implementation of a Convolutional
Encoder and a Viterbi Decoder Based on 802.11a for
OFDM
AIM:
The main ai...
Proposed Method:
In this paper, a (2, 1, 7) convolutional encoder is proposed for FPGA design and
implementation, and then...
BLOCK DIAGRAM:

Fig 1. The hardware architecture of Viterbi decoder.
TOOLS: xlinx 9.2i ise, model sim 6.4c
REFERENCE:
[1]
...
[3] P. J. black and T. H. Meng,“Hybrid Survivor Path Architectures for Viterbi
Decoders,” IEEE ICASSP92, Vol. 1, 1993, pp....
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Fpga design and implementation of a convolutional encoder and a viterbi decoder based on 802.11a for

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Fpga design and implementation of a convolutional encoder and a viterbi decoder based on 802.11a for

  1. 1. FPGA Design and Implementation of a Convolutional Encoder and a Viterbi Decoder Based on 802.11a for OFDM AIM: The main aim of the project is to design “FPGA Design and Implementation of a Convolutional Encoder and a Viterbi Decoder Based on 802.11a for OFDM”. (ABSTRACT) In this paper, a modified FPGA scheme for the convolutional encoder and Viterbi decoder based on the IEEE 802.11a standards of WLAN is presented in OFDM baseband processing systems. The proposed design supports a generic, robust and configurable Viterbi decoder with constraint length of 7, code rate of 1/2 and decoding depth of 36 symbols. The Viterbi decoder uses full-parallel structure to improve computational speed for the add-compare-select (ACS) modules, adopts optimal data storage mechanism to avoid overflow and employs three distributed RAM blocks to complete cyclic trace-back. It includes the core parts, for example, the state path measure computation, the preservation and transfer of the survivor path and trace-back decoding, etc. Compared to the general Viterbi decoder, this design can effectively decrease the 10% of chip logic elements, reduce 5% of power consumption, and increase the encoder and decoder working performance in the hardware implementation. Lastly, relevant simulation results using Verilog HDL language are verified based on a Xinlinx Virtex-II FPGA by ISE 7.1i. It is shown that the Viterbi decoder is capable of decoding (2, 1, 7) convolutional codes accurately with a throughput of 80 Mbps. K.Aravind Reddy (Director) Cell No: 9652926926, 9640648777
  2. 2. Proposed Method: In this paper, a (2, 1, 7) convolutional encoder is proposed for FPGA design and implementation, and then an adaptive, low-power, parallel Viterbi decoder with a constraint length of 7 and a code rate of 1/2 is presented. We can increase the constraint length upto 9 in our proposed method. . Advantage:  In this paper, a (2, 1, 7) convolutional encoder is proposed for FPGA design and implementation, and then an adaptive, low-power, parallel Viterbi decoder with a constraint length of 7 and a code rate of 1/2 is presented.  strong Forward Error Correction (FEC) technologies which have been widely utilized in digital communication applications especially such as the Viterbi Algorithm (VA) are employed Extension In this paper, a (2, 1, 7) convolutional encoder is proposed for FPGA design and implementation, and then an adaptive, low-power, parallel Viterbi decoder with a constraint length of 7 and a code rate of 1/2 is presented. We can increase the constraint length upto 9 in our proposed method K.Aravind Reddy (Director) Cell No: 9652926926, 9640648777
  3. 3. BLOCK DIAGRAM: Fig 1. The hardware architecture of Viterbi decoder. TOOLS: xlinx 9.2i ise, model sim 6.4c REFERENCE: [1] IEEE Std. 802.11, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: High Speed Physical Layer in the 5 GHz band,” 1999. [2] A. J. Viterbi, “Error Boundsfor Convolutional Coding and an Asymptotically Optimum Decoding Algorithm,” IEEE Transactions on Information Theory, Vol. IT-13, . No. 2, 1967, pp. 260-269. doi:10.1109/TIT.1967.1054010 K.Aravind Reddy (Director) Cell No: 9652926926, 9640648777
  4. 4. [3] P. J. black and T. H. Meng,“Hybrid Survivor Path Architectures for Viterbi Decoders,” IEEE ICASSP92, Vol. 1, 1993, pp. 433-436. [4] L. Christopher, et al., “A Fully Integrated Digital Demodulation and forward Error Correction IC for Digital Satellite Television,” IEEE Custom Integrated Circuits Conference, Santa Clara, 1-4 May 1995, pp. 281-284. [5] G. Feygin, “Architectural Tradeoffs for Survivor Sequence Memory Managementin Viterbi Decoder,” IEEE Transactions on Communications, Vol. 41, 1993 pp. 426- 428. K.Aravind Reddy (Director) Cell No: 9652926926, 9640648777

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