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  • 1. DESIGN Of LOW-POWER AND HIGH PERFORMANCE RADIX-4 MULTIPLIER lackuline Moni D, Anu Priyadharsini K Associate Professor, ECE dept. Karunya University PG Student, ECE dept. Karunya UniversityAbstract-A One-bit adder is designed using modified Decision Diagrams and the other is a library based design.complementary pass transistor logic (MCPL). The proposed Various type of full adder has been investigated in [6-adder is implemented in 4x4 bit high radix multiplier to 7].Various technique of multiplier has been investigated inachieve high speed, low area and less power dissipation. This [8-12].circuit is simulated by using DSCH2 schematic design tool and II. Analysis of adderslayout is taken by Microwind 2 VLSI layout CAD tool, and One-bit adder is proposed by using the modifiedthe analysis is done by using the BSIM4 analyzer. The 4x4 bit complementary pass transistor logic. Advantages of usinghigh radix multiplier is then compared with Carry Save Arraymultiplier (CSA multiplier), Baugh-Wooley multiplier, and this method are high speed, lower area, low propagationhigh radix multiplier to show the better performance in terms delay. This full adder is then implemented in high radixof power, area and delay. mUltiplier. It is then compared with the carry save array mUltiplier and Baugh-Wooley multiplier. Simulation resultsKeywords- Radix-4 Multiplier, Baugh-Wooley must be fully based on Complementary Metal OxideMultiplier, Carry Save array Multiplier. Semiconductor (CMOS) design rule. One-bit full adder can be implemented by using I. Introduction the combination of both the multiplexing control inputThere are infmite number of ways to perfonn multiplication techniques and complementary pass transistor logic. Thebut still many researchers working in this field, show the proposed full adder is shown in the Figure 1.importance of mUltiplication. Many multiplier circuitdesigns have been proposed, which manage to operate atlower propagation delays with lesser power dissipation anda lower power rating of input bits [I].Multiplier is generallyused in Digital Signal Processor (DSP) devices. In VLSIdesign, researchers mainly concentrate on area, speed andpower dissipation. High speed multipliers include BraunmUltiplier, Booth mUltiplier, Parallel multiplier and highradix multiplier. [2]. Basic mUltiplication can be realized bythe shift add algorithm by generating partial products andadding successive properly shifted partial products. Thusmultiplication is proportional to the number of partialproducts to be added [3]. In all multiplier circuits, twotypes of adder cells are present. They are half adder and fulladder. For the adder to work in high speed, implementingthe adder in any one of the high speed techniques isessential. Circuit delay depends on the number of inversionlevels. Circuit size depends on the number of transistors inthe circuit. Power dissipation depends on the switchingactivity[4]. Pass transistor can be synthesized by using twomethods. One is using Binary Decision Diagrams and theother is a library based design [5 ]. Pass transistor can besynthesized by using two methods. One is using Binary Figure I: Proposed Full Adder
  • 2. Complementary Pass transistor Logic (CPL) partial product. In four bit radix 4 multiplier, 2 partial products will be produced. Partial product is reduced Complementary Pass Transistor Logic (CPL) to half as compared to the shift and add is thenprovides high-speed, full-swing operation and good driving simulated and then fmally compared with other multipliers.capabilities due to the output static inverters and fastdifferential stage of cross-coupled PMOS transistors. But For example consider 1 11 x 111 . 0 0due to the presence, of a lot of internal nodes and static In this , 1 1 is the multiplier value, X . 00inverters, there is a large power dissipation. 111 is the multiplicand value, a. 0 2a value is the shift version of a i.e.0 0 111 .Multiplexing Control Input Techniques (MCIT) 3a is the addition of 1a + 2a i.e. (111 + 0 0 0 111 = 100 1 ). 00 The mUltiplexing control input technique is The calculation is as follows.developed using the kamaugh map which is drawn from thetruth table of full adder. According to sum and carryBoolean identities, we can generate the pass-transistor 1 1 10 (a) Multiplicand valuefunctions. When expression result=l pass transistor 101 1 (X) Multiplier valuefunction is represented by the input variables and when Oexpression result= 0 pass transistor function is represented 0 0 0 0 p( ) initially its equal to zeroby the complement of the input variables. To generate the 101010 2a x l XO(l1)Pass Transistor Function for n input variable functions, 101010 (O) + 2a Xl XOwe use n-1 as control input data. Simplified sum and carry p (J)expression are given as: 00101010 p shift twice the above valueC=AB+AC+BC (2.1) o 1 1 10 2a X2 X3 (1 ) 0S= ABC+ ABC+ ABC+ ABC (2.2) In CPL techniques, there are many drawbacks. To 1001 1010overcome this, we combine both the CPL techniques and 2MCIT techniques. Drawbacks occur in CPL due to the 001001 1010 p( ) shift twice the above valuebody effects, source follower action, and high power The final product value is p.leakage. If the CPL is not cross coupled, then it results inlow performance and limited fanout. B. Carry Save Array Multiplier III.Analysis Of Multipliers The Carry Save Array (CSA) multiplier is a linear array multiplier. The linear multiplier propagates data downA. Radix 4 Multiplier through the array cell. Each row of CSAs adds one additional partial-product to the partial sum. As the operand The MULTIPLEXER is functioned such that the size increases, linear arrays grow at a rate equal to thefirst two bits of the multiplexer, x, will be grabbed to square of the operand size because the number of rows indetermine the first partial product and shifted to the next 2 the array is equal to the width of multiplicand. The Carrybits of the multiplier to determine the successive partial Save Multiplier is shown in the Figure 3.products by repeating the same process. For a 4 bit radix 4multiplier, two partial products will be generated. As a C. Baugh-Wooley Multiplier:result, half of the partial product will be reduced comparedto other method. The radix-4 multiplier is shown in the A Baugh-Wooley multiplier is an enhancedfigure 2.1t consists of the following:Partial product selector, version of the Braun multiplier. It is designed to allow forPartial product pre computation blocks, Half adder, Full the multiplication of both signed and unsigned operands,adder. which are represented in the 2s complement number systems. The Figure 2: Radix-4 Multiplier Baugh-Wooley In this multiplier, two bits per cycle is considered. proposes a single modification to 2s complement additionFour multiples are precomputed; 1a is the multiplicand to obtain a simple signed multiplier array. It uses inputs Avalue, 2a is the shifted version of a and 3a is the and B which are n bit operands, so their product is a 2n-bitcombination of both half adder and full adder. In half number. Consequently the most significant weight is 2n-1,adder, CPL technique is applied, and in full adder, the and the first term is taken in to account by adding a 1 in theproposed one is implemented. Partial Product Selector is most significant cell of the multiplier. The conventionalformed by OR and AND gates. All PPS and pre Baugh-Wooley multiplier is shown in figure 4.computation block are connected with MUX. The functionof the first two bits of the MUX determine the successive
  • 3. 4 i �cpl � a: 2 _mirror w � ..... 14t 0 Q. 2 2.5 3 3.5 �10t VDD (V) �tfa (a) 20 - �CPL .... u.. � 10 _MIRROR c Q. ..... 14T Figure 2: Radix-4 Multiplier o 2 2.5 3 3.5 �10T VDD (V) �TFA (b) 800 �CPL Vi 600 Q. _MIRROR S 400 ..... 14T � 200 �10T o 2V 2.5V 3V 3.5V �TFA VDD (V) _TGA (c) Figure. 3: Carry Save Array Multiplier Figure. 5: (a)power, (b)delay and (c)PDP of various adders Graphs are plotted based on the, comparison of Multiplier with various techniques in terms of power, delay and power delay product is shown in the Figure 6(a),(b),(c). 1.5 a: �Radix-4 w 3: 0.5 o _Baugh Q. o ..... CSA 3.5 2.5 1.8 1.2 Figure.4: Baugh-Wooley MultiplierDifferent adder techniques like CPL, MIRROR, 14T, lOT, VDD (V)TFA , TGA and the proposed adder power, delay and PDPof different values are shown in Figure 5 (a),(b),(c). (a)Compared with other adder, this adder has less power of. 1 96mw, delay of 25 2ps and PDP of 4468Fj . .
  • 4. References 80 -+-Radix-4 Vi 60 [I] E Costa, S Bambi, and Jose Monteiro "A New Architecture fur Q. signed Radix-2Am Pure array Multipliers" Proceedings of the > 40 2002 IEEE International Conference on Computer Design: 111 VLSI in Computers and Processors (ICCD.02). � 20 �Baugh [2] B Park, M Shin, I C Park, and C M Kyung, "Radix-4 multiplier with regular layout structure," Electronics letter, vol.34, no. o 15, pp.1446-7, 1998. 3.5 2.5 1.8 1.2 [3] Y K Yamanaka, T Nishidha, T Saito, M Shimohigashi, and K ...... CSA Shimizu, A. Hitachi Ltd., Tokyo " A 3.8-ns CMOS 16x16-b VDD (V) multiplier using complementary pass-transistor logic," IEEE Journal of Solid-State Circuits, vo1.25, no 2,pp.388-95, 1990. (b) [4] R Zimmermann and W Fichtner, Fellow, IEEELow-Power" Logic Styles: CMOS Versus Pass-Transistor Logic," IEEE Journal Of Solid-State Circuits, vol. 32, no. 7,pp.1079- 90,1997. -+-RADIX [5] D Markovic, B Nikolic, and V G Oklobdzija, "A general method in synthesis of pass-transistor circuits," Microelectr. J, vol. 31,pp. 991-8,2000. [6] C H Chang, J Gu, and M Zhang, "A review of O.J8-mm full adder performances for tree structured arithmetic circuits," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. Vol. 13 pp. 686-95, 2005. [7] Massimo Alioto, Member, IEEE, and Gaetano Palumbo, Senior Member, IEEE, "Analysis and Comparision on Full Adder Block in Submicron Technology," IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 10, no. 6, pp. 806-23, 2002. 3.5 2.5 1.8 1.2 [8] L Sousa and R Chaves, "A universal architecture for designing VDD (V) effiCient modulo 2n+ 1 multipliers," IEEE Trans. Circuits Syst.­ I:Regular Papers, vol. 52, pp.1166-78, 2005. [9] T Oscal, C Chen, S Wang, and Y W Wu, "Minimization of (c) switching activities of Partial Products for Designing Low­ Figure 6 (a)power, (b)Delay and (c)PDP of Radix-4 Multiplier, Baugh­ Power Multipliers, "IEEE Transaction on Very Large Scale Wooley MUltiplier and Carry Save Array Multiplier Integration (VLSI) Systems,vol. II, no. 3, pp. 418-433,2008. [10] J D Lee, Y J Yooney, K H Leez, and B G Park, "Application of IV.Conclusion and Future work dynamic pass-transistor logic to an 8-bit multiplier," J Kor Phys Soc, vo1.38, pp.220-23, 2001. [II] R Mudassir and Z Abid," New parallel multipliers based on The adder cell was designed using a modified CPL low power adders," 2005 IEEE CCECE/CCGEI, Saskatoon,technique. The I-bit adder cell was implemented in radix-4, pp. 694-7,2005.Baugh-Woolley and CSA multipliers. The proposed Radix- [12] M C Wen, S J Wang, and Y N Lin, " Low-Power parallel4 MUltiplier may be used in DSP applications because it multiplier with column bypassing ," lEE Electr Lett, vol. 41,gives better performance in terms of power, delay and PDP. pp. 1-2, 2001.The proposed adder based multiplier can be used in highspeed application because of its less power dissipation anddelay.