Design of high speed low power multiplier using reversible logic a vedic mathematical approach
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Design of high speed low power multiplier using reversible logic a vedic mathematical approach

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    Design of high speed low power multiplier using reversible logic a vedic mathematical approach Design of high speed low power multiplier using reversible logic a vedic mathematical approach Document Transcript

    • Design of Locally-Clocked Asynchronous Finite State Machines Using Synchronous CAD Tools AIM: The main aim of the project is to design “Design of Locally-Clocked Asynchronous Finite State Machines Using Synchronous CAD Tools”. ABSTRACT: Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of embedded digital systems. These systems present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the design are already drawbacks. This paper proposes a new method to design asynchronous FSM with local clock. The existence of a local clock reduces the requirements of asynchronous logic, enabling the synthesis in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. Furthermore, when compared to other methods found in literature, it uses of conventional logic minimization tools that greatly facilitate the designing. The proposed method starts from a popular specification known as Extended Burst Mode (XBM) and uses a logic minimization synchronous tool for the synthesis. The achieved results show a high potential of practical implementation of this method for AFSM synthesis in PLDs. V.Mallikarjuna (Project manager) ISO: 9001- 2000 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
    • BLOCK DIAGRAM: Fig: Proposed Architecture: AFSM with FC for PLD. Fig: Architecture: AFSM with local clock. TOOLS: Xilinx 9.2ISE, Modelsim6.4c. APPLICATION ADVANTAGES: V.Mallikarjuna (Project manager) ISO: 9001- 2000 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
    • • This method synthesizes the circuit in the “local clock” style, allowing reducing the logic asynchronous requirements, and showing to be very important in order to use synchronous tools. • The provided machines can be synthesized in any PLD, such as CPLDs and FPGAs, without the need of satisfying any type of macro-cells mapping. REFERENCES: • K. D. Muller-Glaser, et. al. “Multiparadigm Modeling in Embedded Systems Design”, IEEE Trans. on Control Systems Technology, vol. 12, no. 2. • J. J. Rodriguez, et. Al., “Features, Design Tools, and Applications Domains of FPGAs”, IEEE Trans. on Industrial Electronics, vol. 54, No. 4, pp.18101823. • P. P. Czapski and A. Sluzek, “A Survey on System-Level Techniques for Power Reduction in Field Programmable Gate Array (FPGA)-Based Devices”, The Second Int. Conf. on Sensor Technologies and Applications, pp.319-327. • C. J., Myers, “Asynchronous Circuit Design”, Wiley & Sons, Inc., 2a edition. • K. Y. Yun e D. L. Dill, "Automatic Synthesis of Extended Burst-Mode Circuits: Part I (Specification and Hazard-.Free Implementation) and Part II V.Mallikarjuna (Project manager) ISO: 9001- 2000 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
    • (Automatic Synthesis)," IEEE Trans. on CAD of Integrated Circuit and Systems, Vol. 18:2, pp. 101-132. V.Mallikarjuna (Project manager) ISO: 9001- 2000 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur