services on...... embedded(ARM9,ARM11,LINUX,DEVICE DRIVERS,RTOS) VLSI-FPGA DIP/DSP PLC AND SCADA JAVA AND DOTNET iPHONE ANDROID If ur intrested in these project please feel free to contact us@09640648777,Mallikarjun.V
correctly determine the start bit of a frame data. The receiver module receives data from RXD pin. RXD jumps into logic 0 Data bits from logic 1 can be regarded as the beginning of a data frame. When the UART receiver module is reset, it has been waiting the RXD level to jump. The start bit is identified by detecting 1 2 3 4 5 6 7 8 RXD level changes from high to low. In order to avoid the misjudgment of the start bit caused by noise, a start bit errorIdle bit Start bit Parity bit Stop bit detect function is added in this design, which requires the received low level in RXD at least over 50% of the baud rate to Figure 1. UART Frame Format be able to determine the start bit arrives. Since the receive clock frequency is 16 times the baud rate in the design, the II. IMPLEMENTATION OF UART RXD low level lasts at least 8 receiving clock cycles is In this paper, the top to bottom (Top to Down) design considered start bit arrives. Once the start bit been identified,method is used. The UART serial communication module is from the next bit, begin to count the rising edge of the bauddivided into three sub-modules: the baud rate generator, clock, and sample RXD when counting. Each sampled value ofreceiver module and transmitter module, shown in Fig. 2. the logic level is deposited in the register rbuf [7, 0] by order.Therefore, the implementation of the UART communication When the count equals 8, all the data bits are surely received,module is actually the realization of the three sub-modules. The also the 8 serial bits are converted into a byte parallel data..baud rate generator is used to produce a local clock signal The serial receiver module includes receiving, serial andwhich is much higher than the baud rate to control the UART parallel transform, and receive caching, etc. In this paper wereceive and transmit; The UART receiver module is used to use finite state machine to design, shown in Fig. 3.receive the serial signals at RXD, and convert them intoparallel data; The UART transmit module converts the bytesinto serial bits according to the basic frame format and RXD_SYNC=0transmits those bits through TXD. R_START Baud Rate Generator R_STOP RXD_SYNC=1 R_CENTER RCNT16=0100 RCNT16=1110 AND AND Data Receiver Transmitter RBITCNT=FRAMELEN RCNT16=1110 AND R_WAIT R_SAMPLE Figure 2. UART Module RBITCNT/ =FRAMELENA. Baud Rate Generator Figure 3. UART Receiver State Machine Baud Rate Generator is actually a frequency divider. Thebaud rate frequency factor can be calculated according to agiven system clock frequency (oscillator clock) and the The state machine includes five states: R_START (waitingrequested baud rate. The calculated baud rate frequency factor for the start bit), R_CENTER (find midpoint), R_WAITis used as the divider factor. In this design, the frequency clock (waiting for the sampling), R_SAMPLE (sampling), andproduced by the baud rate generator is not the baud rate clock, R_STOP (receiving stop bit).but 16 times the baud rate clock. The purpose is to precisely R_START Status: When the UART receiver is reset, thesample the asynchronous serial data at the receiver. Assume receiver state machine will be in this state. In this state, thethat the system clock is 32MHz, baud rate is 9600bps, and then state machine has been waiting for the RXD level to jump overthe output clock frequency of baud rate generator should be 16 from logic 1 to logic 0, i.e. the start bit. This alerts the* 9600Hz. Therefore the frequency coefficient (M) of the baud beginning of a new data frame. Once the start bit is identified,rate generator is: the state machine will be transferred to R_CENTER state. In M =32MHz/16*9600Hz=208 Fig. 3, RXD_SYNC is a synchronization signal of RXD. Because when sampling logic 1 or logic 0, we do not want the When the UART receives serial data, it is very critical to detected signal to be unstable. So we do not directly detectdetermine where to sample the data information. The ideal time RXD signal, but detect the synchronization signalfor sampling is at the middle point of each serial data bit. In RXD_SYNC.this design, the receive clock frequency is designed to be 16times the baud rate, therefore, each data width received by R_CENTER Status: For asynchronous serial signal, inUART is 16 times the receive clock cycle. order to detect the correct signal each time, and minimize the total error in the later data bits detection. Obviously, it is theB. Receiver Module most ideal to detect at the middle of each bit. In this state, the task is to find the midpoint of each bit through the start bit. The During the UART reception, the serial data and the method is by counting the number of bclkr (the receiving clockreceiving clock are asynchronous, so it is very important to frequency generated by the baud rate generator) (RCNT16 is
the counter of bclkr). In addition, the start bit detected in the XMIT_CMD. XMIT_CMD_P is a processed signal ofR_START may not be a really start bit, it may be an occasional XMIT_CMD, which is a short pulse signal. Since XMIT_CMDinterference sharp pulse (negative pulse). This interference is an external signal, outside FPGA, its pulse width is unable topulse cycle is very short. Therefore, the signal that maintains be limited. If XMIT_CMD is valid, it is still valid after sendinglogic 0 over 1 / 4 bit time must be a start bit. one UART data frame. Then the UART transmitter will think by mistake that a new data transmit command has arrived, and R_WAIT Status: When the state machine is in this state, once again start the frame transmit. Obviously the framewaiting for counting bclkr to 15, then entering into transmit is wrong. Here we limit the pulse width ofR_SAMPLE to sample the data bits at the 16th bclkr. At the XMIT_CMD. XMIT_CMD_P is its processed signal. Whensame time determining whether the collected data bit length XMIT_CMD_P = 1 , the state machine transferred tohas reached the data frame length (FRAMELEN). If reaches, it X_START, get ready to send a start bit.means the stop bits arrives. The FRAMELEN is modifiable inthe design (using the Generic). In this design it is 8, which X_START Status: In this state, sends a logic 0 signal to thecorresponds to the 8-bit data format of UART. TXD for one bit time width, the start bit. Then the state machine transferred to X_WAIT state. XCNT16 is the counter R_SAMPLE Status: Data bit sampling. After sampling the of bclkt.state machine transfers to R_WAIT state unconditionally, waitsfor the arrival of the next start bit. X_WAIT Status: Similar with the R_WAIT of UART receive state machine. R_STOP Status: Stop bit is either 1 or 1.5, or 2. Statemachine doesn’t detect RXD in R_STOP, but output frame X_SHIFT Status: In this state, the state machine realizes thereceiving done signal (REC_DONE <= 1 ). After the stop bit, parallel to serial conversion of outgoing data. Thenstate machine turns back to R_START state, waiting for the immediately return to X_WAIT state.next frame start bit. X_STOP Status: Stop bit transmit state. When the data frame transmit is completed, the state machine transferred toC. Transmit Module this state, and sends 16 bclkt cycle logic 1 signal, that is, 1 stop The function of transmit module is to convert the sending bit. The state machine turns back to X_IDLE state after8-bit parallel data into serial data, adds start bit at the head of sending the stop bit, and waits for another data frame transmitthe data as well as the parity and stop bits at the end of the command.data. When the UART transmit module is reset by the resetsignal, the transmit module immediately enters the ready state III. SIMULATION OF MODULESto send. In this state, the 8-bit parallel data is read into theregister txdbuf [7: 0]. The transmitter only needs to output 1 bit The simulation software is Quartus II. And the selectedevery 16 bclkt (the transmitting clock frequency generated by device is Altera’s Cyclone II FPGA: EP2C5F256C6.the baud rate generator) cycles. The order follows 1 start bit, 8data bits, 1 parity bit and 1 stop bit. The parity bit is determined A. Baud Rate Generator Simulationaccording to the number of logic 1 in 8 data bits. Then the During simulation, the system clock frequency is set toparity bit is output. Finally, logic 1 is output as the stop bit. Fig. 32MHz, and baud rate is set to 9600bps. Therefore the4 shows the transmit module state diagram. receiving sampling clock frequency generated by the baud rate generator is 153600Hz, which is 16 times of the baud rate. XCNT16=01111 AND Thus the frequency coefficient of baud rate generator can be XMIT_CMD_P=0 XMIT_CMD_P=1 calculated, which equals 208. Fig. 5 shows the simulation X_IDLE result of baud rate generator. The simulation report shows that this module uses 42 logic elements （ <1% ） , 33 registers RXD_SYNC=1 X_START X_STOP (2%), and meets timing requirement. XCNT16=01110 AND XCNT16=01111 XBITCNT=FRAMELEN XCNT16=01110 AND X_WAIT X_SHIFT XBITCNT/ =FRAMELEN Figure 4. Transmit Module State Diagram Figure 5. Simulation Result of Baud Rate Generator This state machine has 5 states: X_IDLE (free), X_START(start bit), X_WAIT (shift to wait), X_SHIFT (shift), X_STOP B. Receiver Simulation(stop bit). During receiver simulation, the receiving sampling clock X_IDLE Status: When the UART is reset, the state frequency generated by the baud rate generator is set to 153600machine will be in this state. In this state, the UART Hz, UART receiving baud rate is set to 9600bps. The inputtransmitter has been waiting a data frame sending command sequence is: 00110110001, including the start bit 0, parity bit 0 and 1 stop bit. The received data is stored into the register rbuf.
Fig. 6 shows the receiver module simulation diagram. Thefigure shows that the data in rbuf from high to low is00110110, which is just the part of data bits of UART frame. Figure 8. RTL of Top File Figure 6. Receiver Simulation Diagram IV. CONCLUSIONC. Transmitter Simulation This design uses VHDL as design language to achieve the During transmitter simulation, the sending clock frequency modules of UART. Using Quartus II software, Alterasgenerated by the baud rate generator is set to 153600 Hz, and Cyclone series FPGA chip EP2C5F256C6 to completeUART transmitting baud rate is set to 9600bps. Fig. 7 shows simulation and test. The results are stable and reliable. Thethe transmitter module simulation diagram. The simulation design has great flexibility, high integration, with somereport shows that this module uses 78 logic elements（<1%, reference value. Especially in the field of electronic design,13 pins (4%), and meets timing requirement. where SOC technology has recently become increasingly mature, this design shows great significance. REFERENCES  Zou,Jie Yang,Jianning。Design and Realization of UART Controller Bas ed on FPGA  Liakot Ali ， Roslina Sidek ， Ishak Aris ， Alauddin Mohd. Ali ， Bambang Sunaryo Suparjo. Design of a micro - UART for SoC application [J].In: Computers and Electrical Engineering 30 (2004) 257– 268. Figure 7 Transmitter Simulation Diagram  HU Hua, BAI Feng-e. Design and Simulation of UART Serial Communication Module Based on Verilog -HDL[J]. J ISUANJ I YUD. RTL of Top File XIANDA IHUA 2008 Vol. 8 Fig. 8 shows the RTL of UART Top File. It includes the  Frank Durda Serial and UART Tutorial. uhclem@FreeBSD.orgbaud rate generator, receiver, and transmitter modules.