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Design and implementation of double precision fpu processor
Design and implementation of double precision fpu processor
Design and implementation of double precision fpu processor
Design and implementation of double precision fpu processor
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Design and implementation of double precision fpu processor

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For more projects visit www.nanocdac.com r mail info@nanocdac.com

For more projects visit www.nanocdac.com r mail info@nanocdac.com

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  • 1. Design and Implementation of double precision FPU Processor AIM: The main aim of the project is to design and implement “Design and Implementation of double precision FPU Processor”. ABSTRACT: Floating point operations are hard to implement on FPGAs because of the complexity of their algorithms. On the other hand, many scientific problems require floating point arithmetic with high levels of accuracy in their calculations. Therefore, we have explored FPGA implementations of addition and multiplication for IEEE-754 double precision floating-point numbers. For floating point multiplication, in IEEE double precision format, we have to multiply two 24 bits. As we know that in Spartan 3E, 18 bit multiplier is already there. The main idea is to replace the existing 18 bit multiplier with a dedicated 24 bit multiplier designed with small 4 bit multiplier. For floating point addition, exponent matching and shifting of 24 bit mantissa and sign logic are coded in behavioral style. Entire our project is divided into 4 modules. 1. Designing of floating point adder/subtractor. 2. Designing of floating point multiplier. 3. Creation of combined control & data paths. Prototypes have been implemented on Xilinx Spartan 3E.
  • 2. BLOCK DIAGRAM: Fig: Architecture for floating point adder/subtractor
  • 3. Fig: Designed architecture for floating point multiplication. TOOLS: Xilinx 9.2ISE, Modelsim 6.4c. APPLICATION ADVANTAGES:  Image and digital signal processing applications require high floating point calculations throughput, and nowadays FPGAs are being used for performing these Digital Signal Processing (DSP) operations.  The designed architecture can perform both double precision floating point addition as well as double precision floating point multiplication with a double dedicated 24x24 bit multiplier block designed with small 4x4 bit multipliers. REFERENCES:
  • 4. 1. www.xilinx.com 2. Himanshu Thapliyal, Hamid R. Arabnia, A.P Vinod , combined integer and floating point multiplication in FPGA’s 3. Computer arithmetic: Algorithms and hardware design by Behrooz Parhami 4. Computer arithmetic algorithm by Isreal Koren 5. www.randelshofer.ch/fhw/gri/lcd-init for some part of code in lcd interfacing. 6. http://babbage.cs.qc.cuny.edu/IEEE-754/Decimal.html for java applets regarding floating point conversions 7. HITACHI HD44780_LCD data sheet.

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