Design and implementation of a high performance multiplier using hdl

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  • 1. Design and Implementation of a High Performance Multiplier using HDL AIM: The main aim of the project is to design “Design and Implementation of a High Performance Multiplier using HDL”. (ABSTRACT) This paper presents an area efficient implementation of a high performance parallel multiplier. Radix-4 Booth multiplier with 3:2 compressors and Radix-8 Booth multiplier with 4:2 compressors are presented here. The design is structured for m × n multiplication where m and n can reach up to 126 bits. Carry Lookahead Adder is used as the final adder to enhance the speed of operation. Finally the performance improvement of the proposed multipliers is validated by implementing a higher order FIR filter. The design entry is done n VHDL and simulated using ModelSim SE 6.4 design suite from Mentor Graphics. It is then synthesized and implemented using Xilinx ISE 9.2i targeted towards Spartan 3 FPGA. Proposed Method: In this architecture, an area efficient implementation of a high performance parallel multiplier is proposed. Radix-4 Booth multiplier with 3:2 compressors and Radix-8 Booth multiplier with 4:2 compressors are presented here. The design is structured for m × n multiplication where m and n can reach up to 126 bits. V.Mallikarjuna (Project manager) ISO: 9001- 2000 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 2. Advantage: Following the approach, faster than the other multipliers for 16x16 case and consumes only 76% area for 8x8 multiplier and 42% area for 16x16 multiplier. BLOCK DIAGRAM: Fig. 1 block diagram of Wallace booth multiplier V.Mallikarjuna (Project manager) ISO: 9001- 2000 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 3. Fig. 2 wallace tree using 3:2 compressors V.Mallikarjuna (Project manager) ISO: 9001- 2000 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 4. Fig. 3 wallace tree using 4:2 compressor TOOLS: XILLINX ISE 9.2i, MODEL SIM 6.4c REFERENCE: [1] Dong-Wook Kim, Young-Ho Seo, “A New VLSI Architecture of Parallel Multiplier-Accumulator based on Radix-2 Modified Booth Algorithm”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions, vol.18, pp.: 201-208, 04 Feb. 2010 [2] Prasanna Raj P, Rao, Ravi, “VLSI Design and Analysis of Multipliers for Low Power”, Intelligent Information Hiding and Multimedia Signal Processing, Fifth International Conference, pp.: 1354-1357, Sept. 2009. [3] Lakshmanan, Masuri Othman and Mohamad Alauddin Mohd.Ali, “High Performance Parallel Multiplier using Wallace-Booth Algorithm”, Semiconductor Electronics, IEEE International Conference , pp.: 433- 436, Dec. 2002. [4] Jan M Rabaey, “Digital Integrated Circuits, A Design Perspective”, Prentice Hall, Dec.1995 [5] Louis P. Rubinfield, “A Proof of the Modified Booth's Algorithm for Multiplication”, Computers, IEEE Transactions,vol.24, pp.: 1014-1015, Oct. 1975 V.Mallikarjuna (Project manager) ISO: 9001- 2000 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur