Construction of optimum composite field architecture for compact high throughput aes s-boxes

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  • 1. Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes AIM: The main aim of the project is to design and implement “Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes”. ABSTRACT: In this work, we derive three novel composite field arithmetic (CFA) Advanced Encryption Standard (AES) S-boxes of the field . The best construction is selected after a sequence of algorithmic and architectural optimization processes. Furthermore, for each composite field constructions, there exists eight possible isomorphic mappings. Therefore, after the exploitation of a new common subexpression elimination algorithm, the isomorphic mapping that results in the minimal implementation area cost is chosen. High throughput hardware implementations of our proposed CFA AES S-boxes are reported towards the end of this paper. Through the exploitation of both algebraic normal form and seven stages fine-grained pipelining, our best case achieves a throughput 3.49 Gbps on a Cyclone II EP2C5T144C6 field-programmable gate array. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 2. BLOCK DIAGRAM: Fig: ANF-CFA AES S-box with seven stages fine-grained pipelining for (a) Case I, (b) Case II, and (c) Case III. TOOLS: Xilinx 9.2ISE, Modelsim 6.4c. APPLICATION ADVANTAGES: V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 3.  With the employment of ANF representation and seven stages fine grained pipelining, the hardware architecture of Case III managed to achieve a high throughput of 3.49 Gbps with the utilization of 96 Les in Cyclone II EP2C5T144C6 FPGA and thermal power consumption of 34.80 mW.  Apart from AES S-box, the methodologies proposed in this work are also applicable for development of any similar cryptographic circuits that involved finite field arithmetic. REFERENCES: • S. Mathew, F. Sheikh, A. Agarwal, M. Kounavis, S. Hsu, H. Kaul, M. Anders, and R. Krishnamurthy, “53 Gbps native GF (24)2 composite- field AES-encrypt/decrypt accelerator for content-protection in 45 nm highperformance microprocessors,” in Proc. IEEE Symp. VLSI Circuits (VLSIC), pp. 169–170. • V. Rijmen, “Efficient implementation of the Rijndael S-box,” 2000. [Online]. Available: http://ftp.comms.scitech.susx.ac.uk/fft/crypto/rijndaelsbox.pdf • A. Rudra, P. K. Dubey, C. S. Jutla, V. Kumar, J. R. Rao, and P. Rohatgi, “Efficient rijndael encryption implementation with composite field arithmetic,” in Proc. CHES, pp. 171–184. • J.Wolkerstorfer, E. Oswald, and M. Lamberger, “An ASIC implementation of the AES S-boxes,” in Proc. RSA Conf., pp. 67–78. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur
  • 4. • A. Satoh, S. Morioka, K. Takano, and S. Munetoh, “A compact Rijndael hardware architecture with S-box optimization,” in Proc. ASIACRYPT, pp. 239–245. V.Mallikarjuna (Project manager) ISO: 9001- 2008 CERTIFIED COMPANY Mobile No: +91-8297578555. Branches: Hyderabad & Nagpur