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- 1. An Implementation of a 2D FIR Filter Using the Signed-Digit Number System Yasser Mohammad Seddiq1,2, Hesham Altwaijry2 yseddiq@kacst.edu.sa, twaijry@ksu.edu.sa 1 The National Program of Electronics, Communications and Photonics, King Abdulaziz City for Science and Technology 2 Department of Computer Engineering, King Saud University system. Abstract—An FIR filter is implemented in this work. Enhanc- A low-power and small-area FIR filter has been developeding the arithmetic operations of the filter is considered. For the utilizing the signed-digit number system as reported in [2] andaddition operation, the signed-digit number system is utilized. [3]. Another work that is presented in [4] used the signed-digitFor the multiplication operation, Booth-3 algorithm is used to representation to represent filter coefficients. For multipliersreduce the number of partial products. Then a 1D filter is used toconstruct a 2D filter that is deployed on real hardware in an im- and adders, Booth-2 algorithm and carry-save adder are usedage processing application. respectively. In [5], the use of signed-digit number system helped in reducing the number of partial products in the mul- Index Terms— Computer arithmetic, Hardware implementa- tipliers of the filter. Asymmetric signed-digit number systemtion, Digital signal processing, FIR filters, signed-digit number has been utilized in [6] to develop a high-speed dot productsystem, Carry-save adder, Booth multiplier, Image processing, unit that can be used in FIR filters.FPGA In this paper the carry-propagate-free addition of the signed-digit number system is utilized to implement finite I. INTRODUCTION impulse response (FIR) filters. Additionally Booth-3 algorithmF ILTERS are components that are used in signal processing for two purposes: separation of interfering signals andrestoration of corrupted signals[1]. Digital filters are the filters is utilized to speed up multipliers in the filter. A 1D FIR filter is implemented using an FPGA platform. After that, a 2D fil- ter is built using the 1D filter. The 2D filter is mapped into anthat are implemented digitally as in software, as an ASIC, an FPGA and tested on real hardware.FPGA solution. Digital filters are fundamental components of The rest of the paper is organized as follows. A brief back-digital signal processing (DSP) systems. Commonly, DSP ground overview about the signed-digit number system andsystems manipulate digitized signals by applying mathemati- the FIR filters are presented in Section II. Improving FIR fil-cal models of the required functions. Therefore, improving ters by using the signed-digit number system and Booth algo-arithmetic operations in digital filters should have a direct rithm is discussed in Section III. Section IV reports the designimpact on the overall performance of the filter. Fortunately, and the implementation of the FIR filter that is done in thisthe literature of computer arithmetic is rich in advanced tech- work. Synthesis results are discussed in Section V. Imageniques that constructively affect the performance of digital processing deployment of the 2D filter is presented in Sectionfilters when applied. VI. Finally, summary and conclusions are reported in Section In modern applications of digital filters, signal samples are VII.getting wider. Moreover, a finite impulse response (FIR) filter,must deal with a large set of samples simultaneously. Some II. BACKGROUND OVERVIEWlimitations in the binary number system become more notice-able when handling many wide samples. An observation about A. The Signed-Digit Number System Overviewthe conventional binary system is that different representations This section discusses an important feature of the uncon-are used for signed and unsigned numbers such as the 2’s ventional number system, which is the redundancy. A numbercomplement representation. Another observation is the carry system is called redundant if an algebraic value cannot have apropagation associated with the addition operation in the bi- unique representation. The number of digits of a redundantnary system. This carry propagation increases the delay and number system is expected to be greater than r, where r is thelimits the scalability of arithmetic systems. radix [7]. In this brief review, a redundant number system, The presence of these limitations is the motivation to inves- which is the signed-digit number system, is discussed.tigate unconventional number systems when implementing In the signed-digit number system, each digit can be eitherhigh precision digital filters such as the signed-digit number positive or negative and hence is called signed-digit [8],[9]. This feature makes the sign information implicitly included in the number representation and there is no need for special re- 978-1-4577-0069-9/11/$26.00 ©2011 IEEE
- 2. presentations for signed and unsigned numbers similarly to B. Improving Multiplicationconventional binary system. Multiplication is a two step process: generating the partial Another feature is the carry-propagate-free addition under products and then accumulating them. When multiplying thethe signed-digit number system. The carry chain in signed multiplicand (M) and the multiplier (R), the result is the prod-digit is limited to one position to the left. This allows adding uct (P). The most straightforward method to generate partiallarge precision signed-digit numbers in constant time. products is add-and-shift where each non-zero bit of R will Some properties of the signed-digit number system are: cause a left shift in M by a number of bits that is equal to the1) As any other positional number system, the algebraic val- weight of that bit of R. A problem with this algorithm is that it ue of a number Z consisting of n+m+1 digits (zm, ... , z1, generates a high number of partial products, which implies z0, z-1, ... , z-n) is calculated as: more delay in the accumulation step. Improving the multipli- m cation speed can be achieved by reducing the number of par- Z= ¦ zi r i (1) tial products. One of the earliest algorithms is the one pro- i=−n posed by Booth [11].2) A number Z is equal to 0 if and only if all the digits zi are Booth algorithm is based on the idea that if that number of equal to 0.3) The sign of a number is inverted by inverting the sign of ones in R is reduced, then the number of partial products will each digit of that number. be reduced. The algorithm was devised to work sequentially,4) The sign of a number is given by the sign of the leftmost Modified Booths algorithm was later proposed to make allow non-zero digit. parallel generation of the partial product [10] [12] [13]. In this paper, the term Booth algorithm is used for the parallel version B. Finite Impulse Response Filters Overview of algorithm. Widely used versions of Booth algorithm are A fundamental parameter of any digital filter is its impulse Booth-2 and Booth-3.response, which basically consists of an infinite number of In the Booth-2 algorithm, R is divided into overlappingsamples. When only a subset of the impulse response is consi- groups of 3 bits. The groups are then used to select the partialdered for a filter, we obtain the finite impulse response (FIR) product as a multiple of M as described in Table II.filter. The function of an FIR filter can be mathematically When the groups become 4-bit wide, the encoding schememodeled by the process of convolution. When a digital signal is called Booth-3 and the number of partial products that willx[n] enters a filter with impulse response h[n], the output y[n] be generated will decrease. Likewise, the groups used to selectis calculated by convolving x[n] with h[n] as in the equation the appropriate partial product multiple of M for Booth-3 is N −1 shown in Table II. All of these multiples can be calculated by y[ n ] = ¦ h[k ]x[n − k ] (2) a simple shift except for the multiple 3M, which is called a k =0 hard multiple. III. IMPROVING FIR FILTER PERFORMANCE TABLE II: BOOTH ALGORITHM PARTIAL PRODUCT (PP) SELECTION TABLEA. Improving Addition ŽŽƚŚͲϮ ŽŽƚŚͲϯ Recalling that carry propagation is limited to one position to ƌŽƵƉ WW ŐƌŽƵƉ WW ƌŽƵƉ WWthe left, a signed-digit number system can perform addition orsubtraction with a fixed delay regardless of the width of the ϬϬϬ Ϭ ϬϬϬϬ Ϭ ϭϬϬϬ ʹϰDoperands. A general block diagram of the signed-digit adder is ϬϬϭ D ϬϬϬϭ D ϭϬϬϭ ʹϯDillustrated in Fig. 1. Selecting values for the intermediate re- ϬϭϬ D ϬϬϭϬ D ϭϬϭϬ ʹϯDsults u and c is shown in Table I [10]. Ϭϭϭ ϮD ϬϬϭϭ ϮD ϭϬϭϭ ʹϮD ϭϬϬ ʹϮD ϬϭϬϬ ϮD ϭϭϬϬ ʹϮD ϭϬϭ ʹD ϬϭϬϭ ϯD ϭϭϬϭ ʹD ϭϭϬ ʹD ϬϭϭϬ ϯD ϭϭϭϬ ʹD ϭϭϭ Ϭ Ϭϭϭϭ ϰD ϭϭϭϭ Ϭ IV. IMPLEMENTATION OF FIR FILTER USING SIGNED-DIGIT NUMBER SYSTEM Fig. 1: The signed-digit adder For the purpose of implementing an FIR filter, the signed- TABLE I: GENERATING U AND C FOR SIGNED-DIGIT ADDITION [10] digit number system and Booth-3 algorithm are used in this xi yi 00 01 or 10 0 1 or 1 0 11 11 work to enhance the filter performance. In order to implement xi – 1 – none X1 None X1 – – the signed-digit adder, the logic equations proposed in [14] are yi – 1 is is 1 used. The equations performs the operation S = X+Y such that 1X 1X 1 the digits are encoded as {x+, x– }, {y+, y– } and {s+, s– }. ci+1 0 1 0 0 1 1 1 The multiplier is implemented using the Booth-3 algorithm. ui 0 1 1 1 1 0 0 An implementation of the multiplier with a solution to the
- 3. hard multiple 3M was proposed in [15] using the signed-digit g ϭϮϰϱϴϰ ϭϰϬϬϬϬnumber system to calculate the hard multiple 3M as 4M – M. e ϭϮϬϬϬϬThe selection of the partial products is done b the logic equa- by ϭϬϬϬϬϬ ϳϬϵϲϴtions that are derived in our work as follows: M = ri −1 ⊕ ri (3) ϴϬϬϬϬ Eсϭϲ ϰϰϱϴϱ 2 M = ri ri +1 ri −1 + ri +1ri ri −1 ϲϬϬϬϬ ϯϭϬϵϯ (4) EсϯϮ ϮϮϯϱϱ ϰϬϬϬϬ ϭϭϰϮϯ ϭϭϯϰϬ 4 M = ri + 2 ri +1 ( ri −1 + ri ) + ri + 2 ri +1 i ( ri −1 + ri ) (5) Eсϲϰ ϱϱϴϭ ϮϳϬϭ ϮϬϬϬϬ Where ri is the i th bit of the multiplier ( R) Ϭ The jth digit of the ith partial product is foun as follows: nd tсϭϮ tсϮϰ tсϰϴ + ppi , j = 4 M Mm j + 2 M m j −1 + 4 Mm j −2 (6) Fig. 4: Logic Elements used in design of 1-D FIR filters. ppi− j = M 4 Mm j , (7) Where m j is the j th bit of the multiplier M It is noticed that the delay is mo affected by W than N. ore That is because of the Carry propag adder (CLA) that is in gate the last stage of the filter. Its delay is directly affected by W. y When the CLA is analyzed separate it is found that around ely, 28% of the filter delay is caused by the CLA. Also, the multip- lier delay depends on the number of partial products, which in f turn is a function of W. These two sources of delay explain o why W has a much larger impact on the overall filter delay. Looking at the hardware utilizat tion results, it is observed that for small values of W, the valu of N does not have that ue much impact on the filter size. Recalling that larger values of Fig. 2: The Signed-digit FIR filter implemented in th work. his W imply larger multipliers may justify this. In fact, while in- creasing N, the number of multiplie instantiated in the filter ersFinally, the 1D FIR filter is built is shown in Fig. . The final n will also increase. Therefore, when W is small, these multip- nstage of the filter is a carry lookahead adder (CLA) to convert liers become less significant to the overall size, but with larger othe result from signed-digit representation to 2’s complement o W the multipliers become more significant and filter sizerepresentation. growth becomes more noticeable. V. SYNTHESIS RESULTS OF THE 1 FILTER 1D VI. THE 2D FILTER DEPLOYMENT D Here, the sample width of the filter input i called W while is The 2D FIR filter is built using th 1D filter reported above. hethe number of samples that are processed w within the filter is The filter should perform the 2D connvolution process:called N. Three precision levels of W are se elected as 12, 24 M −1 N −1and 48 bits. For N, the selected orders are 16 32 and 64 sam- 6, y[m, n ] = ¦ ¦ x[i, j ]h[m − i, n − j ] (8)ples. Therefore, there 9 different configurat tions for the FIR i =0 j =0filter to be synthesized. Synthesis and place--and-route is per-formed using Quartus II software and A Altera Stratix IIIEP3SL340 FPGA is selected. The synthesis and place-and-rout results are summarized in Fig 3 and Fig 44. ϯϱ Ϯϵ͘ϳ ϯϬ Ϯϯ͘Ϯ Ϯ Ϯϯ͘ϴ Ϯϱ Ϯϭ͘ϯ ϭϵ͘ϯ ϮϬ ϭϳ͘ϴ ϭϲ͘ϵ Eсϭϲ Fig. 5: The 2D FIR filter ϭϰ͘ϯ ϭϱ ϭϮ͘ϴ EсϯϮ M instances of 1D filter of order N are used to build the 2D ϭϬ Eсϲϰ filter of order M-by-N as illustrated in Fig 5. For the purpose d of deploying the 2D filter on real ha ardware, an arbitrarily cho- ϱ sen filter dimensions of 11-by-11. The filter is deployed in an T Ϭ edge extraction application where th filter works as a moving he tсϭϮ tсϮϰ t tсϰϴ average filter to blur an image and the result of the filter is d subtracted from the original image in order to extract the im-Fig. 3: Delay of 1-D FIR filters. age edges. The edge extraction sy ystem is implemented and
- 4. mapped into Altera Cyclone II FPGA running on development for Wireless Embedded System," IEEE Trans. on Circuits and Sys-board. An input image is fed form PC to the FPGA to be [4] Hwan-Rei Lee, Chein-WeiVol. and No. 1, pp: 21 -Liu, Jan New Hardware- tems—II: Express Briefs, Jen 51, and Chi-Min 25, "A 2004processed and then returned back to the PC again for display. Efficient Architecture for Programmable FIR Filters," IEEE Trans. onA test case of the edge extraction filter is shown in Fig 6. In Circuits and Systems-11: Analog and Digital Signal Processing, Vol. 43, No. 9, PP: 637 – 644, Sep. 1996this test case, the intermediate result of the low-pass moving [5] Xiaodong Xu and Yiqi Zhou, "Efficient FPGA Implementation of 2-Daverage filter is return from the FPGA first as in Fig 6(b). DWT for 9/7 Float Wavelet Filter," Proc. of ICIECS 2009, pp:1-4, 2009Then, the final result of subtracting the blurred image from the [6] William Kamp and Andrew Bainbridge-Smith, "Multiply Accumulateoriginal one is shown in Fig 6(c). Unit Optimised for Fast Dot-Product Evaluation," Proc. of ICFPT 2007, pp: 349 - 352, 2007 [7] D. E. Atkins "Introduction to the Role of Redundancy in Computer Arithmetic," Computer Magazine, Volume 8, Issue 6, pp 74 – 77, June 1975. [8] Algirdas Avizieni "Binary-Compatible Signed-Digit Arithmetic", Pro- ceedings of AFIPS Conference, Volume 26, Part I, pp 664-672, 1964. [9] P. A. Ramamoorthy, Brahmaji Potu and G. Govind “DSP System Archi- tecture Using Signed-Digit Number Representation,” Proc. of ICASSP 1988, Vol 3, pp 1702 – 1705, Apr. 1988. [10] Israel Koren, Computer Arithmetic Algorithms, A. K. Peters. 2002.(a) Original image (b) Blurred image (c) Subtraction:(a) – (b). [11] A. D. Booth, "A Signed Binary Multiplication Technique," Quarterly Fig. 6 Edge extraction process using the SD moving average filter Journal of Mechanics and Applied Mathematics, vol. 4, no. 2, pp. 236- 240, 1951. [12] Hesham A. Altwaijry, “Area and Performance Optimized CMOS Mul- VII. SUMMARY AND CONCLUSIONS tipliers,” PhD Thesis, Stanford University, 1997. [13] Gary W. Bewick, "Fast Multiplication: Algorithms and Implementa- In this work, a 1D FIR filter is implemented. The signed- tion", A PhD Dissertation, Stanford University, 1994.digit arithmetic techniques are exploited to reduce addition [14] Hiroshi Makino, Yasunobu Nakase, Hiroaki Suzuki, Hiroyuki Morinaka,time. Booth-3 algorithm is utilized to speedup multiplication. Hirofumi Shinohara and Koichiro Mashiko, “An 8.8-ns 54 x 54-Bit Mul-For synthesis and place-and-rout phase, nine different configu- tiplier with High Speed Redundant Binary Architecture,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 6, June 1996.rations are made for the sample width W = 12, 24 and 48 bits [15] Nurettin Besli “A Novel Arithmetic Unit Using Redundant Binaryand for filter order N = 16, 32 and 64 samples. After the 1D Signed Digit Number System,” PhD dissertation, Florida Institute offilter is implemented, it is used to build a 2D FIR filter. A final Technology, July 2004.test and deployment on development board is carried out toserve an image processing application. Although signed-digit addition is carry-propagate-free, theconversion from signed-digit to 2’s complement is still a bot-tleneck of the filter delay. The number of partial products in-creases the multiplier size, which has a significant effect onthe filter size. Since the converter delay and the multiplier sizeboth depend on W, then W is still effective even with carry-propagate-free arithmetic. When considering using signed-digit number system in fil-ters, it is highly suggested to make the whole DSP system,which the filter is a part of, based on signed-digit representa-tion. That will lead to eliminating the converter from the filtercompletely and pushing it to the primary output of the system.Also, a higher radix Booth algorithm will help a lot in savingdelay and area. ACKNOWLEDGMENT This work has been partially supported by the National Pro-gram of Electronics, Communications and Photonics atKACST, and by the Center of Excellence in Information As-surance (CoEIA) at King Saud University (KSU). REFERENCES[1] Steven Smith, The Scientist and Engineers Guide to Digital Signal Processing, California Technical Publishing, 1997.[2] Yunhua Wang, "Multiplierless CSD Techniques for High Performance FPGA Implementation of Digital Filters," A Phd Dissertation, Universi- ty of Oklahoma, 2007.[3] Shyh-Feng Lin, Sheng-Chieh Huang, Feng-Sung Yang, Chung-Wei Ku, and Liang-Gee Chen, "Power-Efficient FIR Filter Architecture Design

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