DWARI AND PARSA: EFFICIENT HIGH-STEP-UP INTERLEAVED DC–DC CONVERTER WITH A COMMON ACTIVE CLAMP 67Fig. 1. (a) Coupled-inductor boost converter and (b) interleaved coupled-inductor boost converter.and high reliability with reduced size inductors and capaci-tors . Various advantages of interleaving are well reportedin the literature , , and . The schematic diagramof the proposed interleaved coupled-inductor boost converter isshown in Fig. 1(b).An interleaved boost converter with three winding-based cou-pled inductors is reported in  and . This converter hastwo interleaved phases, and the inductors of one interleavedphase are coupled with the inductors of the other interleavedphase. Therefore, with this converter the modular structure,which is a key beneﬁcial feature of the interleaved convert-ers, cannot be realized. Furthermore, the maximum number ofinterleaved phases is only two in this converter. The interleavedconverter, presented in this paper, is modular and can be de-signed for any number of phases.In a practical coupled inductor, there will be considerableamount of leakage inductance present due to the nonideal cou-pling between the primary inductor (L1) and the secondary in-ductor (L2) [see Fig. 2(a)]. The leakage inductance (Ll) causeshigh voltage stresses to the switches, large switching losses,parasitic ringing, and severe electromagnetic interference prob-lems, which degrade the converter performances  and .Resistor–capacitor–diode (RCD)-based snubber circuits can beused to mitigate the problem, but the losses in these circuits arevery high  and . Active-clamp circuits can be used toaddress this issue . But these clamp circuits are complexand costly. Moreover, the efﬁciency improvement in these cir-cuits is limited by the high conduction loss in the active-clampswitches , , and .Fig. 2. (a) Nonideal coupled-inductor boost converter with leakage inductanceand (b) coupled-inductor boost converter with capacitor and series diode-basedpassive-clamp circuit .A diode and capacitor-based passive-clamp circuit is pro-posed in . In this clamp circuit, the clamp capacitor (Cc) isdischarged to the output through the secondary side inductor(L2) of the coupled-inductor boost converter [see Fig. 2(b)].However, the clamp diode (Dc), in this circuit, is in series withthe coupled inductor. Therefore, it’s not only the leakage in-ductance current, but the total coupled-inductor current, whichﬂows through the clamp diode (Dc). This causes large losses inthe clamp diode. The clamp diode needs to be rated for the entirelarge power processed by the coupled-inductor boost converter.This can make the converter operation inefﬁcient for the higherpower applications. Furthermore, in this clamp circuit, to takethe advantages of the reduced switch voltage stress feature ofthe coupled-inductor boost converter, the clamp capacitor has tobe considerably large, capable of handling the high amount ofcharge, and discharge currents of the converter. Also, this willcause additional losses in the clamp capacitor. It can be notedthat, if any of the previously discussed clamp circuit is usedin the interleaved coupled-inductor boost converter; each of theinterleaved phases of the converter will require additional clampcircuit components and control circuits (for active clamp). Thiswill increase the cost, size, and complexity.A single active-clamp circuit can be proposed, in whichthe energy stored in leakage inductances of all the interleavedcoupled-inductor boost converters are gathered in a commonclamp capacitor . In each of the interleaved units, a clampdiode is connected from the common node of the coupled in-ductors to the clamp capacitor for providing the discharge pathof the leakage energy. Therefore, only the leakage currents ﬂowthrough the clamp diodes; this makes the clamping operationefﬁcient. A simple boost converter is used to recycle the leak-age energy, gathered in the clamp capacitor, to the output ofthe interleaved converter. The boost converter is controlled tokeep the clamp-capacitor voltage to a low level, and hence, thevoltage stress on the switches is low. This allows the use of
68 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011low-voltage and high-performance devices. It can be noted that,a conventional boost converter can be used for the clamp circuit,because the ratio of the output voltage to the clamp voltage isnot very high.This paper is organized as follows. Section II presentsthe coupled-inductor boost converter and their interleaving.Section III presents the proposed interleaved coupled-inductorboost converter with a common clamp boost converter. Detailedanalysis of the converter is presented in this section. Guidelinesfor the converter design are presented in Section IV. Simulationresults of a 1500 W converter, designed for the veriﬁcation ofproposed converter operation is presented in Section V. A con-verter prototype is developed based on this design. In Section VI,detailed experimental results and loss analysis of the prototypeare presented for validation. Section VII concludes the paper.II. COUPLED-INDUCTOR BOOST CONVERTERAND INTERLEAVINGA. Coupled-Inductor Boost ConverterAssume that the ideal coupled-inductor boost converter [seeFig. 1(a)] is operating under continuous conduction mode. Thewaveform of the primary side inductor current or the input cur-rent iL1 is shown in Fig. 3(a). The dynamic equation of the inputcurrent can be deﬁned asdiL1dt=⎧⎪⎨⎪⎩viL1, t ∈ [0, dT]vi − voL11N + 1, t ∈ [dT, T](1)where vi is the input voltage, vo is the output voltage, d is theduty ratio of the converter, T is the switching time period, and Nis the secondary inductor turns to primary inductor turns ratio.The steady-state operating points of the converter can be de-ﬁned as: Vi = vi, Vo = vo, and D = d. Using (1), under steadystate, the output voltage to input voltage ratio (2) can be obtainedby applying the volt-second balance condition to the primary in-ductor L1.VoVi=1 + ND1 − D. (2)It can be seen from (2) that, for the same voltage gain, theduty cycle can be reduced by increasing turn ratio. Considering,the coupling between the primary and secondary inductors isideal, the voltage stress Vcl on the switch can be obtained asVcl =NVi + VoN + 1. (3)The switch ON-state resistance RDS-ON varies almost pro-portionally with the square of the switch voltage rating. Hence,the conduction loss in the switch of a coupled-inductor boostconverter is a function of the turn ratio and the voltage step-up ratio. It would be a merit of interest to compare the switchconduction losses of a boost converter (Wsb) and a coupled-inductor boost converter (Wsc). The ratio of these two losses forvarious turns ratio (N) and step-up ratio (Vo/Vi) are plotted inFig. 3(b). From this ﬁgure, it can be seen that with appropriateFig. 3. (a) Gate pulses and primary inductor current of an ideal coupled-inductor boost converter and (b) switch conduction-loss comparison betweenboost converter (Wsb) and coupled-inductor boost converter (Wsc).choice of the turn numbers, the switch conduction losses in thecoupled-inductor boost converter can be signiﬁcantly reduced.B. Interleaved Coupled-Inductor Boost ConverterIn high current or high power application, interleaving of buckconverters or boost converters are well established  and .To take beneﬁt of the advantages of interleaving, interleavedcoupled-inductor boost converter can be used. In this approach,a single coupled-inductor boost converter cell is treated as aphase and n such phases are connected in parallel and operatedat the same switching frequency. Furthermore, all the phasesare operated at the same duty ratio, but they are phase shiftedby 2π/n radian electrical angle (see Fig. 4; n = 3). It canbe mentioned that due to interleaving, the effective switchingfrequency as seen by the input and the output of the interleavedconverter circuit is n times higher than the switching frequencyof a phase. Under normal or full-load condition, each of theinterleaved phases equally shares the total output load. But underlower output power demand condition, the number of operatingphases can be adjusted for maximum efﬁciency operation of theindividual phases.The number of parallel phases n in an interleaved convertermainly depends on the maximum power demand of the loadand the maximum power rating of the interleaved phases. In
DWARI AND PARSA: EFFICIENT HIGH-STEP-UP INTERLEAVED DC–DC CONVERTER WITH A COMMON ACTIVE CLAMP 69Fig. 4. (a) Three-phase interleaved converter with ideal coupled-inductorboost converters and (b) from top to bottom: gate pulses, primary inductorcurrents, and output capacitor charging current.this paper, the output load is considered to be 1500 W. Further-more, the maximum power rating of each interleaved phases isconsidered to be 500 W. Therefore, the number of phases tobe interleaved for supplying the total output power is n = 3.The input currents and the output currents of these interleavedphases are shown in Fig. 4(b). It can be noticed that the outputcurrents in the individual phases are discontinuous, and they arephase shifted by 2π/3 radians. The summation of the outputcurrents of the interleaved converters (ioc) charges the outputcapacitor and provides the current required by the load. For aﬁxed number of interleaved units, the ac component of this totalcurrent, which charges the output capacitor, is mainly decidedby the operating duty cycle of the converter. It can be noted thatfor three interleaved coupled-inductor boost converters (n = 3),the output ripple is minimum when the duty cycle D = 0.33 orD = 0.66 , . As the input voltage is low, with lower dutycycle D = 0.33, the input current peak and its rms value willFig. 5. (a) Parallel diode clamped coupled-inductor boost converter and(b) proposed interleaved coupled-inductor boost converter with single boostconverter clamp (for n = 3).be larger. This will cause higher losses and require devices withhigher current rating. Therefore, the larger duty cycle D = 0.66can be chosen for the nominal operation of the converter.III. INTERLEAVED COUPLED-INDUCTOR CONVERTERWITH A COMMON ACTIVE CLAMPIn the practical coupled inductors, due to the nonideal cou-pling between the primary and the secondary windings, therewill be leakage inductances. The equivalent circuit diagram ofa practical converter with the leakage inductance is shown inFig. 2(a). This leakage inductance will cause high-voltage spikeswhen the switch is turned off. This results in a high-voltage stressacross the switches and in ringing losses. It can be proposed toclamp the switch voltage to the output voltage, using a paralleldiode [see Fig. 5((a)]. In this clamp circuit, the energy stored inthe leakage inductance is discharged directly to the output by theparallel diode, and the switch voltage is clamped to the outputvoltage. It can be seen that this converter avoids the disadvan-tage of series conduction loss of the total power, but the switchvoltage stress becomes equal to the output voltage. So this con-ﬁguration does not take full advantages of the coupled-inductorboost topology, and hence, it is not suitable for high-step-upapplication where the output voltage level is high.
70 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011To lower the voltage stress on the switches close to the level ofthe voltage stress present in an ideal coupled-inductor boost con-verter, a common active-clamp circuit based on a boost convertercan be proposed, as shown in Fig. 5(b). In the proposed active-clamp circuit, in each phase, a clamp-diode (Dc1, Dc2, . . . Dcn )is connected to the common node of the primary inductor, thesecondary inductor, and the switch of an interleaved coupled-inductor boost converter. The cathode terminals of all the clampdiodes are connected to a clamp capacitor Cc. The energiesstored in the leakage inductors of the interleaved phases aredischarged through the clamp diodes and gathered in the clampcapacitor Cc. Furthermore, the boost converter is used to trans-fer the stored energy in the clamp capacitor to the output ofthe interleaved converters, while maintaining the voltage levelof the clamp capacitor to a lower level [see Fig. 5(b)]. Thevoltage stress on the switches (S1, S2, . . . Sn ) is decided bythis clamp-capacitor voltage. It can be suggested that any otherconverter topology, which can perform similar boost operationwhile maintaining the voltage level of the clamp capacitor canbe also used for the active-clamp operation.A. Converter AnalysisConsider the nonideal coupled-inductor boost converters areoperated under continuous conduction mode and a boost con-verter is used for active clamping of the interleaved converters.Under this condition, there are mainly three modes of operationin one switching cycle of a coupled-inductor boost converter.The operation modes for one of the interleaved phases (Phase-1)are shown in Fig. 6(a). The nonideal coupled inductors of theinterleaved phases can be modeled [see Fig. 6(a)] by a magne-tizing inductor (Lm1), which is connected in parallel with anideal transformer and a series leakage inductor (Ll1). The turnsratio of the transformer is equal to the primary to the secondaryturns ratio (1:N) of the coupled inductor. The value of the mag-netizing inductance can be obtained by subtracting the leakageinductance value from the primary winding inductance value ofthe coupled inductor. The input current (ii1) and the output cur-rent (io1) of the interleaved phase are deﬁned in this equivalentmodel, Fig. 6(a). The key waveforms during the three operationmodes are presented in Fig. 6(b). These operation modes arediscussed as follow.Mode-1(t ∈ [t0, t1]): This mode begins when the switch S1is turned on. The output diode D1 is reverse biased, and theinput voltage Vi charges the primary inductor (Lm1) and theleakage inductor (Ll1). The rate of rise of the input current ofthe converter can be written asdi1dt=viLm1 + Ll1t ∈ [0, dT] . (4)Consider, in steady state, the output power of the Phase-1of the converter is Po1 and the efﬁciency of the converter is η.Using (2) and (4), the peak input current Ii1P can be obtainedasIi1P =Po1ηVi1 + N1 + ND+Vi2DTLl1 + Lm1. (5)Mode-2(t ∈ [t1, t2]): This mode starts when the switch S1 isturned off. The leakage inductor (Ll1) forward biases the clampdiode Dc1, and the energy stored in the leakage inductor isdischarged to the clamp capacitor Cc. This causes a dischargecurrent spike (icl1). The peak of this current is equal to themaximum value of the input current (Ii1P ), reached at the endof Mode-1. At the same instant, when the switch S1 is turnedoff, the stored energy in the magnetizing inductor (Lm1) forwardbiases diode D1 at the secondary side of the coupled inductor.The voltage difference between the converter output and theinput (Vo − Vi) is divided as per the turns ratio of the idealtransformer and the voltage at the point A [see Fig. 6(a)] isdeﬁned by (3). It can be noted that the fall rate of the leakagecurrent is decided by the voltage difference between the clamp-capacitor voltagevc and the voltage the node A. This can bepresented by (6).dil1dt=Nvi + voN + 1− vc1Ll1t ∈ [t1, t2] . (6)In steady state, the total fall time for the leakage inductorcurrent τlf can be obtained from (5) and (6). This can be deﬁnedasτlf =Ii1P (N + 1)Vc(N + 1) − (NVi + Vo)Ll1 t ∈ [t1, t2]. (7)From (6) and (7), it can be seen that the fall time of the inductorcurrent can be reduced by increasing the clamp voltage (Vc).These considerations should be taken into account for designingthe clamp boost converter and the voltage rating of the switchesin the interleaved coupled-inductor boost converters. During thismode, the current fall rate in the magnetizing inductor can befound asdim1dt=vi − voN + 11Lm1t ∈ [t1, t2] . (8)The output current (io1) and the input current (ii1) of theconverter can be obtained asio1 =im1 − il1N + 1t ∈ [t1, t2]ii1 = il1 + io1 =im1 + Nil1N + 1t ∈ [t1, t2]. (9)Form (9), it can be seen that the slope of the input and theoutput current of the converter during Mode-2 are deﬁned by theslopes of the magnetizing current (im1) and the leakage inductorcurrent (il1). As the leakage inductance value is much smallerthan the magnetizing inductance value form (6) and (8), it can beseen that the slopes of the input and the output currents in Mode-2 are mainly decided by the slope of the leakage inductancecurrent.Mode-3(t ∈ [t2, t3]): This mode begins when the leakage in-ductor current (ii1) value has become zero, and the leakageenergy is completely discharged. The clamp diode Dc1 is re-versed biased by the clamp voltage Vc. The output diode D1remains forward biased and the voltage at the point A is deﬁnedby (3). The energy to the output is transferred form the mag-netizing inductor and from the source. The switch S1 remainsturned off.
DWARI AND PARSA: EFFICIENT HIGH-STEP-UP INTERLEAVED DC–DC CONVERTER WITH A COMMON ACTIVE CLAMP 71Fig. 6. (a) Operation modes (Mode 1: t ∈ [t0 , t1 ], Mode 2: t ∈ [t1 , t2 ], Mode 3: t ∈ [t2 , t3 ]) and (b) key waveforms during the operation modes.B. Clamp Boost ConverterFrom the previous analysis, it can be seen that the energystored in all the leakage inductances of the interleaved coupled-inductor boost converters are discharged to the capacitor (Cc).To clamp the switch voltages of the interleaved converter, thevoltage of this capacitor has to be controlled. In this paper, asimple boost converter is used for this purpose. The boost con-verter transfers the leakage energy stored in this clamp capacitor(Cc) to the output and maintains its voltage to a desired clampvoltage level [see Fig. 5(b)]. So, the power rating of the clampboost converter is decided by the maximum total leakage en-ergy of the interleaved converters. It can be noted that unlike theregular boost converters, which have a ﬁxed input voltage and avariable output voltage, this clamp boost converter has a ﬁxedoutput voltage but a variable input voltage. This is because the
72 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011total leakage energy of the interleaved converters is very smallcompared to the total output power of the interleaved converters.Therefore, the voltage at the output of the clamp boost converteris decided by the interleaved coupled-inductor boost converters.The duty ratio of the clamp boost converter can be controlled todischarge the leakage energy stored in the clamp capacitor (Cc)to the output dc bus and maintain its input voltage to a refer-ence clamp voltage level. The clamp voltage level decides thevoltage stresses on the switches of the coupled-inductor boostconverters. With low switch voltage stress, the converter can bedesigned to deliver power at high efﬁciency even when consid-erable amount of leakage inductance is present in the coupleinductors. The discussion about the operation of the standardboost converter is avoided here for brevity. But the design con-sideration to decide the parameters of the boost converter withrespect to the parameters of the interleaved coupled-inductorboost converter is presented as follows.It can be seen that when the switch of a coupled-inductor boostconverter is turned off (Mode-2 and Mode-3) and the outputdiode is on, the voltage at the common node of the two coupledinductors [point A in Fig. 6(a)] is deﬁned by (3). Therefore,for successful operation of the active-clamp circuit, the voltagelevel at the clamp capacitor (Cc) should be maintained abovethe voltage level of the point A. Therefore the lower bound forthe clamp voltage (Vc min) can be related asVc min >NVi + VoN + 1. (10)The maximum value of the clamp voltage that can be allowedcan be decided from the information of the maximum voltagerating of the devices of the interleaved coupled-inductor boostconverter.Consider the total leakage power from all leakage inductancesis Plt. This leakage power can be obtained asPlt = fi12nu=1Llu (IiuP )2(11)where fi is the switching frequency of the interleaved coupled-inductor boost converters, n is the number of total interleavedphases, and Llu and IiuP are the primary leakage inductance andthe peak primary inductor current in the uth phase, respectively.The peak currents can be calculated from (5). For simplicity,it can be considered that the leakage inductances and the peakcurrents of the different phases are equal.The clamp boost converter can be operated either in con-tinuous conduction mode (CCM) or in discontinuous conduc-tion mode (DCM). Under CCM, the switching losses are morethan the switching losses under DCM. However, the conductionlosses under the DCM are more than the conduction losses underthe CCM. The clamp boost converter, considered in this study,processes small amount of power obtained from the leakage in-ductances of the interleaved converters and the voltage level atthe clamp capacitor (Vc min) is quite higher than input voltagelevel (Vi). Therefore, the average inductor current of the clampboost converter is small. But the MOSFET of the clamp boostconverter switches at high voltage levels. Therefore, in this pa-per, the clamp boost converter is chosen to operate in DCM toFig. 7. (a) From top to bottom: gate pulses to the three interleaved converter(n = 3), gate pulses to the clamp boost converter, and the inductor current of theclamp boost converter, and (b) control circuit block diagram for the clamp-boostconverter.reduce the losses in the clamp boost converter. The gate pulsesto the MOSFET of the clamp boost converter and the current inthe boost inductor under DCM operation are shown in Fig. 7(a).Consider the operating duty cycle, the switching frequency andthe inductance value of the clamp boost converter are Dc, fc,and Lb, respectively. Under DCM operation, the average in-put power of the clamp boost converter, supplied by the clampcapacitor Cc can be derived asPib =12V 2c D2cfcLb11 − Vc/Vo. (12)Under steady-state condition, the average leakage power (Plt)discharged to the clamp capacitor should be equal to the averageinput power of the boost converter (Pib). Therefore, using (11)and (12) the value of the boost inductor can be obtained asin (13). This calculation can be used for designing the boostinductor.Lb =1fifcV 2c D2cnu=1 Llu (IiuP )211 − Vc/Vo. (13)To clamp the voltage stresses on the switches of the inter-leaved coupled-inductor boost converters to a low level, thevoltage of the clamp capacitor should be maintained at a desiredreference value. To achieve this, the clamp-capacitor voltage(the input of the clamp boost converter) is sensed and the clampboost converter is controlled in a closed loop. The block diagram
DWARI AND PARSA: EFFICIENT HIGH-STEP-UP INTERLEAVED DC–DC CONVERTER WITH A COMMON ACTIVE CLAMP 73of the closed-loop control scheme applied to the clamp-boostconverter is presented in Fig. 7(b). Based on the error informa-tion between the sensed clamp capacitor voltage (vb) and thereference clamp voltage (v∗br ), a suitable controller is used toestimate the duty cycle of the converter. It can be noted that,in the clamp-boost converter, the input voltage decreases withthe increase of the duty cycle. Therefore, in this paper, the errorinformation is obtained by subtracting the reference clamp volt-age from the measured clamp-capacitor voltage. The estimatedvoltage of the controller is used by a pulse width modulationcontroller to generate the gate pulses for the switch of the clampboost converter. A suitable driver is used to drive the MOSFETof the converter.It can be mentioned that, for n = 3, the frequency of the volt-age ripple at the output capacitor of the interleaved coupled-inductor boost converter is three times the switching fre-quency of each interleaved coupled-inductor boost converter[see Figs. 4(b) and 5(b)]. For this reason, in this paper, theswitching frequency of the clamp boost converter is chosento be three times the switching frequency of the interleavedconverters(fc = 3fi).IV. DESIGN GUIDELINESConsidering the standard power train architectures of the EV,HEV, FCV, and telecom power systems –, , and ,in this paper, the nominal input voltage and the output volt-age of the converter are chosen as 42 and 350 V, respec-tively. Therefore, the voltage step-up ratio of the converter isVo/Vi = 8.33. As discussed earlier, in Section II, the numberof interleaved phases of the converter is n = 3 and for optimalperformance of interleaved converter, the chosen nominal dutyratio is D = 0.66. The key converter design step is the selectionof turns ratio of the coupled inductors (N), which can performthe required voltage step-up operation while operating at theselected nominal duty ratio. To consider effect of the leakageinductance on the voltage step-up ratio of the coupled-inductorboost converter, volt–second balance can applied both on themagnetizing inductor (Lm1) and on the leakage inductor of acoupled-inductor boost converter(Ll1). The voltage gain of theconverter can be obtained asVoVi= 1 +D(1 + N)1 − DK, K =Lm1Lm1 + Ll1. (14)Fig. 8 presents the design plots for the voltage gain (Vo/Vi)versus duty ratio (D) of a coupled-inductor boost converter fordifferent turns ratios(N). In this ﬁgure, the value of K = 0.97.Appropriate turns ratio of the converter can be selected fromthe chart by using the voltage gain and nominal duty cycleinformation.The voltage rating of the switches of the coupled-inductorboost converters is decided by the value of clamp voltage andthe safety margin. The clamp voltage is mainly decided by thevoltage at the common node of the coupled inductors(Vcl), dur-ing the turn-OFF period of the switches. Therefore, the voltageVcl is a key design parameter that has to be obtained. Using (3)and (14), the ratio between the voltage Vcl and the input voltageFig. 8. Design plot: voltage gain of the converter (Vo/Vi) versus duty ratio (D)for different turns ratios (N); (K = 0.97).Vi can be expressed as following (15).VclVi=DK − D + 11 − D. (15)Interestingly, it can be found that, when N = 0, the outputvoltage to input voltage gain (Vo/Vi) in (14) is equal with theratio between the voltage Vcl and the input voltage Vi in (15).Therefore, the design curve for N = 0, in Fig. 8, can be used toobtain the value of the voltage Vcl. Based of the values of Vcl,leakage inductance, peak of the primary inductor current, andthe clamp voltage of the interleaved converter can be designed(5, 7, and 15).To select the diodes in the secondary side of the interleavedcoupled-inductor boost converters, the maximum reverse-biasvoltage, the peak forward current, and the average forward cur-rent in the diodes are to be known. It can be seen from Fig. 6,when the switch is turned on (Mode-1), the secondary side diodeDo1 remains turned off, and the input voltage is applied acrossthe primary side winding of the coupled inductor. The voltageapplied across the primary side of the coupled-inductor willbe reﬂected on its secondary side. Therefore, under this con-dition, the maximum reverse-bias voltage, VDor applied acrossthe secondary side diode Do1 can be obtained asVDor = ViLm1Lm1 + Ll1N − ViLlLm1 + Ll1+ Vo. (16)Considering that the leakage inductance Ll1 is smaller com-pared to the magnetizing inductance Lm1, (16) can be simpliﬁedasVDor = ViN + Vo. (17)The maximum reverse-bias voltage applied across the sec-ondary side diode can be obtained by using the aforementionedequation.Under steady state, the average current through the secondarydiode of an interleaved coupled-inductor boost converter (e.g.,Do1 in Phase-1) can be obtained by applying the charge balancetheory on the output capacitor. Therefore, it can be perceivedthat the average forward current in the secondary diode is equal
74 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011TABLE IKEY PARAMETERS OF THE CONVERTERto the output dc current of the interleaved phase. The peak valueof the pulsating current through the secondary side diode isdecided by the input peak current Ii1P (5) of the phase; reachedat the end of Mode-I, Fig. 6(b). Considering that the energystored in the leakage inductor is very small compared to theenergy stored in the magnetizing inductor, the peak value ofcurrent Ii2P in the secondary side diode can be obtained asIi2P = Ii1P11 + N=Po1ηVi11 + ND+Vi2DTLl1 + Lm111 + N. (18)The peak forward current rating of the secondary side diodescan be decided by using the aforementioned (18). The peakforward current in the clamp diodes (e.g., Dc1 in Phase-1) ofthe proposed active-clamp circuit (see Fig. 6) is equal to theinput peak current Ii1P . Therefore, (5) can be used to calculatethe peak forward current rating of the clamp diodes.V. SIMULATION RESULTSA 42 to 350 V step-up converter with nominal output powerrating of 1500 W is designed and simulated to verify the pro-posed concept. Converter analysis and design guidelines, pre-sented in the previous sections, are used for this purpose. Theconverter consists of three interleaved coupled-inductor boostconverters and a common clamp boost converter.Simulations of the converter are carried out in SABER. Thekey converter parameters are listed in Table I. The estimatedleakage inductance of the converter is 1.7 μH. The interleavedconverter is designed to operate at a switching frequency of25 kHz. The calculated lower limit of the clamp voltage ofthe designed converter is about 120 V. To limit the fall timeof the leakage inductor current to about 2 μs, the clamp volt-age level of the converter is designed to be 140 V (5, 7). Thisclamp voltage value decides the maximum voltage stress of theswitches of the coupled-inductor boost converter. The selectedMOSFET for the interleaved coupled-inductor boost converteris STW75NF20 (200 V, Rds−ON = 33 mΩ; STMicroelectron-ics). In each interleaved phase, three MOSFETs are connectedin parallel to realize the switch. The output diode selected for theconverter is FFH30S60 S (600 V; Fairchild Semi.). The switchFig. 9. (a) Drain-to-source voltage of the switch in a coupled-inductor boostconverter without any clamping and (b) output voltage, clamp voltage and drain-to-source voltage of the switch in a coupled-inductor boost converter with theproposed active-clamp circuit.selected for the clamp boost converter is STP17NK40Z (400 V,ST Micro.). These device models are used in the simulation.The simulated voltage stress across the MOSFETs of theinterleaved converter, when no clamping circuit is employed,is shown in Fig. 9(a). The voltage across the MOSFETs of theinterleaved converters with the common clamp boost converteris shown in Fig. 9(b). It can be seen that the high voltage spikescaused by the leakage inductors can be successfully reduced toa lower level by the proposed clamp boost converter. The outputvoltage level and the clamp voltage levels of the converter underfull-load condition are also presented in Fig. 9(b).The total input current of the converter is presented inFig. 10(a). The currents in the primary inductors of the threephases of the interleaved converter are also shown in this ﬁgure.It can be seen that the phase currents are equal in amplitude andphase shifted by 120◦. The primary current, secondary current,and leakage inductor current of one phase of the interleaved con-verter are shown in Fig. 10(b). From this ﬁgure, it can be seenthat the energy stored in the leakage inductance is discharged tothe clamp-capacitor in the form of a current spike. These simu-lations results agree with the analysis of the converter presentedin Section III. The current in the inductor of the clamp boostconverter and the gate pulses to the MOSFET of the clamp boostconverter are shown in Fig. 11. It is calculated from the simu-lation and the previous analysis that the total leakage energy ofthe interleaved coupled-inductor boost converter is 44.2 W. Theestimated efﬁciency of the converter is 95.4%. The simulation
DWARI AND PARSA: EFFICIENT HIGH-STEP-UP INTERLEAVED DC–DC CONVERTER WITH A COMMON ACTIVE CLAMP 75Fig. 10. (a) From top to bottom: total input current of the converter, inputcurrents of the interleaved coupled-inductor boost converters, and (b) primarycurrent, secondary current, and leakage current in a phase of the interleavedcoupled-inductor boost converters.Fig. 11. (a) Gate pulses to the clamp boost converter and (b) inductor currentof the clamp boost converter.results show that the proposed converter can successfully handlethe high-input current and perform voltage-step-up operation ata high efﬁciency.It can be mentioned that if the proposed boost converter basedactive clamping circuit is not used, the leakage energy cannotbe recycled. Therefore, due to the large voltage stresses [seeFig. 9(a)], MOSFETs of much higher voltage ratings, whichhave large ON-state resistances RDS-ON have to be used torealize the switches of the interleaved converters. Furthermore,additional losses will occur due to the parasitic ringing in theFig. 12. Converter prototype: three interleaved coupled-inductor boost con-verters with a common clamp boost converter.Fig. 13. Gate pulses to the interleaved coupled-inductor boost converters(10 V/div).circuit. From the simulations, it is estimated that if the proposedactive clamping circuit is not used and higher voltage MOSFETs(600 V) are utilized to realize the switches, the efﬁciency of theinterleaved converter is about 82.7%. This is much lower thanefﬁciency of the converter with boost active-clamp circuit.VI. EXPERIMENTAL VALIDATIONFor validation of the proposed converter and its analysis in theprevious sections, a prototype of 1500 W interleaved coupled-inductor boost converter with a common clamp boost converteris developed and tested. The prototype is shown in Fig. 12. Thecoupled inductors of the interleaved converter are designed withKool Mμ KE5528 E-cores. The primary winding of the coupledinductor has 21 turns (125 × 40 litz wire, three parallel wires)and the secondary winding is made of 62 turns (125 × 40 litzwire, single wire).
76 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011Fig. 14. From top to bottom (50 V/div): converter output voltage (350 V),clamp voltage (140 V), and drain-to-source voltage (VD S ), measured in aninterleaved coupled-inductor boost converter.Fig. 15. Input currents of the three interleaved coupled-inductor boost con-verters (10 A/div).The gate pulses applied to the MOSFETs of the interleavedcoupled-inductor boost converter are shown in Fig. 13. Theswitching frequency of the converter is 25 kHz. The measuredinput and output voltages of the converter are 42 and 350 V, re-spectively. The clamp voltage is maintained at 140 V. The mea-sured output voltage and clamp voltages are shown in Fig. 14. Inthis ﬁgure, the measured drain-to-source voltage of a MOSFETin an interleaved coupled-inductor boost converter is also pre-sented. It can be seen from this ﬁgure that the proposed clamp-ing arrangement can successfully clamp the voltage across theswitch to a low level, close to the voltage stress offered by anideal coupled inductor.The input currents of the interleaved coupled-inductor boostconverters are shown in Fig. 15. The total input current of theconverter is shown in Fig. 16. It is measured that the averageFig. 16. Total input current of the converter (10 A/div).Fig. 17. From top to bottom: clamp voltage (50 V/div), input current of phase-1of the interleaved converters (5 A/div), and leakage current of phase-1 (5 A/div).Fig. 18. From top to bottom: clamp voltage (50 V/div), leakage currents ofthe interleaved converter charging the clamp capacitor (5 A/div).
DWARI AND PARSA: EFFICIENT HIGH-STEP-UP INTERLEAVED DC–DC CONVERTER WITH A COMMON ACTIVE CLAMP 77Fig. 19. From top to bottom: gate pulses to the clamp boost converter(10 V/div) and inductor current of the clamp boost converter (1 A/div).TABLE IILOSS DISTRIBUTIONvalue of the input current is 37.65 A. The leakage current inphase-1 of the interleaved converter and the input current of thatphase are presented in Fig. 17. The slope of the leakage currentis decided by the leakage inductor and the voltage differencebetween the clamp voltage and the voltage at the common nodeof the primary and secondary inductors. It can be seen that thefall time of the leakage current is close to 2μs. The measuredleakage currents from all the three interleaved coupled-inductorboost converters, which charge the clamp capacitor, are pre-sented in Fig. 18. These measurements agree with the previousanalysis and simulation results. The gate pulses to the MOS-FET of the clamp boost converter and the inductor current inthat converter are presented in Fig. 19. As per the presenteddesign, the clamp boost converter is operated under DCM. Theoperating duty cycle of the clamp boost converter, estimated bythe controller, is 0.28. It is obtained from the measurements thatthe average leakage power of the interleaved converters is about47.5 W, which matches with the previous calculation.To ﬁnd the loss distribution in the converter, the currents andvoltages in different components are measured or estimated.The various loss components in the converter are presented inTable II. The efﬁciency of the converter, calculated from thisloss analysis is about 95.1%. The measured efﬁciency of theconverter is about 94.8%. Therefore, it can be seen that theproposed interleaved coupled-inductor boost converters with acommon boost clamp can perform high-step-up operation withhigh efﬁciency.VII. CONCLUSIONCoupled-inductor boost converters can be interleaved toachieve high-step-up power conversion without extreme dutyratio operation while efﬁciently handling the high-input cur-rent. In a practical coupled-inductor boost converter, the switchis subjected to high voltage stress due to the leakage inductancepresent in the nonideal coupled inductor. The presented active-clamp circuit, based on single boost converter, can successfullyreduce the voltage stress of the switches close to the low-levelvoltage stress offered by an ideal coupled-inductor boost con-verter. The common clamp capacitor of this active-clamp circuitcollects the leakage energies from all the coupled-inductor boostconverters, and the boost converter recycles the leakage ener-gies to the output. Detailed analysis of the operation and theperformance of the proposed converter were presented in thispaper. It has been found that with the switches of lower voltagerating, the recovered leakage energy, and the other beneﬁts ofan ideal coupled-inductor boost converter and interleaving, theconverter can achieve high efﬁciency for high-step-up powerconversion. A prototype of the converter was built and testedfor validation of the operation and performance of the pro-posed converter. The experimental results agree with the analy-sis of the converter operation and the calculated efﬁciency of theconverter.REFERENCES L. Solero, A. Lidozzi, and J. A. Pomilio, “Design of multiple-input powerconverter for hybrid vehicles,” IEEE Trans. Power Electron., vol. 20,no. 5, pp. 107–116, Sep. 2005. A. A. Ferreira, J. A. Pomilio, G. Spiazzi, and de Araujo Silva, “Energymanagement fuzzy logic supervisory for electric vehicle power suppliessystem,” IEEE Trans. Power Electron., vol. 20, no. 1, pp. 107–115, Jan.2008. A. Emadi, K. Rajashekara, S. S. Williamson, and S. M. Lukic, “Topo-logical overview of hybrid electric and fuel cell vehicular power systemarchitectures and conﬁgurations,” IEEE Trans. Veh. Technol., vol. 54,no. 3, pp. 763–770, May 2007. J. Bauman and M. Kazerani, “A comparative study of fuel cell-battery, fuelcell-ultracapacitor, and fuel cell-battery-ultracapacitor vehicles,” IEEETrans. Veh. Technol., vol. 57, no. 2, pp. 760–769, Mar. 2008. Q. Zhao and F. C. Lee, “High-efﬁciency, high step-up DC–DC con-verters,” IEEE Trans. Power Electron., vol. 18, no. 1, pp. 65–73, Jan.2003. I. Barbi and R. Gules, “Isolated DC-DC converters with high-output volt-age for TWTA telecommunication satellite applications,” IEEE Trans.Power Electron., vol. 18, no. 4, pp. 975–984, 2003. A. Reatti, “Low-cost high power-density electronic ballast for automotiveHID lamp,” IEEE Trans. Power Electron., vol. 15, no. 2, pp. 361–368,Mar. 2000.
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