Accurate and efficient on chip spectral analysis
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Accurate and efficient on chip spectral analysis

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  • 1. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 Accurate and Efficient On-Chip Spectral Analysis for Built-In Testing and Calibration Approaches Hari Chauhan, Student Member, IEEE, Yongsuk Choi, Marvin Onabajo, Member, IEEE, In-Seok Jung, Student Member, IEEE, and Yong-Bin Kim, Senior Member, IEEE Abstract— The fast Fourier transform (FFT) algorithm is widely used as a standard tool to carry out spectral analysis because of its computational efficiency. However, the presence of multiple tones frequently requires a fine frequency resolution to achieve sufficient accuracy, which imposes the use of a large number of FFT points that results in large area and power overheads. In this paper, an FFT method is proposed for on-chip spectral analysis of multi-tone signals with particular harmonic and intermodulation components. This accurate FFT analysis approach is based on coherent sampling, but it requires a significantly smaller number of points to make the FFT realization more suitable for on-chip built-in testing and calibration applications that require area and power efficiency. The technique was assessed by comparing the simulation results from the proposed method of single and multiple tones with the simulation results obtained from the FFT of coherently sampled tones. The results indicate that the proper selection of test tone frequencies can avoid spectral leakage even with multiple narrowly spaced tones. When low-frequency signals are captured with an analog-to-digital converter (ADC) for on-chip analysis, the overall accuracy is limited by the ADC’s resolution, linearity, noise, and bandwidth limitations. Post-layout simulations of a 16-point FFT showed that third-order intermodulation (IM3) testing with two tones can be performed with 1.5-dB accuracy for IM3 levels of up to 50 dB below the fundamental tones that are quantized with a 10-bit resolution. In a 45-nm CMOS technology, the layout area of the 16-point FFT for on-chip built-in testing is 0.073 mm2 , and its estimated power consumption is 6.47 mW. Index Terms— Analog testing, built-in testing (BIT), coherent sampling, digitally assisted calibration, fast Fourier transform (FFT), on-chip distortion analysis, spectral testing. I. I NTRODUCTION D IGITALLY assisted analog design [1] and integrated transceiver calibration [2], [3] approaches are gaining popularity in ensuring efficient and reliable mixed-signal systems in nanoscale CMOS technologies. One design aspect is to equip analog blocks with performance-tuning features that allow the recovery from process variations and faults. Examples of such tuning mechanisms include input impedance matching, gain and center frequency tuning for low-noise amplifiers [3]–[5], second-order nonlinearity and mismatch Manuscript received August 13, 2012; revised December 8, 2012; accepted February 24, 2013. The authors are with the Electrical and Computer Engineering Department, Northeastern University, Boston, MA 02115 USA (e-mail: chauhan.h@husky.neu.edu; choi.yon@husky.neu.edu; monabajo@ece.neu.edu; jung.i@husky.neu.edu; ybk@ece.neu.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2013.2251919 correction for mixers [6]–[8], as well as linearity enhancements for baseband filters [9]. The other aspect related to digitally assisted design is the extraction of performance metrics on the chip to enable one-time or periodic calibrations. Many performance characteristics can be observed based on the output spectrum of a circuit under test (CUT) or a chain of analog blocks, which has led to on-chip spectrum analyzers that emulate conventional off-chip instrumentation [10], [11]. Alternatively, calibration methods have been proposed that incorporate existing or dedicated analog-to-digital converter (ADC) and digital signal processing resources to directly quantize the output signals of analog circuits for the computation of the fast Fourier transform (FFT) and automatic tuning with digital-to-analog converters (DACs) [12], [13]. Extraction of circuit linearity parameters with the latter approach calls for efficient FFT implementations, which is the focus of this paper. The presented method leverages that the frequencies for two-tone tests can be selected by the designer of the built-in test (BIT) or built-in calibration (BIC) scheme to circumvent inaccuracies due to spectral leakage while using a small number of FFT points. This capability to accurately measure the power of the tones as well as their distortion and intermodulation products with an efficient on-chip FFT can also find application in loopback testing techniques with spectral estimation such as in [14] and [15]. Fig. 1 visualizes the BIC approach that is the target application for the presented FFT realization. The calibration method could be applied to an individual analog block or a cascade of blocks. In practice, the maximum test signal frequency depends on the highest possible ADC sampling frequency and clock frequency for the FFT computation. Thus, a downconversion within the chain of blocks under calibration is assumed if it involves RF circuits. In such a case, an effective calibration might require sequential injection of test signals at various locations along the analog signal chain through the use of switches as in [16]. Alternatively, it has been shown that an envelope detector can be placed at the output of an RF circuit to extract the signal characteristic at lower frequencies. For example, it is outlined in [17] how an input signal with two test tones ( f 1 , f 2 ) allows to determine thirdorder linearity characteristics of the CUT by monitoring the spectral components at frequencies up to 3 · ( f 2 − f 1 ), which can be assured to be low by selecting appropriate test tone frequencies with narrow spacing. This permits the use of lower sampling frequencies. The output signal is quantized by the on-chip ADC in Fig. 1 prior to the FFT computation, 1063-8210/$31.00 © 2013 IEEE
  • 2. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 2 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS of > 1 mm2 and > 20 mW, respectively. The purpose of the proposed FFT utilization approach is to reduce the overheads associated with on-chip FFT implementations for built-in testing applications because mixed-signal systems-on-a-chip frequently do not provide room for inclusion of such extensive digital signal processing resources. A. Basic FFT Algorithm Fig. 1. On-chip BIC approach with spectral testing. which may be implemented with existing system resources or extra components. An adaptive biasing block (that typically includes DACs) enables the digitally assisted performance tuning for the analog circuit(s) based on the digital extraction of gain, linearity, or frequency response parameters. Most related circuit-level and system-level considerations in the above-mentioned references are outside of the scope of this paper, in which the main focus is on the realization of suitable area- and power-efficient FFT implementations to support on-chip BIT and BIC approaches. One way to characterize a nonlinear circuit is by applying a test tone at the input and measuring the harmonic distortion (HD) magnitudes in the spectrum at multiples of the input frequency. This approach is feasible at low frequencies but less practical at RFs because of the difficulties associated with measuring high-frequency harmonics. Furthermore, these harmonics typically fall outside the bandwidth of narrow-band RF amplifiers and other receiver blocks. For this reason, two-tone test methods have been developed. For example, the characterization of the thirdorder linearity can be conducted by applying two closely spaced input tones ( f 1 , f 2 ) and measuring the third-order intermodulation product at (2 · f 2 − f 1 ) or (2 · f 1 − f 2 ), which can be nearby frequencies within the CUT’s passband [18]. This paper is organized as follows. In Section II, the basic FFT and application-related constraints are discussed. In Section III, the coherent sampling approach and its limitations are reviewed. The proposed approach is presented in Section IV, for which comparative simulation results are provided in Section V. In Section VI, implementation details and post-layout simulation results are discussed. Conclusion is given in Section VII. The basic FFT algorithm calculates the spectrum of the input waveform only for certain discrete frequencies known as FFT bins that are separated by the fundamental frequency ( f ) of the FFT. The f strictly depends on the sampling frequency ( f samp ) and the length of the FFT (NFFT) as follows: f ≡ f samp /NFFT. Thus, to avoid spectral leakage and to accurately measure the frequency components of the input waveform, its frequencies have to be exact integer multiples of f . To achieve high-frequency resolution, either the sampling frequency has to be decreased or the length of the FFT has to be increased. Since the sampling frequency should meet the Nyquist criterion, the sampling frequency condition can typically not be relaxed when the goal is to perform on-chip analysis of the highest possible signal frequency under the constraints of a given CMOS technology. In contrast, increasing the length of the FFT to achieve better frequency resolution results in an additional area overhead and thereby reduces the feasibility of an FFT implementation for on-chip testing applications. Therefore, the simple FFT algorithm is most useful for single-tone testing when the input waveform contains a single frequency component and its higher order harmonics. On the other hand, spectral leakage is difficult to avoid in multi-tone testing cases, where one or more of the input tones might not be the integer multiple of f . A useful approach to alleviate the leakage effect is to choose a suitable window function that minimizes the energy spreading [22], [23]. However, the use of a windowing technique introduces various other flaws into the spectrum such as frequency/amplitude imprecision, broadening of main lobe width, and creation of side lobes. Moreover, windowing operations require additional computational resources. III. C ONVENTIONAL C OHERENT S AMPLING Coherent sampling is a useful and efficient technique for evaluating the spectral performance of analog/mixed signal circuits [24]–[27], because it increases the FFT accuracy and eliminates the need for a window function if certain conditions are met. Coherent sampling of a single tone assures that its power in the spectrum is contained in exactly one frequency bin. The condition for coherent sampling is given by f in / f samp = Ncycle /NFFT II. FFT FOR T ESTING A PPLICATIONS Various on-chip FFT implementations have been developed for communication systems such as those using orthogonal frequency division multiplexing that requires a combination of high throughput rate and accuracy [19], [21]. These requirements typically translate into a large number of FFT points (e.g., 64–2048), resulting in area and power requirements (1) where f in is the input frequency, f samp is the sampling frequency, Ncycle is the integer number of cycles of the signal to be sampled, and NFFT is the length of the FFT engine. To ensure coherent sampling, one can first determine the number (usually prime) of integer cycles (Ncycle ) that fits into the predefined sampling window, and use it to approximate the input frequency to the near optimal frequency that exactly
  • 3. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. CHAUHAN et al.: ACCURATE AND EFFICIENT ON-CHIP SPECTRAL ANALYSIS 3 matches with one of the discrete frequency bins in the spectrum for the given FFT length [28], [29]. Under the condition in (1), there will not be any leakage because the coherent sampling guarantees an exact integer number of input signal cycles. Coherent sampling methods can be used for performing single-tone testing, because the nearby optimal input frequency can be calculated for the single-frequency component. When several input tones are present, it is typically not guaranteed that the tones are integer multiples of the FFTs fundamental frequency, and thus spectral leakage will occur in many multitone testing scenarios. This approach not only eliminates the spectral leakage problem but it also offers the following benefits when used either for single-tone or multi-tone testing. 1) Accurate spectral characteristics can be determined for a number of higher order harmonics of the input test tone. 2) Flexibility in choosing Ncycle and NFFT for the given input test tone fin . Any values for Ncycle and NFFT can be used for spectral testing, provided that the ratio of NFFT and Ncycle is chosen such that the calculated f sampCoh satisfies the Nyquist criteria for the given f in and for the desired higher order harmonics of fin . For example, with Ncycle = 1, and NFFT = 16, f sampCoh is 16 · f in ; which means that the spectrum of f in and its harmonics until the seventh order can be precisely calculated without aliasing and spectral leakage. 3) Accurate spectral characteristics are achievable even with short FFT length, for example, an FFT with 16 points. Thus, the presented approach offers significant savings in terms of area, power, and the required computational resources. 4) The noise levels with the discussed approach are generally low, because spectral leakage is avoided based on the coherent sampling characteristics. In a production test environment, test signals with coherent input frequencies can be generated arbitrarily with standard automatic test equipment. Even though the proposed on-chip FFT engine could be utilized to reduce off-chip resource requirements and the number of required test outputs of the chip for test cost reduction, it is envisioned to be more valuable during in-field testing and self-calibrations. On-chip test signals can be generated by dedicated circuits for built-in self-test such as the 40-MHz generator in [30], or by sinusoidal oscillators with wide-frequency tuning range such as the 1- to 25-MHz oscillator in [31]. Signal generation methods with a digital foundation are advantageous in ensuring coherence with the proposed approach. For example, the 41-MHz signal generator in [32] contains a block that creates a stepwise approximation of a sine wave using a digital master clock ( f clk ) that is M = 16 times higher than the output frequency. This synthesized sine wave is subsequently processed by an analog filter to generate a purer sinusoidal output with a 67-dB spurious-free dynamic range. Since the signal generator in [32] takes up only 0.1 mm2 in 0.35-μm CMOS technology, it would be a good candidate for applications that require the generation of coherent input signals on the chip at frequencies below 50 MHz. With such a signal generator, the master clock that produces f in (= f clk /M) in (2) can be directly derived from fsampCoh with a simple digital divider, or vice versa. Alternatively, the designer of the test might decide to use f sampCoh = f clk , which would be possible with NFFT = M = 16 and Ncycle = 1 in (2), for instance. IV. P ROPOSED A PPROACH An approach derived from the conventional coherent sampling technique is proposed in this paper for BIT applications. It follows the rules of coherent sampling, but instead of defining the near-optimal fundamental FFT frequency for a single test tone, the coherent sampling frequency is calculated based on a fixed-frequency difference between the tones in multi-tone test cases. Consequently, it circumvents spectral leakage problems associated with basic coherent sampling during multi-tone testing. Both in the single-tone and multitone test cases, the method exploits the FFT engine that can be codesigned with the requirements of a given built-in test application, which often leaves room to select test signal frequencies in a way that the required on-chip FFT resources are minimized. A. Single-Tone Testing For single-tone test cases, the coherent sampling rule is rearranged and repeated to introduce the proposed approach fsampCoh = fin · NFFT/Ncycle. (2) The new sampling frequency, called coherent sampling frequency ( f sampCoh ) here, is calculated for the desired input test tone ( f in ) with predefined values of FFT length (NFFT) and a chosen integer number of cycles of the input signal (Ncycle ). B. Multi-Tone Testing For multi-tone test cases, the FFT fundamental frequency, defined as f , can be used in lieu of f in in (2), which represents the effective resolution for suitable test tone frequencies. In a two-tone intermodulation test scenario, for example, this means that the spacing between the test tones must be equal to f or an integer multiple of f . This frequency resolution in the spectrum can be set to the desired value for a particular on-chip testing application. With this predefined value for f , the corresponding value of f sampCoh can be determined according to fsampCoh = f · NFFT/Ncycle . (3) The choice of test tones should abide by the following rules. 1) Test tone frequencies should be at least less than half of the value of f sampCoh in order to meet the Nyquist criterion. 2) Test tones should be separated by integer multiples of f . V. M ATLAB S IMULATION R ESULTS In this section, we present the simulation results to compare the conventional coherent sampling method with the proposed approach. A single-tone test case and a two-tone test case are discussed to highlight the differences.
  • 4. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 4 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Fig. 2. FFT with conventional coherent sampling (NFFT = 16). Spectrum of the input signal x(t) with a fundamental frequency component of 12.5 MHz and three harmonics. A. Case 1: Single-Tone With High-Order Harmonics Consider the following desired test input signal with a fundamental frequency of f in and three harmonic components x(t) = 105 · sin(2π · f in · t) + 103 · sin(2π · 2 f in · t) +102 · sin(2π · 3 f in · t) + 10 · sin(2π · 4 f in · t). (4) Let the above signal be sampled at a sampling rate of f samp , and analyzed using a 16-point FFT. 1) Conventional Coherent Sampling Approach: Let f in = 10 MHz, NFFT = 16, and f samp = 200 MHz. Then f = f samp /NFFT = 12.5 MHz. Using (1), we find Ncycle = fin · NFFT/ f samp = 0.8 ∼ 1. = (5) Therefore, the nearest optimal input frequency ( f inCoh ) is finCoh = Ncycle · f samp /NFFT = 12.5 MHz. (6) It should be noticed that the difference between f in and f inCoh is 2.5 MHz. In traditional testing applications (e.g., testing of an ADC block with fixed sampling rate) it is normally feasible to generate a single test tone with a fundamental frequency of f inCoh instead of f in . Fig. 2 shows the spectrum of the coherent (12.5 MHz fundamental) input signal x(t) obtained using a 16-point FFT and the conventional coherent sampling technique. It can be observed that the amplitudes at the signal’s fundamental and harmonic frequencies are accurately represented by the magnitudes of the frequency bins at the corresponding multiples of f inCoh . 2) Proposed Approach: With f in = 10 MHz, NFFT = 16, Ncycle = 1 from (5), and using (2) and (3), we get f sampCoh = f in · NFFT/Ncycle = 160 MHz f = f sampCoh · Ncycle /NFFT = 10 MHz. (7) (8) Notice that f in this case is exactly 10 MHz, which allows to calculate the spectrum precisely at the desired fundamental input frequency and its harmonics. This implies that the ADC sampling frequency and FFT rate must be selected accordingly, which exploits the design freedom in BIT and BIC scenarios with dedicated ADC and FFT engine. The spectrum of x(t), calculated with the proposed approach, is displayed in Fig. 3, showing that the amplitudes of the fundamental and harmonic Fig. 3. FFT with the proposed method (NFFT = 16). Spectrum of the input signal x(t) with a fundamental frequency component of 10 MHz and three harmonics. components are in exact agreement with those calculated using conventional coherent sampling. B. Case 2: Two-Tone Signal 1) Conventional Coherent Sampling Approach: Two-tone signals are frequently used to characterize the intermodulation components generated by second-order or third-order nonlinearities of a CUT. The frequency separation between the two test tones is typically much smaller than the frequency of each tone. Hence, it is not feasible to satisfy coherent sampling by locating the second test tone at a frequency that is a multiple of the first tone’s fundamental frequency. As demonstrated by simulation in this section, the FFT spectrum will exhibit severe inaccuracies due to leakage when the input signal is comprised of one tone that satisfies coherent sampling and another tone that does not. Consider the input signal y(t) such that y(t) = 105 · sin(2π · f 1 · t) + 105 · sin(2π · f 2 · t). (9) Signal y(t) consists of two ideal test tones at frequencies f 1 and f2 without intermodulation components. After using f 1 = 12.5 MHz [i.e., equal to the coherent input frequency ( f inCoh ) from (6)] and f 2 = 13.5 MHz in the simulation, the spectrum in Fig. 4 was calculated with NFFT = 16 and f samp = 200 MHz. From the signal contents at frequencies other than f1 and f2 , it is evident that spectral leakage occurs because f 2 does not satisfy the coherent sampling criterion. It is not practical to increase NFFT due to the corresponding die area requirement for the FFT implementation. Furthermore, in the discussed example case, such an approach would require an approximately 10 times larger f samp in order to obtain f inCoh around 1 MHz based on (6), which would allow placing the test tones at multiples of f inCoh with a separation close to 1 MHz. However, operating the on-chip ADC and FFT engine at 2 GHz would be impractical or consume too much power for many applications. 2) Proposed Approach: To avoid spectral leakage in multi-tone BIT and BIC setups, the test tone frequencies can be chosen such that they and their intermodulation products are integer multiples of f . A secondary consideration is the need to maintain a sampling rate low enough (e.g., < 200 MHz) for on-chip ADC and FFT engine implementations. The example
  • 5. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. CHAUHAN et al.: ACCURATE AND EFFICIENT ON-CHIP SPECTRAL ANALYSIS Fig. 4. Spectrum of the input signal y(t) with f 1 = 12.5 MHz (coherent) and f 2 = 13.5 MHz (not coherent). in this section demonstrates the benefit of selecting the sampling frequency based on the required frequency resolution ( f ) between tones. Consider the input signal z(t) such that z(t) = 105 · sin(2π · f 1 · t) + 105 · sin(2π · f 2 · t) +10 · sin(2π · [2 f 1 − f 2 ] · t) +10 · sin(2π · [2 f 2 − f 1 ] · t) f · NFFT/Ncycle = 16 MHz. (11) C. ADC Resolution Requirement The amplitudes of harmonic distortion (HD) and intermodulation (IM) distortion components are influenced by the number of ADC bits n. For a single-tone signal digitized by an n-bit ADC with a unit step size, the amplitude of the pth harmonic component is defined as [33] ∞ where A p = 0 if p is even, δpq = 0 if p = q, δpq = 1 if p = q, and J p is the Bessel function. Quantization of a twotone signal with frequency components f1 and f2 produces IM distortion products with the following amplitudes ( Apq ) and frequencies (Fpq ) [33]: ∞ (10) With this approach, frequency components up to f sampCoh /2 = 8 MHz can be accurately measured, while the test tones have to be selected at integer multiples of f = 1 MHz to avoid leakage. Compared to the approach with increased NFFT, this method also has the advantage that the sampling frequency is not several orders of magnitude larger than the frequencies of interest. Instead, the band of interest spans fsampCoh /2, which is 8 MHz in this example, to show an FFT realization that would be useful for the characterization of baseband circuits in wireless receivers or other low-frequency analog circuits. Fig. 5 displays the corresponding spectrum of z(t) for a case in which f 1 = 3 MHz and f 2 = 5 MHz. The result demonstrates that the two input test tones and their third-order intermodulation components are captured with high accuracy and without any spectral leakage. A p = δ p1 ·2n−1 + Fig. 5. Spectrum of input signal z(t) with two test tones, f 1 = 3 MHz and f 2 = 5 MHz, and their third-order intermodulation products at 1 and 7 MHz, calculated using a 16-point FFT. Apq = δ p1 · δq0 · 2n−2 + δ p0 · δq1 · 2n−2 which consists of test tones at f 1 and f 2 as well as their thirdorder intermodulation (IM3) products (e.g., as at the output of a CUT) during standard two-tone testing of a nonlinear analog circuit. If f = 1 MHz, then evaluation of (3) with NFFT = 16 and Ncycle = 1 yields f sampCoh = 5 2 J p 2 · m · π · 2n−1 , if p is odd m·π m=1 (12) + m=1 2 J p 2 · m · π · 2n−2 m·π ·Jq 2 · m · π · 2n−2 Fpq = p · f 1 + q · f 2 (13) (14) where p and q are integers with an odd and positive sum. From (12) and (14), it can be shown that increasing the resolution of an ideal ADC by 1 bit reduces the third-order HD (HD3) component by 9 dB and IM3 components by 12 dB. Another factor influencing the accuracy of the spectral analysis is the length of the FFT (NFFT). The digitized samples at the output of ADC contain the applied input signals with their distortion components, the generated quantization noise and distortions, as well as ADC device noises. The finite size of the FFT engine puts an additional limitation on the accuracy of the spectral measurement in the presence of distortion components. To achieve high accuracy with an FFT that is preceded by an ADC, a fine frequency resolution is desired, suggesting the use of a large number of FFT points [34]. To avoid excessive area and power consumption due to a largesized FFT engine, the selections of ADC resolution and FFT length have to be made under the given accuracy requirements and design constraints. MATLAB simulations were performed to show the impact of finite ADC resolution and FFT length on HD and IM components. The ADC was modeled with an n-bit quantizer, and the proposed approach described in Section IV was used to calculate the power spectrum of the signal. Fig. 6 shows the IM3 power in decibels relative to the carrier (i.e., IM3 power magnitude in decibels below the fundamental components from a two-tone test) as the FFT length and the ADC resolution are swept from 16 to 2048 points and from 4 to 14 bits, respectively. The IM3 power is 57 dBc when a 10-bit ADC resolution is combined with a 16-point FFT, as annotated in Fig. 6. If necessary, higher accuracy can be achieved by increasing the FFT length. As shown in Fig. 6,
  • 6. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 6 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS TABLE III S IMULATED IM3 (in dBc) W ITH DNL E RROR ( FROM A T WO -T ONE T EST W ITH f 1 = 3 MH Z , f 2 = 5 MH Z , f IM3 = 1 MH Z , AND NFFT = 24 ) DNL (LSB) 7 8 n-bits ADC 10 11 9 12 41.45 44.57 50.80 57.22 64.09 72.11 13 14 84.3 84.5 ±0.3 (μ) 49.75 53.15 59.52 65.32 66.30 75.04 102.04 86.44 ±0.3 (σ ) 1.92 22.95 1.79 ±0.5 (μ) 48.70 52.90 58.10 70.40 70.98 75.59 4.64 93.98 87.69 ±0.5 (σ ) 8.58 4.48 5.01 4.92 5.45 5.29 5.17 4.86 0.90 9.52 7.73 2.79 TABLE IV Fig. 6. IM3 versus FFT length (NFFT) and ADC resolution (n-bits) from a two-tone test with f 1 = 3 MHz and f 2 = 5 MHz. S IMULATED IM3 (in dBc) W ITH W IDEBAND N OISE ( FROM A T WO -T ONE T EST W ITH f 1 = 3 MH Z , f 2 = 5 MH Z , f IM3 = 1 MH Z , AND NFFT = 24 ) n bits 9 10 11 12 13 14 TABLE I T HEORETICAL AND S IMULATED IM3 (in dBc) FROM A T WO -T ONE T EST ENOB 8 9 10 11 12 13 15 14 W ITH f 1 = 3 MHz, f 2 = 5 MHz, AND f IM3 = 1 MHz μ 57.76 62.30 71.23 75.34 83.95 90.77 94.64 σ 4.50 3.81 6.36 4.00 5.69 5.47 6.79 8 9 10 n-bit ADC 11 12 13 14 24 TABLE V 44.57 50.80 57.22 64.09 72.11 84.3 84.5 25 47.56 55.31 62.8 72.72 85.17 92.5 86.18 26 S IMULATED IM3 (in dBc) W ITH W IDEBAND N OISE AND ±0.5-LSB DNL E RROR ( FROM A T WO -T ONE T EST W ITH f 1 = 3 MH Z , f 2 = 5 MH Z , 48.16 56.54 69.67 75.18 85.43 91.34 95.73 27 f IM3 = 1 MH Z , AND NFFT = 24 ) 52.14 65.03 77.67 90.44 96.35 90.68 104.3 215 70.88 78.68 89.12 100.60 101.32 107.1 114.4 NFFT 96.33 108.37 120.41 132.45 144.49 156.5 168.5 9 10 11 12 13 14 8 9 10 11 12 13 14 μ 60.72 63.40 75.54 75.61 81.61 89.10 96.82 σ ∞ n bits ENOB 15 5.76 4.26 7.67 4.79 5.00 6.76 5.93 TABLE II T HEORETICAL AND S IMULATED HD3 (in dBc) FROM A S INGLE -T ONE T EST W ITH f 0 = 3 MH Z NFFT n-bit ADC 11 12 8 9 10 13 14 24 56.38 64.67 72.24 78.17 83.31 86.42 92.91 215 71.67 80.71 89.26 98.92 106.99 113.49 120.4 ∞ 72.24 81.27 90.30 99.34 108.37 117.40 126.4 the simulated power of the same IM3 component is 85 dBc with 10-bit ADC resolution but with a 2048-point FFT. To give additional insights into the tradeoffs of ADC resolution and FFT length, theoretical values (ADC distortion only, NFFT = ∞) obtained from (12) and (14) were compared with simulated results using NFFT = 24 , 25 , 26 , 27 , and 215 . Tables I and II summarize the IM3 and HD3 components (in decibels relative to the carrier) for the respective twotone and single-tone test cases presented in Section V. Notice that only the test tones were applied, such that the listed IM3 and HD3 levels represent the accuracy limit of the ADC–FFT combination under the given conditions. For a 10-bit ADC, HD3 levels down to 72 dB below the fundamental can be extracted with NFFT = 24 . In contrast, the selection of NFFT = 215 would allow to identify HD3 down to 89 dB, which is close to the 90 dBc theoretical HD3 generated by the 10-bit ADC. An important metric for ADC nonlinearity is differential nonlinearity (DNL), which can be in the range of ±0.09 to ±0.5 LSB, for example [35], [36]. To assess the impact of the ADC’s static nonlinearity, simulations were performed with DNL errors of ±0.3 and ±0.5 LSB by generating random offsets of each reference voltage level with a Gaussian distribution such that the DNL value is equal to three times the standard deviation (σ ). Table III summarizes the mean (μ) and the standard deviation (σ ) of the IM3 components from 20 simulations for the two DNL cases with NFFT = 24 . Assuming a 10-bit ADC with ±0.3-LSB DNL, a mean IM3 of 65.32 dBc with 4.86-dB standard deviation is observed. This suggests that the inherent linearity of the ADC and FFT combination would allow to measure IM3 values up to 50 dBc (3 · σ lower than the mean) in 99.8% of the cases. To capture the effect of noise on the IM3 characterization capability, white noise was introduced at the ADC input in M ATLAB simulations such that the ADC’s effective number of bits (ENOB) reduces by 1 bit. The mean (μ) and the standard deviation (σ ) of the measured IM3 component from 20 simulations are listed in Table IV. The results indicate that IM3 values up to 52 dBc (= μ − 3σ ) can be extracted with 99.8% confidence using NFFT = 24 and an ADC having an ENOB of 10 bits. As shown in Table V, in presence of both DNL of ±0.5 LSB and wideband noise, IM3 values up to 52.5 dBc (= μ − 3σ ) can be accurately determined with a 16-point FFT and ENOB = 10 bit. The results suggest that the presence of DNL and noise causes distribution of power over more frequency bins, which leads to increased variation of the IM3 measurement capability but with a higher mean.
  • 7. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. CHAUHAN et al.: ACCURATE AND EFFICIENT ON-CHIP SPECTRAL ANALYSIS DNL of the ADC causes distribution of power over frequency bins due to the generation of more intermodulation products that depend on the random DNL variations across the reference voltages. Generally, nonzero DNL results in less power at the IM3 frequencies but higher power at other frequencies due to the generation of different intermodulation products. However, the power levels in all frequency bins exhibit higher variations with nonzero DNL. To investigate the effect of ADC bandwidth limitation on the IM3 characterization capability, a third-order low-pass filter (LPF) with a cutoff frequency of 3.37 MHz was placed in front of an ideal behavioral model of a 10-bit ADC to model frequency limitation during Spectre simulations in Cadence with a 16-MHz sampling frequency. The characteristics of the LPF are such that it has an ENOB of approximately 10 and 6 bits for f in ≤ 3 MHz and for f in = 7 MHz, respectively. Furthermore, the ENOB with input frequencies of 5 and 6 MHz is approximately the same (ENOB ≈ 7 bits), which is why they were selected for a two-tone test simulation. After taking a 16-point FFT of the ADC output, the IM3 components of 50.96 and 55.64 dBc were present at the frequencies of 4 and 7 MHz, respectively. This estimated test accuracy at frequencies with an ENOB ≈ 7 bits deviates by 1–7 dB from the IM3 limits for the 7-bit ADC cases with DNLs in Table III. Note that the test tones experience different attenuations and phase shifts because the ADC bandwidth limitation is modeled with a third-order LPF, which impacts the IM3 limits. Nevertheless, the result indicates that the ADC ENOB dictates the test accuracy as in the previously discussed example with wideband noise. For on-chip implementation, it is desirable to achieve small area and power with sufficient accuracy. The combination of a 10-bit ADC and 16-point FFT was chosen for the implementation example discussed in Section VI, because it provides appropriate accuracy for various BIT scenarios. Efficient ADCs can be designed with 10–80 MS/s for the anticipated applications. For example, a 10-bit ADC with 40-MS/s sampling rate implemented in 65-nm CMOS technology was reported in [37] with an active area of 0.06 mm2 and power dissipation of 1.21 mW. D. Selection of NFFT and the ADC Resolution Based on the analysis presented in Section V-C, the following procedure can be adopted to aid in selecting the appropriate ADC resolution and the FFT length. Step 1: Identify the required accuracy of the IM3 (HD3) measurement (in decibels relative to the carrier). For example, a transistor-level simulation of a CUT using test tones of a specified amplitude will result in a certain output IM3 that should be lower than the IM3 limits in the tables. Step 2: Based on Table I, select the appropriate ADC resolution and the FFT length (NFFT). If one of the two is too high for efficient on-chip implementation based on available resources, then the test tone amplitudes in step 1 can be increased to obtain lower output IM3 (in decibels relative to the carrier), relaxing the requirements for the on-chip test resources. 7 Fig. 7. bits). Radix-2 16-point FFT processor (bold lines: buses with multiple Step 3: Define the desired frequency resolution ( f ) in the output spectrum depending on the application-specific requirements and available test tone generation circuitry. Step 4: Using (2), determine the coherent sampling frequency ( f sampCoh ). Note that fsampCoh should be chosen such that the desired IM3 (or HD3) components fall within f sampCoh /2. Step 5: Choose the input test tone frequencies ( f 1 , f 2 ) as an integer multiple of the frequency resolution ( f ). VI. I MPLEMENTATION E XAMPLE A radix-2 16-point FFT engine was implemented to determine the spectral characteristics of the signal generated at the output of an ADC. The FFT engine is based on the standard decimation-in-time algorithm. It is designed as a serialized, streaming I/O FFT block that accepts streaming complex input and generates streaming complex output continuously with every clock cycle after an initial latency of 34 clock cycles, where each output corresponds to a frequency bin. The input and the output data streams are represented in 2s complement Q10.4 and Q13.4 format, respectively. The output of the 10-bit ADC represents the integer portion of the input data, where four additional fractional bits are appended to achieve a resolution of −84 dBc. The integer portion of the output data is comprised of 13 bits to capture the overflow that is generated during the FFT computation. Fig. 7 shows the block diagram of the FFT engine, where Iin, Iout and Qin, Qout represent the real and the imaginary parts of the input and the output data streams, respectively. The input data are passed to the FFT logic unit and the processed data are carried to the butterfly unit for further arithmetic operations or to the DualPort RAM unit for storage in the registers. The functions of the FFT logic unit are to reorder the output bins of the FFT engine, to calculate addresses for the butterfly unit, and to count the delay for feedback registers. Its outputs are the twiddle indexes, addresses for the DualPort RAM, calculated real and imaginary parts of data, and FFT outputs (Iout, Qout). The twiddle indexes are passed
  • 8. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 8 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS TABLE VI R ESULTS FROM A T WO -T ONE T EST: C ALCULATED FFT OF THE I NPUT S IGNAL (65 536 P OINTS ) V ERSUS O UTPUT OF THE 16-P OINT FFT E NGINE f 1 , f 2 = 3, 5 −11.37 −11.38 20 · log10 (| Magnitude |) PostActual Layout IM3 Output (dBc) (dBFS) −11.36 – – PostLayout Output IM3 (dBc) – f IM3 = 1 −61.37 −61.31 −62.08 50.00 49.93 50.72 f IM3 = 7 −61.37 −61.36 −60.04 50.00 49.98 48.68 Frequency (MHz) Actual Input (dBFS) Calculated Input (dBFS) Calculated IM3 (dBc) Fig. 9. Output spectrum from post-layout simulation, showing the two test tones ( f 1 = 3 MHz, f 2 = 5 MHz) and their IM3 products at 1 and 7 MHz Fig. 8. Layout of the FFT engine (0.73 mm2 in 45-nm CMOS technology). to the twiddle table unit, where the sine and cosine values are selected for the calculations inside the butterfly unit. The outputs of the butterfly unit and the DualPort RAM are two pairs of real and imaginary numbers that are calculated in parallel. To reduce hardware complexity, the DualPort RAM serves as feedback delay resistors, and a minimized butterfly unit is used. The FFT engine was implemented in Verilog HDL and synthesized to the gate level netlist with Cadence RTL compiler using the publicly available 45-nm PDK [38]. The generated gate level netlist was ported to the Cadence Encounter tool to complete the physical layout of the FFT engine and to evaluate the overall area and power requirements The layout is displayed in Fig. 8. It occupies a total chip area of around 0.073 mm2 with 87% density in 45-nm CMOS technology. The total estimated power dissipation for 16 MHz 16-point FFT computations at 1.1 V supply voltage is 6.47 mW. From Table I, it should be noted that an ideal two-tone input signal when quantized using a 10-bit ADC contains an IM3 component at 57.2 dBc in the output spectrum obtained with a 16-point FFT. Thus, to accurately determine the IM3 components of an input signal from a CUT, the third-order intermodulation components should be larger than the intrinsic linearity limitation of the chosen combination of the ADC resolution and the number of FFT points, such that IM3 < 57.3 dBc. As an example, a two-tone test signal represented by (10) but with a known IM3 component of 50 dBc was applied during the post-layout simulation of the 16-point FFT engine implementation together with a 10-bit ADC (Verilog model). The extracted parasitic resistances and the capacitances were included in the post-layout simulation. The output bit streams from the post-layout simulation were imported to MATLAB to plot the resulting output spectrum that is shown in Fig. 9. Table VI compares the post-layout simulation results of the implemented FFT engine, with the FFT of the input signal to the ADC obtained with the Cadence calculator using 65 536 points. The columns named Actual Input list the differences (in decibels relative to the carrier) between the input components specified for the signal sources at the frequencies of interest relative to the full-scale input range of the ADC. As a reference for comparison to the post-layout 16-point FFT results, the “Calculated Input” columns include the corresponding frequency component values obtained for the same input with an ideal 65 536-point FFT. An error of less than ±0.02 dB is observed for the fundamental components at 3 and 5 MHz, whereas the applied 50-dBc IM3 components at 1 and 7 MHz are captured with an error of 0.72 and 1.32 dB, respectively. The post-layout FFT engine simulation results indicate that the chosen combination of a 10-bit ADC and a 16-point FFT in this example is suitable to accurately determine the IM3 components of ≤ 50 dBc. VII. C ONCLUSION An accurate FFT-based analysis approach was introduced for on-chip spectral characterization of multi-tone signals. The proposed approach was derived from the coherent sampling method. It was demonstrated that it allows the designer to
  • 9. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. CHAUHAN et al.: ACCURATE AND EFFICIENT ON-CHIP SPECTRAL ANALYSIS 9 select the appropriate test signal frequencies, ADC resolution, and FFT length to achieve the desired frequency resolution in the output spectrum without spectral leakage. The method avoids the use of a large number of FFT points to minimize the required on-chip FFT resources for area- and power-efficient built-in testing applications. Post-layout simulation results of an FFT implementation in standard 45-nm CMOS technology showed the feasibility of the approach. For a 16-MHz 16-point FFT computation, the implemented FFT engine consumes an estimated power of 6.47 mW with 1.1 V supply and occupies an area of 0.073 mm2 . A methodology was presented to determine the suitable ADC resolution and the FFT length to obtain a required accuracy. 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  • 10. This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. 10 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS Hari Chauhan (S’12) received the M.S degree in computer engineering from Northeastern University, Boston, MA, USA, in 2011, where he is currently pursuing the Ph.D. degree in electrical engineering. His current research interests include digital system design, digitally assisted analog circuit design, low-power VLSI design, and RF integrated circuit design. Yongsuk Choi received the B.S degree in electrical and electronics engineering from Chung-Ang University, Seoul, South Korea, in 2011. He is currently pursuing the Ph.D. degree in electrical engineering from Northeastern University, Boston, MA, USA. His current research interests include high speed, low-power VLSI design, and analog VLSI circuit design. Marvin Onabajo (S’01–M’10) received the B.S. degree (summa cum laude) from The University of Texas at Arlington, Arlington, TX, USA, in 2003, and the M.S. and Ph.D. degrees from Texas A&M University, College Station, TX, USA, in 2007 and 2011, respectively, all in electrical engineering. He was an Electrical Test/Product Engineer with Intel Corp., Hillsboro, OR, USA, from 2004 to 2005. He was a Design Engineering Intern with the Broadband RF/Tuner Development Group, Broadcom Corp., Irvine, CA, USA, in 2011. He is an Assistant Professor with the Electrical and Computer Engineering Department, Northeastern University, Boston, MA, USA. His current research interests include analog/RF and mixed-signal IC design, built-in testing, data converters, and on-chip sensors for thermal monitoring. In-Seok Jung (S’11) received the B.S. and M.S. degrees in electronic engineering and semiconductor engineering from Chungbuk National University, Cheongju-si, South Korea, in 2007 and 2009, respectively. He is currently pursuing the Ph.D. degree in electrical engineering from Northeastern University, Boston, MA, USA. His current research interests include high speed, low-power VLSI design, analog VLSI circuit design, and power ICs. Yong-Bin Kim (S’88–M’88–SM’00) received the B.S. degree in electrical engineering from Sogang University, Seoul, Korea, the M.S. degree in electrical engineering from the New Jersey Institute of Technology, Newark, NJ, USA, and the Ph.D. degree in electrical and computer engineering from Colorado State University, Fort Collins, CO, USA, in 1982, 1989, and 1996, respectively. He was a Technical Staff Member with Electronics and Telecommunications Research Institute, Daejeon, Korea, from 1982 to 1987. He was a Senior Design Engineer with Intel Corp., Hillsboro, OR, USA, from 1990 to 1993, involved in microcontroller chip design and Intel Pentium Pro microprocessor chip design. He was a Technical Staff Member with Hewlett Packard Company, Fort Collins, from 1993 to 1996, involved in HP PA8000 RISC microprocessor chip design. He was a Staff Engineer with Sun Microsystems, Palo Alto, CA, USA, from 1996 to 1998, involved in 1.5 GHz Ultra Sparc5 CPU chip design. He was an Assistant Professor with the Department of Electrical Engineering, University of Utah, Salt Lake City, UT, USA, from 1998 to 2000. He is currently an Associate Professor with the Department of Electrical and Computer Engineering, Northeastern University, Boston, MA, USA. His current research interests include low-power analog and digital circuit design as well as high-speed low-power very large-scale integrated circuit design and methodology.