2. CAO et al.: NOVEL 1T-1D DRAM CELL FOR EMBEDDED APPLICATION 1305Fig. 1. (a) Equivalent circuit, (b) cross-sectional view, (c) doping proﬁle, and (d) plan-view layout of the planar channel 1T-1D DRAM.Fig. 2. (a) Current contour during the WRITE-0 operation. (b) Current contour during the WRITE-1 operation (inset: the current path of the PTFET is very closeto the Si surface). (c) FG potential along the cutline through CG/FG/substrate at the standby (blue line) “0” and (red line) “1” states. (d) I–V curves comparisonthat shows the threshold-voltage shift of the FG MOSFET.this paper, we focus on the device simulation by using thetechnology computer-aided design (TCAD) simulation tools.Its WRITE, READ, retention, and disturb performances will bediscussed.This 1T-1D DRAM has the usual DRAM operations ofWRITE, READ, and standby. The WRITE-0 operation is per-formed by applying a positive voltage on the CG electrode anda zero voltage on the drain electrode. As shown in Fig. 2(a), thediode in the embedded TFET is forward biased, and holes aredriven out of the FG. The contour of current ﬂow during theWRITE-0 operation is also shown in Fig. 2(a). This operationresults in a lowered potential in the FG and an increased thresh-old voltage of the FG NMOS. During the WRITE-1 operation,the CG is set to a negative voltage, and the drain is set toa positive voltage [see Fig. 2(b)]. The p-n junction of theTFET is reverse biased, and it works as a p-type TFET. Underthis operation, holes are pushed into the FG, and electronsare driven out. As a result, the potential in the FG is raised,and the threshold voltage of the NMOS is lowered. The FGpotential of standby “0” and standby “1” states are compared inFig. 2(c), where a potential window between state-0 and state-1can be observed in the FG. During the READ operation, bothCG and drain electrode are connected to positive voltages. Theinformation stored in this memory cell can be recognized bysensing the read-out drain current density. The I–V curves ofthe FG MOSFET showing the threshold-voltage shift is shownin Fig. 2(d).A. Modeling of the Memory Access Transistor of1T-1D DRAM: TFETIn the proposed 1T-1D memory cell, the TFET (or enhancedgated diode) is the access device of the FG capacitor. In orderto verify the operation speed of the 1T-1D DRAM cell, wesimulate the p-type TFET device in this memory cell. The sim-ulation tool is Silvaco TCAD Atlas device simulator, version5.14.0.R. In addition to the regular MOSFET simulation modelssuch as FLDMOB, CONMOB, IMPACT, AUGER, and SRHmodels, the BBT.Kane model is used to calculate the band-to-band current. Equation (1) is the expression of the Kane localband-to-band tunneling model, i.e.,GBBT =A.BTBTEgFBBT.GAMMAexp −B.BTBTE32gF.(1)In (1), GBBT is the band-to-band tunneling generation rate,A.BTBT and B.BTBT are constants. F is the magnitude ofthe electric ﬁeld. The speciﬁed parameters are listed in the fol-lowing: A.BTBT is 3.5 × 1021(eV1/2/cm · s · V2); B.BTBT is2.25 × 107(V/cm · eV3/2); and BBT.GAMMA is 2.5.
3. 1306 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 5, MAY 2012Fig. 3. (a) Simulated transfer characteristics of the TFET embedded in the 1T-1D DRAM. (b) Simulated and measured transfer characteristics of a planar TFETwith 6nm gate oxide.Fig. 4. (a) Capacitors in 1T-1D DRAM cell for calculation with charge balance model. Experimental device cross section is shown in Fig. 8. (b) Impact of Vcgon the FG potential. Vfg is increased by 0.5 V with a 0.9-V increase in Vcg. (c) Electric potential for the 1T-1D DRAM cell with (red line) READ-1 and (blue line)READ-0 states at Vcg = 0.7 V.The temperature of this simulation is set to 300 K, andthe gate leakage current is ignored. The simulated transfercharacteristics of the embedded TFET are shown in Fig. 3(a). Itcan be seen that the drive current in the WRITE-1 mode at Vd =2.0 V and Vcg = −2.0 V is 1 µA/µm due to the enhanced band-to-band tunneling rate. For comparison, the measured transfercharacteristics of a planar p-type TFET with a gate oxide thick-ness of 6 nm are shown in Fig. 3(b), where the drive current atVd = 2.0 V and Vcg = −2.0 V is close to 3 µA/µm. Althoughthe drive current of a few microamperes per micrometer is muchlower than that of the MOSFET, it is able to charge a capacitorof 0.1 fF within 1 ns. More importantly, the TFET has shownan ultralow leakage value of about 1 × 10−14A/µm , ;a much smaller capacitor can be used for charge storage inthe 1T-1D DRAM. With a TFET having low Ion and Ioﬀ anda tiny storage capacitor, the 1T-1D DRAM is not limited bythe drive current and storage capacitance requirements of theconventional standalone DRAM.B. Capacitive Coupling in the 1T-1D DRAM CellIn order to understand the fundamental working mechanismof this device, the capacitive coupling is analyzed. Fig. 4(a)illustrates the capacitors in a 1T-1D DRAM memory cell.According to the charge balance model , the relation be-tween charge and FG voltage Vfg can be expressed asQfg = Cfg(Vfg − Vcg) + Cs(Vfg − Vs)+ Cd(Vfg − Vd) + Cbb(Vfg − Vbb) (2-1)where Cfg, Cs, Cd, and Cbb represent the CG-to-FG overlapcapacitance, source-to-FG overlap capacitance, drain-to-FG ca-pacitance, and FG-to-bulk capacitance, respectively. Vfg, Vcg,Vs, Vd, and Vbb represent the FG voltage, the CG voltage, the
4. CAO et al.: NOVEL 1T-1D DRAM CELL FOR EMBEDDED APPLICATION 1307Fig. 5. (a) Vd and Vcg along the transient simulation time. (b) Corresponding drain current in the transient simulation.source voltage, the drain voltage, and the substrate voltage,respectively. From (2-1), we can deduce the following:Vfg = (Qfg + Cfg · Vcg + Cs · Vs + Cd · Vd + Cbb · Vbb)/(Cfg + Cs + Cd + Cbb)= Qfg/(Cfg + Cs + Cd + Cbb) + Vcg · rcg + Vs · rs+ Vd · rd + Vbb · rbb (2-2)where r represents the capacitive coupling ratio of each elec-trode. For examplercg = Cfg/(Cfg + Cs + Cd + Cbb). (2-3)Since the ﬂoating junction gate and drain electrode conﬁgurea p-n diode, Cd is a diode capacitor that is modulated by thevoltage bias (Vfg − Vd). Cd will decrease with the increasingreverse-bias voltage of the p-n diode.According to (2-2), the coupling ratio of CG can be approxi-mately calculated by (2-4) when Vd, Vs, and Vbb are ﬁxed, i.e.,rcg =dVfgdVcg. (2-4)The potential along the cutline through the CG, the FG, andthe channel is plotted in Fig. 4(b). When Vcg is increased from−0.2 to 0.7 V, Vfg is increased by 0.5 V. Therefore, the couplingratio of CG is around 0.56.With the increasing Vcg, Vfg can be close to or higher thanVth of the FG NMOS. The MOS channel of the 1T-1D DRAMcell can be strongly inversed when Vfg > Vth. As a result, a highcurrent can be obtained. In Fig. 4(c), the potential of the FG iscompared for the READ state “1” and state “0.” The “0” cell hasVfg of 0.24 V, and the “1” cell has Vfg of 1.0 V with the sameVcg. Because p+doped poly-silicon is used as gate-poly forNMOS, Vth of this NMOS is around 1.2 V. Therefore, the cellwith Vfg of 0.24 V has a very low drain current at Vcg = 0.7 Vand Vd = 1.2 V.TABLE IBIAS CONDITIONS FOR WRITE-0, WRITE-1, READ,AND HOLD OPERATIONSIII. TRANSIENT SIMULATION RESULTS AND DISCUSSIONSA. READ and WRITE Operation SimulationThe transient simulation results of the bulk-Si based 1T-1DDRAM and the operation conditions are shown in Fig. 5 andTable I, respectively. The feature size F of the simulated deviceis 90 nm. The length of the CG is 360 nm (4F). The lengthof the FG is 290 nm (3F + 20 nm), including a misalignmentbudget of 20 nm. The thickness of the gate oxide [Tox1; seeFig. 1(b)] of the n-type MOSFET is 4 nm, whereas that of thegated diode (Tox2) is 5 nm. The interpoly-dioxide thicknessis 5 nm. The doping concentrations for n+CG, p+FG, n−lightly doped drain (LDD), n+source, and n++drain are 1.5 ×1019, 3 × 1018, 1.5 × 1018, 2.5 × 1020and 2.5 × 1020cm−3,respectively. The ion-implantation dose of n−LDD and p−region of the gated diode is 2 × 1013cm−2. The implantationenergy are 85 and 3 keV, respectively. The simulations are doneby Athena (process simulation) and Atlas (device simulation)softwares from Silvaco Corporation. To calculate the band-to-band effect, the Kane band-to-band tunneling model is used.According to the transient simulation results, WRITE-0 andWRITE-1 operations take 1 ns, including the 0.2-ns rising/falling edge of the signal pulse. The WRITE-0 and WRITE-1current is around 1 µA/µm. It can be seen that the READ-0current is as low as 1 pA/µm due to the low FG potential.The READ-1 current is as high as 20 µA/µm because ofthe increased FG potential. The sense current ratio of state-1and state-0 is about 107. The hold “0” current is about 1 fA/µm,
5. 1308 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 5, MAY 2012Fig. 6. Disturb of the 1T-1D DRAM cell simulated with the temperatureof 300 K.Fig. 7. Simulated retention curves of the 1T-1D DRAM cell at 300and 360 K.whereas the hold “1” current is around 10 pA/µm. The rel-atively large hold “1” current results from relatively higherpotential in the FG at standby “1” state.B. Disturb Stress and Retention PerformanceVarious bitline (BL) disturbs and wordline (WL) disturbs aresimulated, and the results are shown in Fig. 6. It can be seenthat the FG potential window between different states after a1000-ns disturb operation is 0.4 V. From the simulation results,it is found that the most serious disturb operations are theWRITE-0 WL disturb on the “1” cells and the WRITE-1 opera-tion WL disturb on the “0” cells. These two disturb mechanismslimit the disturb performance of the 1T-1D DRAM. When apositive voltage is applied to the CG during the WRITE “0”operation, holes stored in the FG of “1” cells will be drivenout due to the forward p-n junction diode leakage current. TheWRITE-0 operation degrades Vfg of “1” cells for over 0.7 V witha 1000-ns disturb time.During the WRITE “1” BL disturb, the reverse-biasing volt-age of the p-n junction in the TFET is increased. Consequently,the leakage current through the TFET is increased. As shown inFig. 8. (a) Array design of 1T-1D DRAM cells with shared BL contacts.(b) The processes’ memory array with 13.2-F2 unit cell size. Cross section(c) parallel and (d) perpendicular to the WL.Fig. 3, the TFET leakage current increases with the increasingVd for both simulated and experimental TFETs. The WRITE “1”BL disturb results in an increase in the FG potential. As shownin Fig. 6, the FG potential of the “0” cell increases by 0.2 Vafter the 1-µs disturb operation. A similar impact of the WRITE“1” BL disturb on the “1” cells is also observed in Fig. 6.The simulated retention curves for the “0” and “1” cells areshown in Fig. 7. It is shown that the potential window of the FG
6. CAO et al.: NOVEL 1T-1D DRAM CELL FOR EMBEDDED APPLICATION 1309between states “0” and “1” is still wide after the 1-s retentionsimulation at room temperature. This good performance is dueto the low leakage current of the reverse-biased p-n structure.Similar to the conventional 1T-1C DRAM, high temperaturedegrades the signal window much faster. The 360-K retentioncurves indicate that the potential window between states “0”and “1” is halved after the 100-ms retention simulation.C. Investigation of the Integration CompatibilitySeveral different process ﬂows have been investigated. Ourpaper shows that this 1T-1D DRAM cell is compatible withthe self-aligned FG and shallow trench isolation (STI) processﬂow for fabricating the high-density NAND Flash memory.Meanwhile, it is compatible with the split-gate Flash memoryand EEPROM devices. That means that it can be integratedwith the high-density Flash as the high-density data buffer forthe solid-state disk application or integrated as the embeddedDRAM for system-on-chip applications.The process compatibility with dual-poly processes has beenstructurally studied before adjusting the ion-implantation steps.As shown in Fig. 8, a memory array conﬁgured by rows of1T-1D DRAM cells are designed and integrated. In Fig. 8(a),two neighboring cells share one bit contact and one source line.The source active-area lines are connected to a common sourcemetal line. In Fig. 8(b), a microscope image of the array isshown. As shown in Fig. 8(c), the STI taper changes at the arrayedge along the parallel-WL direction. Two dummy BLs and twoactive-area lines are added in order to improve the uniform inthe array. In Fig. 8(d), the device structure with the same celldesign to Fig. 1(b) is shown (this cross section is close to theSTI edge). With the shared BL contact design, the unit cell sizeis 13.2 F2. It is slightly larger than the embedded stack capacitor1T-1C DRAM, but the structure becomes compatible with mostof the dual-poly processes.IV. CONCLUSIONThe performance of a novel 1T-1D DRAM cell based ondual-poly processes has been proposed and studied through2-D process and device simulations. Fast WRITE speed (1 ns)and low operation voltages can be achieved by introducing aTFET into this memory cell. By process and structure optimiza-tion, a large READ current window has been realized. Asidefrom that, the process of the 1T-1D DRAM is compatible withthat of the dual-poly Flash memory cell. The introduction of1T-1D DRAM cell will enable the integration of high-speedhigh-density DRAM for embedded application. A 3-D 1T-1Dmemory device will be investigated for further scaling down(e.g., 22 nm).REFERENCES W. Mueller, G. Aichmayr, W. Bergner, E. Erben, T. Hecht, C. Kapteyn,A. Kersch, S. Kudelka, F. Lau, J. Luetzen, A. Orth, J. Nuetzel,T. Schloesser, A. Scholz, U. Schroeder, A. Sieck, A. Spitzer, M. Strasser,P.-F. Wang, S. Wege, and R. Weis, “Challenges for the DRAM cell scalingto 40 nm,” in IEDM Tech. Dig., 2005, pp. 339–342. S.-W. Chung, S.-D. Lee, S.-A. Jang, M.-S. Yoo, K.-O. Kim, S. Chung,Y. Cho, H.-J. Cho, L.-H. Lee, S.-H. Hwang, J.-S. Kim, B.-H. Lee,G. Yoon, H.-S. Park, S.-J. Baek, Y.-S. Cho, N.-J. Kwak, H.-C. Sohn,S.-C. Moon, K.-D. Yoo, J.-G. Jeong, J.-W. Kim, and S.-J. Hong, “Highlyscalable saddle-Fin(S-Fin) transistor for sub-50nm DRAM technology,”in Proc. Symp. VLSI Technol. Tech. Dig., 2006, pp. 32–33. I. Ban, U. E. Avci, D. L. Kencke, and P. L. D. Chang, “A scaled ﬂoatingbody cell (FBC) memory with high-k + metal gate on thin-silicon andthin-BOX for 16-nm technology node and beyond,” in Proc. Symp. VLSITechnol. Tech. Dig., 2008, pp. 92–93. S. Okhonin, M. Nagoga, J. M. Sallese, and P. Fazan, “A SOI capacitor-less1T DRAM concept,” in Proc. IEEE Int. SOI Conf., 2001, pp. 153–154. T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao, andK. Sunouchi, “Memory design using a one-transistor gain cell on SOI,” inProc. ISSCC Tech. Dig., 2002, pp. 152–455. Z. Lu, J. G. Fossum, J.-W. Yang, H. R. Harris, V. P. Trivedi, M. Chu, andS. E. Thompson, “Simpliﬁed superior ﬂoating-body/gate DRAM cell,”IEEE Electron Device Lett., vol. 30, no. 3, pp. 282–284, Mar. 2009. H.-J. Cho and M.-R. Lin, “Novel DRAM cell with ampliﬁed capacitor forembedded application,” in IEDM Tech. Dig., 2009, pp. 1–4. C. Anghel, Hraziia, A. Gupta, A. Amara, and A. Vladimirescu, “30-nmtunnel FET with improved performance and reduced ambipolar current,”IEEE Trans. Electron Devices, vol. 58, no. 6, pp. 1649–1654, Jun. 2011. P.-F. Wang, K. Hilsenbeck, T. Nirschl, M. Oswald, C. Stepper, M. Weis,D. Schmitt-Landsiedel, and W. Hansch, “Complementary tunneling tran-sistor for low power application,” Solid State Electron., vol. 48, no. 12,pp. 2281–2286, Dec. 2004. T. Mori, T. Yasuda, and T. Maeda, “Tunnel ﬁeld-effect transistors withextremely low off-current using shadowing effect in drain implantation,”Jpn. J. Appl. Phys., vol. 50, no. 6, pp. 06GF14-1–06GF14-3, Jun. 2011. K. K. Bhuwalka, S. Sedlmaier, A. K. Ludsteck, C. Tolksdorf, J. Schulze,and I. Eisele, “Vertical tunnel ﬁeld-effect transistor,” IEEE Trans. ElectronDevices, vol. 51, no. 2, pp. 279–282, Feb. 2004. P.-F. Wang and Y. Gong, “A novel 4.5 F2 capacitorless semiconductormemory device,” IEEE Electron Device Lett., vol. 29, no. 12, pp. 1347–1348, Dec. 2008. M. H. Manley, M. Hart, and P. J. Cacharelis, “Method of making anon-volatile memory cell utilizing polycrystalline silicon spacer tunnelregion,” U.S. Patent 5 108 939, Oct. 16, 1990. P. Pavan, L. Larcher, and A. Marmiroli, Floating Gate Devices: Operationand Compact Modeling. Norwell, MA: Kluwer, 2004.Cheng-Wei Cao received the B.S. degree in mi-croelectronics and solid-state electronics in 2010from Fudan University, Shanghai, China, where heis currently working toward the M.S. degree in theDepartment of Microelectronics.His main research interests are novel memorydevices, device modeling, and simulation.Song-Gan Zang received the B.E. degree in theoret-ical physics and the M.S. degree in microelectronicsfrom Fudan University, Shanghai, China, in 2007 and2011, respectively.He is currently a 28-nm Graphics Design Engi-neer with the Advanced Micro Devices ShanghaiResearch and Development Center, Shanghai. Hisresearch interests include low-power circuit, memoryand device design, and fabrication for the cutting-edge integrated-circuit technology.Xi Lin was born in Wenzhou, China, in 1988. Hereceived the B.S. degree in 2010 from Fudan Univer-sity, Shanghai, China, where he is currently workingtoward the Ph.D. degree in the Department of Micro-electronics.He is dedicated in the research and fabrication ofnovel semiconductor devices and technologies basedon technology computer-aided design simulation.
7. 1310 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 5, MAY 2012Qing-Qing Sun received the B.S degree in physicsand the M.S. degree in microelectronics and solid-state electronics from Fudan University, Shanghai,China, in 2004 and 2009, respectively.He is currently an Associate Professor with theSchool of Microelectronics, Fudan University. Hisresearch interests include fabrication and charac-terization of advanced metal–oxide–semiconductorﬁeld-effect transistors, mainly high-k dielectric-based devices. He is also interested in design,fabrication, and characterization-advanced memorydevices, such as resistive switching memory devices and Flash.Charles Xing received the B.E. degree in appliedmechanics and the M.S. degree in material sciencefrom Fudan University, Shanghai, China, where heis currently working toward the Ph.D. degree inmicroelectronics and solid-state electronics.He has 20 years of information-technology andintegrated-circuit industry experience with a back-ground in research and development, technology,fabrication, and management. Since 2003, he hasbeen with the Semiconductor Manufacturing Inter-national Corporation, Shanghai, where he startedthe new materials research and application for nanoscale semiconductor. Hisresearch ﬁelds covered both front-end-of-line and back-end-of-line processingtechnologies, mainly focusing on thin-ﬁlm process, Cu interconnections, andLow-K materials, etc.Peng-Fei Wang received the B.S. and M.S. de-grees from Fudan University, Shanghai, China, in1998 and 2001, respectively, and the Ph.D. degreefrom the Technical University of Munich, München,Germany, in 2003.Until 2004, he was with the Memory Divisionof the Inﬁneon Technologies in Germany on thedevelopment and the process integration of novelmemory devices. Since 2009, he has been a Professorwith Fudan University. His research interests includedesign and fabrication of semiconductor devices anddevelopment of semiconductor fabrication technologies such as high-k gatedielectrics and copper/low-k integration.David Wei Zhang received the B.S., M.S., and Ph.D.degrees in electrical engineering from Xi’an JiaotongUniversity, Xi’an, China, in 1988, 1991 and 1995,respectively.In 1997, he was an Associate Professor withFudan University, Shanghai, China, where he hasbeen a Full professor since 1999 and is currentlythe Chairman of the Department of Microelectronicsand the Director of the Fudan–Novellus InterconnectResearch Center. He has authored more than 200referred archival publications and is the holder of15 patents. More than 50 students have received their M.S. or Ph.D. de-grees under his supervision. His research interests include integrated-circuitprocessing and technology, such as copper interconnect technology, atomiclayer deposition of high-k materials; semiconductor materials and thin-ﬁlmtechnology; new structure dynamic random access memory (RAM), Flashmemory, and resistive RAM; and metal–oxide–semiconductor FET based onnanowire and nanotube, and tunneling FET.