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design and implementation of low power fft ifft processor for wireless communication

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  • 1. Proceedings of the International Conference onPattern Recognition, Informatics and Medical Engineering , March 21-23, 2012978-1-4673-1039-0/12/$31.00 ©2012 IEEEDesign And Implementation of Low Power Fft/IfftProcessor For Wireless CommunicationA.Anbarasan K.ShankarP.G Scholar Assistant ProfessorArunai College of Engineering Arunai College of EngineeringThiruvannamalai Thiruvannamalaianbarasan.a2011@gmail.com shan.maddy87@gmail.comAbstract - Fast Fourier transform (FFT) processing is one of thekey procedure in popular orthogonal frequency division multiplexing(OFDM) communication systems. Structured pipeline architectures,low power consumption, high speed and reduced chip area are themain concerns in this VLSI implementation. In this paper, theefficient implementation of FFT/IFFT processor for OFDMapplications is presented. The processor can be used in variousOFDM-based communication systems, such as WorldwideInteroperability for Microwave access (Wi-Max), digital audiobroadcasting (DAB), digital video broadcasting-terrestrial (DVB-T).We adopt single-path delay feedback architecture. To eliminate theread only memories (ROMs) used to store the twiddle factors, thisproposed architecture applies a reconfigurable complex multiplier toachieve a ROM-less FFT/IFFT processor and to reduce thetruncation error we adopt the fixed width modified booth multiplier.The three processing elements (PE’s), delay-line (DL) buffers areused for computing IFFT. Thus we consume the low power, lowerhardware cost, high efficiency and reduced chip size.Keywords:FFT, IFFT, OFDM, Modified Booth Multiplier.I. INTRODUCTIONThe Fast Fourier Transform (FFT) and its Inverse FastFourier Transform (IFFT) are essential in the field of digitalsignal processing (DSP), widely used in communicationsystems, especially in orthogonal frequency divisionmultiplexing(OFDM) systems, wireless-LAN, ADSL, VDSLsystems and Wi-MAX. Apart from the applications, the systemdemands high speed of operation, low power consumption,reduced truncation error and reduced chip size. By consideringthese facts, we proposed the ROM-less processor with singlepath delay feedback (SDF) pipeline architecture and modifiedbooth width multiplier. The SDF pipelined architecture is usedfor the high-throughput in FFT processor. There are three typesof pipeline structures; they are single-path delay feedback(SDF), single-path delay commutator (SDC) and multi-pathdelay commutator. The advantages of single-path delay feedback(SDF) are (1) This SDF architecture is very simple to implementthe different length FFT. (2) The required registers in SDFarchitecture is less than MDC and SDC architectures. (3) Thecontrol unit of SDF architecture is easier.We implement the processor in SDF architecture withradix-4 algorithm. There are various algorithms to implementFFT, such as radix-2, radix-4 and split-radix with arbitrary sizes[3]-[5]. Radix-2 algorithm is the simplest one, but its calculationof addition and multiplication is more than radix-4s. Thoughbeing more efficient than radix-2, radix-4 only can process 4n-point FFT. The radix-4 FFT equation essentially combines twostages of a radix-2 FFT into one, so that half as many stages arerequired. Since the radix-4 FFT requires fewer stages andbutterflies than the radix 2 FFT, the computations of FFT can befurther improved.In order to speed up the FFT computation we increasethe radix, for reducing the chip size we use ROM-lessarchitecture and for further low power consumption weimplement the reconfigurable complex multiplier and delay linebuffers[8]-[10], error compensation is carried out using fixedwidth modified booth multiplier. Several error compensationmethods have been proposed [17]-[18] here, the fixed widthmodified booth multipliers achieve better error performance interms of absolute error and mean square error. Using radix-4algorithm, we propose a 64-point FFT/IFFT processor withROM less architecture. Finally, this paper is organized asfollows. Section II describes the FFT/IFFT processor with radix-4 algorithm. Proposed architecture is discussed in Section III.The performance evaluation and results is then discussed inSection IV. Finally conclusion and future work will see inSectionV.II. FFT/IFFT ALGORITMHIn last three decades, various FFT architectures such assingle-memory architecture, dual memory architecture, pipelinedarchitecture, array architecture and cache memory architecture
  • 2. International Conference on Pattern Recognition, Informatics and Medical Engineering (PRIME-2012)153have been proposed. In order to improve the power reduction,we propose a radix-4 64-point pipeline FFT/IFFT processor. Inorder to speed up the FFT computations, more advancedsolutions have been proposed using an increase of the radix. Theradix-4 FFT algorithm is most popular and has the potential tosatisfy the current need. The radix-4 FFT equation essentiallycombines two stages of a radix-2 FFT into one, so that half asmany stages are required. To calculate 16-point FFT, the radix-2takes log216=4 stages but the radix-4 takes only log416=2stages.A 16-point, radix-4 decimation-in-frequency FFT algorithm isshown in Figure 1. Its input is in normal order and its output is indigit-reversed order. It has exactly the same computationalcomplexity as the decimation-in-time radix-4 FFT algorithm.Fig.1: Flow graph of a 16-point radix-4 FFT algorithm.When the number of data points N in the DFT is apower of 4, then is more efficient computationally to employ aradix-4 algorithm instead of radix-2 algorithm. A radix-4decimation in-time FFT algorithm is obtained by splitting the N-point input sequence x(n)into four sub sequences x(4n), x(4n +1), x(4n + 2) and x(4n + 3). The radix-4 decimation in frequencybutterfly is constructed by merging 4-point DFT with associatedcoefficients between DFT stages. The four outputs of the radix-4butterfly namely X(4n), X(4n+1), X(4N+2) and X(4N+3) areexpressed in terms of its inputs x(n), x(n)+N/4 , x(n)+N/2 andx(n)+3N/4.III. PROPOSED ARCHITECTUREIn this paper, low power techniques are employed forpower consumption using reconfigurable complex multiplier.Using radix-4 algorithm, increase the computational speed,further reduce the chip area by three different processingelements (PE’s) were proposed in this radix-4 64-pointFFT/IFFT processor. Our proposed architecture uses a lowcomplexity reconfigurable complex multiplier instead of ROMtables to generate twiddle factors and fixed width modifiedbooth multiplier to reduce the truncation error.Fig.2: Proposed radix-4 64-point pipeline FFT/IFFT processorThis proposed architecture consists of three differenttypes of processing elements (PEs), reconfigurable constantcomplex multiplier, delay line buffers (as shown by a rectanglewith a number inside) and some extra processing units for IFFT.Here, the conjugate operation is easy to implement, where wehave to generate the 2’s complement of the imaginary part of acomplex value. This new multiplication structure becomes thekey component in reducing the chip area and powerconsumption. Based on the radix-4 FFT algorithm, the threetypes of processing elements (PE3, PE2, PE1) proposed in ourdesign. Illustrated in fig.3, fig.4, and fig.5 respectively.Fig.3 Circuit diagram of our proposed PE3 stage.Fig.4 Circuit diagram of our proposed PE2 stage.
  • 3. International Conference on Pattern Recognition, Informatics and Medical Engineering (PRIME-2012)154Fig.5 Circuit diagram of our proposed PE1 stage.The PE3 stage is used to implement the radix-4butterfly structure, and serves as sub-modules of the PE2andPE1 stages. In the PE2 stage, the calculation of multiplication by–j or 1 uses the outcome of the PE3 module. Note that amultiplication by -1 is practically to take the 2’s complement ofthe input value. The PE1 stage is responsible for computing themultiplications by –j, WNN/8, and WN3N/8, respectively. SinceWN3N/8= -jWN3N/8, it can be done with a multiplication by, WNN/8first and then a multiplication by –j. Hence, our designedhardware utilizes this kind of cascaded calculation andmultiplexers to realize all the calculations in the PE1 stage.The realization of multiplication by, WNN/8using radix-4 butterfly structure with its both outputs commonly multipliedby 1/√2, is shown in fig.6Fig.6 Circuit diagram of the multiplication by WNN/8Here the multiplication operation of modified boothmultipliers, the multiplication operation of A=an-1an-2....a0(multiplicand) and B= bn-1bn-2....b0 (multiplier) can be expressedas follows:The modified booth encoder and partial productgeneration circuit shown in fig.7Fig. 7(a) modified booth encoder. (b) Partial product generationcircuit.Here the partial product matrix of booth multiplicationwas slightly modified and effective error compensation wasderived [16]. The output quality in terms of peak signal to noiseratio (PSNR) for different fixed-width booth multipliers are usedin different applications.V. CONCLUSIONA low power pipelined 64-point FFT/IFFT processorfor OFDM applications has been described in this paper. Ourdesigned hardware requires about 33.6k gates, and has a workingfrequency up to 80 MHz synthesized by using 0.18µm CMOStechnology. Since our design requires low-cost and consumeslow power, as well as reduced SQNR and highly efficient.Hence it can be applied as a powerful FFT/IFFT processor inwireless communication systems. In futureREFERENCES[1]. Chu yu, Mao-Hsu Yen “ A Low power 64-pointFFT/IFFT Processor for OFDM Applications” IEEETransactions on Consumer Electronics,Vol. 57, Feb2011[2]. N.Kirubanandasarathy, Dr.K.Karthikeyan,” VLSIDesign of Mixed Radix FFT Processor for MIMI-OFDM in Wireless Communication”, 2011 IEEEProceedings.[3]. Fahad Qureshi and Oscar Gustafson,”Twiddle FactorMemory Switching Activity Analysis of Radix-22 andEquivalent FFT Algorithms”, IEEE Proceedings, April2010.[4]. Jianing Su, Zhenghao Lu, “Low cost VLSI design of aflexible FFT processor”, IEEE Proceedings, April2010.[5]. He Jing, Ma Lanjaun, Xu Xinyu, “A Configurable FFTProcessor”, IEEE proceeding 2010.[6]. M.Merlyn, “FPGA Implementation of FFT Processorwith OFDM Transceiver”, 2010 IEEE proceeding.[7]. “A Radix based Parallel pipelined FFT processor forMB- OFDM UWB system, “Nuo Li and N.P.van derMeijs, IEEE Proceedings, 2009.
  • 4. International Conference on Pattern Recognition, Informatics and Medical Engineering (PRIME-2012)155[8]. Minhyrok Shin and Hanho Lee, “ A High-Speed FourParallel Radix-24 FFT/IFFT Processor for UWBApplications,” in Proc. IEEE Int. Symp. Circuits andsystems, 2008, pp. 960-963.[9]. “A Radix based Parallel pipelined FFT processor forMB-OFDM UWB system, “Nuo Li and N.P.van derMeijs, IEEE Proceedings, 2009.[10]. Wei Han, Ahmet T. Erdogan, Tughrul Arslan, andMohd. Hasan, “High-Performance Low-Power FFTCores,” ETRI Journal, Volume 30, Number 3, June2008.[11]. “ A Mathematical Approach to a Low Power FFTArchitecture,” K. Stevens and B. Suter, IEEE Int’lSymp. on Circuits and Systems, 2008.[12]. “A 64-Point Fourier Transform Chip for High-SpeedWireless LAN Application Using OFDM,” K.Maharatna, E. Grass, and U. Jagdhold, IEEE Journal ofSolid-State Circuit, 2008.[13]. “Low Power Commutator for Pipelined FFTProcessors,” W. Han, A.T. Erdogan, T.Arslan, and M.Hasan, IEEE Int’l Symp. On Circuit and Systems(ISCAS), vol. 5, Kobe, Japan, May 2008, pp. 5274-5277.[14]. Yuan Chen, Yu-Wie Lin and Chen-Yi Lee ”A BlockScaling FFT/IFFT Processor for WiMAXApplications,” in proc. IEEE Asian solid-state circuitsconf., 2006, pp.203-206 [15] Y.T.Lin, P.Y. Tsai andT.D.Chiueh, “Low-power variable-length Fast Fouriertransform Processor,” IEEE. Proc. Comput. Digit.Tech., Vol. 152, no. 4 pp.449-506, july 2005[15]. “High-Accuracy Fixed-Width Modified BoothMultipliers for Lossy Applications”, Jiun-Ping Wang,Shiann-Rong Kuang, IEEE Transactions on Very LargeScale Integration (VLSI) systems ,Vol. 19 No.1, Jan2011.[16]. K.J Cho, K.C .Lee, J.G.Chung, and K.K.Parhi,”Designof low error fixed width modified booth multiplier,”IEEE Trans. Very large scale Integr. (VLSI) syst.,vol.12,no.5,pp.522-531, May 2004[17]. M.A.Song, L.D.Van,and S.Y.Kuo “Adaptive low –errorfixed width booth multiplier,”IEICETrans.Fundamentals,vol.E90-A, no.6 pp.1180-1187,Jun.2007

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