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Current Mode Techniques for Multiple Valued Arithmetic and Logic
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Current Mode Techniques for Multiple Valued Arithmetic and Logic

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Current Mode Techniques for Multiple Valued Arithmetic and Logic Current Mode Techniques for Multiple Valued Arithmetic and Logic Document Transcript

  • 279 Current Mode Techniques for Multiple Valued Arithmetic and Logic tC.T. Clarke ,and G. R. Nudd Department of Computer Science, University of Warwick, Coventry, CV4 7AL, U.K. ctc@dcs.warwick.ac .uk grn@dcs.warwick.ac.uk (+44) 203-523523 ABSTRACT This paper analyses the general properties of Current Mode Multiple Valued Logic (CMMVL) circuits, and presents a framework for further exploitation. A unified circuit view is proposed in which circuits are described in terms of CMMVL to voltage mode binary decoders, and binary to CMMVL encoders. The relative merits of various encodings are explored for a single digit multiplier. It is shown that CMMVL has an inherent advantage in the VLSI layout of fan-in dominated subsystems such as Wallace trees. The construction of CMMVL circuit cells for general logic is discussed. INTRODUCTION Multiple Valued Logic is a step towards reducing the enormous amounts of interconnect in todays VLSI circuits. It offers the use of signal space that combines some of the efficiency of analogue signalling with the noise immunity of digital signalling. However, in order to exploit MVL there must be a consistent design methodology. This paper moves towards this by analysing existing circuit designs into a common framework and indicate situations where the advantage of MVL may be most apparent. Current mode multiple valued logic circuits have proven themselves to be useful in the design of circuits such as multipliers [I], neural networks [6],and PLAs 121. The work of Current et al. 171,and Summerfield et al. (51 gives a set of building blocks from which we can construct any logical operation in quaternary, i.e. a modulo 4 sum and product, giving a simple solution to logic expressed in the form of Reed-Muller expansions. We look at circuits designed in current mode MVL and investigate MVLs inherent drawbacks and advantages. Following that, we discuss the design of, and possible extensions to, various simple arithmetic building blocks designed by ourselves and others. Large reductions in bus area are shown to be achievable in Wallace trees by using these circuits. We suggest the use of basic cells combined with multiple output sections that can be fitted onto these cells to alleviate the problem of unit fan-out that current mode circuits have. t This work was supported in part by IED Project No. 1053. S. Summerfield Department of Engineering. University of Warwick, Coventry, CV4 7AL, U.K. esrev@csv.warwick.ac.uk (+44) 203-523873 CURRENT MODE CIRCUITS All current mode circuits are built up from the same basic circuit elements although they are not always represented or implemented in the same way. The basic elements are summing nodes, current mirrors, comparators, and switched current sources. Standard binary logic is also included in some circuits. The summing node is often referred to as a ‘free function’ since no logic is required to implement it. All we have to do to sum two current outputs is connect those outputs together, and we get the sum by Kirchoff‘s current law. This sum needs to be split from a carry if there is one, and quantised. The simple two transistor current mirror is also very well used. It allows us to turn an addition into a subtraction, and vice versa for unidirectional systems (i.e. where a current can only travel in one direction on a connection between two blocks). We can also use it to produce multiple copies, of an input, each multiplied by a constant factor. The simple current mirror is however, not a perfect device. It has many potential problems, and so more complicated mirrors such as the cascode mirror are sometimes used [3].For bi-directional systems, a slightly more complicated mirror is required, but it allows for the inversion, and replication of an input current. In addition, we can split the bi-directional current into it’s positive and negative parts, i.e. a pair of unidirectional currents. Comparators are required so that we can restore a current mode signal to it’s proper signal levels. The comparator is often lumped with switched current sources, but it should be noted that the communication between these two sections is a binary signal, and consequently this is an ideal place for simple binary logic such as is used by Current [7]. Comparators require references to compare against. These can be generated locally as with Kawahito’s circuits [I], or broadcast as a gate voltage for a local source. In practical implementations we would require a stable on chip reference for example IS], or accurately defined transistor parameters as used by Kawahito [I]. CURRENT MODE ADDERS In this section, we examine leading designs of adders in the current mode MVL area. We begin with K. W. Current et al.’sadder which is shown in block from in figure la. This circuit has three inputs two of which are quaternary inputs, and one is a carry, all of which come into the circuit on the same physical connection. The currents are summed on the input node, and then seven
  • 280 0 1 2 3 4 5 6 >6 comparators are used to distinguish between all possible input quaternary variables, but also because some functions are easier to combinations. A small amount of binary logic is then used to implement than others. Any function which can use a sum has got split the carry, and sum outputs. This circuit is constructed in a a built in advantage, because of it's ease of implementation. standard CMOS process. The most obvious function that can effectively utilise the 1 9 nla 6 2 4 3 3 4 2 6 nla 9 1 nla 0 S 1 0 3 2 2 1 3 3 0- a) A Second summing node b) Figure 1. The two current mode adder types. Carry lines are omitted for clarity. Value I Encoding A I Encoding B 0 I -4 I 7 Sum I OutputC OutputD <O I 0 I nla Tathe 1. Encoding (a), and decoding (b) for a quaternary single digit multiplier Kawahito et al. 111 use a different approach as shown in figure 15. Using redundant numbers is an inherent part of the design of their multiplier. The numbers are represented by bi-directional currents and the adder is in two parts. The first part splits the sum of the two bi-directional quaternary inputs into a carry, and an intermediate sum. In the second stage, the carry from the preceding digit is added to the intermediate sum on the second summing node, and the result is quantised. This circuit was implemented in CMOS with an extra option: a depletion mode PMOS transistor, with very low threshold voltage variations. The first stage of this design does not quantise the intermediate sum. Current's adder, and the individual stages of Kawahito's adder can be seen to be made up of the same three elements: a decoder which is a set of comparators, optional binary logic, and an encoder consisting of switched current sources. These two examples show the two methods available to us for dealing with a summed input. We can either decode once, and use logic to determine the outputs, or we can have a second summed node which sets the input into the range of the second stage: the quantiser. The two stage process can have advantages in that, some functions will yield a smaller design using this technique. SINGLE DIGIT MULTIPLIERS The design of efficient MVL circuits is dependant on having a good set of basic logic building blocks. Clearly any set of logic blocks that can implement all possible functions is usable, but to find an efficient set is more difficult. This is not onlv because of the over four billion possible quaternary functions of two summing node, is an adder. We simply produce currents proportional to the input values, and sum them on a node. This is not the only use however, once we see that we can code the inputs in many different ways. For example Summerfield, Clarke and Nudd [SI encode the input current to be approximation of the log of the input value. This coupled with a modified quantisation, and carry creation stage that performs a pseudo-anti-logarithm gives a single digit multiplier. In general, we can take modified encoders, and quantisers and form any function. However it should be noted that with present processing technology, it would be difficult to create a circuit which could differentiate between all of the 16 input combinations from two quaternary inputs. This is because of the limited accuracy possible with simple current mode circuits. Each function that we wish to create may have many possible encoderldecodersets, and choosing the best one is very difficult. For an example, we can look at the log encoding used by Summerfield et al. 151 which is shown as A in table la. The two inputs are summed together, and a unit of current added. This extra unit shifts the result of the summation, so that only a unidirectional current need be considered. The decoding is shown by the function given as C in table lb. All the negative currents, and the zero current represent the same output value 0. So to decide whether or not we have to output a 0, all we need is a comparator at half of one current unit. It is possible to find other encodings that have different characteristics, for the same product function. If we encode the inputs as shown as B in table la for example, and then decode as shown as D in table 1b, then we have the same overall functionalitv as with A. and C tables la. and l b
  • 281 2 3 4 5 respectively. However, there is never a negative current flowing, grouping can be seen with the zeros in the H decoding. We can on the node, so it can be arranged that the circuit operates in such sometimes reduce the number of comparators required still further a way that many of the transistors in the circuit are always by using a two stage system like that shown in figure Ib. switched on, speeding up the circuit. 0 - 1 0 0 Ou utG *Output H 0 0 0 1 - 1 Table 2. Encoding (a), and quantisation (b) for a signed binary single digit multiplier output b) Figure 2. a) An MVL, and b) a binary Wallace tree structure A GENERALISED DESIGN METHODOLOGY As we have already mentioned, we can create most functions using the concept of encode, sum, decode, and logic (which we shall assume to be part of the decoder for the rest of this section). What is important is organising the encoding to make the decoding easier. For example, when we take a function such as a signed binary multiplier, we could encode the inputs as shown by E or F in table 2a. In the case of E, the required decoder is shown as G in table 2b. We need 4 comparators to be able to distinguish between the different possible output values (at 0.5, 2.5, 3.5, and 5.5 current units), but the H decoding which corresponds to the F encoding requires only 3 comparators ( at 3.5, 4.5, and 5.5 current units). There will be many more encodings that can give the same result. Simple cases such as unsigned additions will at best require 1 less comparator, than there are possible output values ( assuming that we use a single stage circuit like that of K. W. Current). This is because we can group each possible output value into one range of currents that does not overlap with any other output value. This USING CURRENT MODE LOGIC IN NETWORKS Wallace tree structures are notorious for being difficult to lay out efficiently. They are not naturally placed in rectangular blocks, and routing large trees is a major problem. With current mode circuits the routing problem is greatly reduced, as it is with MVL. The reduction in current mode circuits is due to the fact that the inputs to each full adder share the same physical input connection, reducing the number of busses. The MVL advantage is due to the reduced number of wires in each bus. This leads to very great savings when laying out structures such as these in current mode MVL. An example is shown in figure 2a. Figure 2b is a corresponding binary voltage mode block representation. The hatched areas are interconnection busses, and the arrows show the inputs, and outputs from and to the busses. The MVL busses are half as wide, as we assume quaternary signals, and hence half the number of connections that would be required for binary. In addition, the sharing of inputs in the current mode circuit greatly reduces the interconnection difficulties. The bus area for the current mode quatemary circuit could be as little as 25% of that of the binary circuit.
  • a(lin) b(lin) 1 Log Log lin- lin- earPRODUCT Outputs{ a;b+c .d(lin) (cTd).(c.d)(lin) Figure 3. An example schematic of a current mode circuit. CURRENT MODE MVL LIBRARIES When we are laying out larger circuits that use the building blocks already described, we may find that we need more than one encoding of a particular output, or more than one copy of an encoding. This is because of the unity fan-out of current mode circuits. A library could be designed so as to have each function as, an input section, and a set of output sections, one output section for each encoding type. It should be possible to fit any number of these output sections onto a single input section. Figure 3 shows a schematic for this style of library. The variables are shown with the way they have been encoded in brackets after the variable name. The decoder, and logic are in the SUM or PRODUCT sections, and the encoders (marked linear, and log) are simply slotted on the end. We encode in a log manner to perform a product, and a linear manner to perform a sum. This system makes use of the fact that the logic section output is voltage mode, and hence has an infinite fan-out, allowing it to drive as many encoders as necessary. The schematic shown is a logic circuit that has been described in modulo 4 sum and product form. These circuits could be designed to give carry outputs as well if they were also to be used for arithmetic. This kind of library is applicable to both the one and two stage of design styles already described. CONCLUSIONS We have shown that MVL circuits have inherent advantages in certain situations such as Wallace trees. Combined with current mode circuitry, the advantages become very apparent, as shown here, and by the multiplier designed by Kawahito et al. [I]. We have proposed various techniques for the creation of libraries of building blocks for generalised logic and arithmetic. These techniques would allow block level design of any circuit in current mode MVL. There are now in place, all the necessary parts for a library such as the one we have described. REFERENCES 111 121 S . Kawahito et al., "A high-speed compact multiplier based on multiple-valued bi-directional current-mode circuits", Proceedings 17th international symposium on mrrltiple- valued logic, pp. 172-180, 1987. F.. J. Pelayo et al., "CMOS Current-Mode Multivalued PLA's", IEEE transactions on circuits and systems; 38, 4, pp. 434-441, April 1991. 131 D. A. Freitas, and Current, K.W., "A CMOS current comparator circuit", Electronics Letters; 19, 17, pp. 695- 697, August 1983. K. Chen, and Svensson, C., "Current-mode CMOS cosine transform chip", Electronics Letters; 25, 17, pp. 1142- 1144, August 1989. 141 151 S . Summerfield, C. T. Clarke, and Nudd, G.R. "VLSI Arithmetic with Current Mode Multiple Valued Logic", Proc ISCAS92, Vol. 6 , pp. 3001-3004, May 1992. T. Yamakawa, and Miki, T., "The Current Mode Fuzzy Logic Integrated Circuits Fabricated by the Standard CMOS Process", IEEE transactions on computers, c-35, 2, pp. 161-167, February 1986. W. Current, F. Edwards, and Freitas, D., "A CMOS multiple valued test chip", Proc 17th International symposium on multiple valued logic, pp. 16-19, 1987. W. M. Sansen, F. 0. Eynde, and Steyaert, M., "A CMOS Temperature-Compensated Current Reference", IEEEjournal of solid-state circuits; 23, 3, pp. 821-824, June 1988. [6] 171 181