Semiconductor overview


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Semiconductor overview

  1. 1. Nabil Chouba http:// Semiconductor overview
  2. 2. The Beginning 1947 : Point Contact Transistor  BELL LABS : Bardenn, Brattain & Shockley * William Shockley : 1956 Nobel Prize in Physics
  3. 3. Integrated Circuit from 1960 to 2010 1961 First planer IC "flip-flop" 2010 IBM POWER7 transistors: 1.2 B Invented by Robert Noyce , Fairchild *integrated circuit Invented by Jack Kilby , Texas Instruments *cmos 45 , 5 GHz, cache, D ual DDR3 memory controllers Level 1 & 2 caches remain SRAM ,32MB eDRAM on-chip Level 3
  4. 4. Processor Evolution 1979 MOTOROLA 68000 the Most Powerful µp16-Bit 40k transistors 1971 Intel 4004 The First µp 4-Bit 2,25k transistors,24mm2 1976 Zilog Z80 the Most Popular µp 8-bit 4,5k transistors 1993 Intel Pentium 32 bit 3.1M transistors 2003 AMD Opteron 64 bit 233M transistors 2008 AMD Barcelona Quad-Core 128 bit 463M transistors ,283 mm2
  5. 5. Moore's Law : 1960 -Number of transistors on integrated circuit : Doubling every two years. -RAM storage capacity & Power consumption : Doubling every 18 months. *Gordon Moore
  6. 6. Transistor Scaling i4004
  7. 7. Financier Impact of Moore Law *Price of Megabit in CMOS
  8. 8. Human Brain In 2010, the semiconductor industry Manufactured roughly 1 billion transistors for every human on the planet;
  9. 9. CMOS technology <ul><li>C omplementary M etal O xide S emiconductor </li></ul><ul><li>Patented in 1967 by Frank Wanlass at Fairchild </li></ul><ul><li>Based on use of complementary and symmetrical pairs of p-type and n-type MOSFETs transistor </li></ul><ul><li>+ high noise immunity </li></ul><ul><li>+ low static power consumption. </li></ul><ul><li>+ high density </li></ul>
  10. 10. NMOS Transistor Basics 1. Cut-off Region: no channel exists (iD = 0) for all values of VD. (VGS < Vt) 2. Triode Region: The NMOS transistor is active and not “pinched off.” This means the value of VDS affects the value of iD (VGS > Vt and VDS ≤ VGS – Vt). 3. Saturation Region: The channel is “pinched off” because increases in VD have no affect on iD (VGS > Vt and VDS > VGS – Vt)
  11. 11. Saturation Region Technology fixed parameters : μ eff : is the charge-carrier effective mobility, Cox : is the gate oxide capacitance per unit area m : is the Body effect Vt : is the threshold voltage Fixed by designer : W : is the gate width L : is the gate length (L min fixed by the Technology ) V gs ( = Vdd)
  12. 12. NMOS & PMOS Transistor complementary and symmetrical pairs of p-type and n-type MOSFETs transistor
  13. 13. CMOS NAND Gate (back-end) Transistor Level Schematic Level Layout Level =0 = 1 =
  14. 14. ASIC FLOW (front-end) Schematic Block VHDL files Netlist Design Synthesis
  15. 15. Semiconductor Manufacturing Sand Silicium Wafer Die Packaging Chip Ingots
  16. 16. Manufacture/Making Ingots Czochralski process
  17. 17. Wafer <ul><li>A wafer is a thin slice of semiconductor material </li></ul><ul><li>High purity 99.999999 % crystalline silicon </li></ul><ul><li>Wafer sizes is 100, 150, 200, 300mm diameter. </li></ul>
  18. 18. Lithography Process
  19. 19. Stepper Costing several hundred to several thousand million yen ASML, Ultratech, Nikon, Canon - Early days of lithography used 456 nm wavelength light. - Lithography today is using 193 nm wavelength light.
  20. 20. Interconnect Layer
  21. 21. Design Tor Test Every chip are tested Teradyne tester <ul><li>Design For Test (DFT) </li></ul><ul><ul><li>Test cost 50% of the chip </li></ul></ul><ul><ul><li>Scan-Chain - ATPG </li></ul></ul><ul><ul><li>BIST : Built In Self Test </li></ul></ul>
  22. 22. Defect on ASIC  Defect increase as cmos technology shrinks  Defect on metal 1 wire malfunction of wire bonding machine Number of defect Transistor shrink Burnt part During test.
  23. 23. TEST Cost Fabrication capital versus test capital.
  24. 24. Chip Failure Bathtub curve.
  25. 25. Power Dissipation Thermal dissipation Traditional Power saving : -Lower the clock frequency (F clk ) -Lower the load capacity (C l ) -Lower the rail voltage (V dd ) Dynamic Power : C l V dd 2 P trans F clk Static Power : leakage  gate thickness New Power saving technique : -Power gating, Clock gating -Voltage & frequency scaling -Multi-voltage, Multi-threshold logic
  26. 26. TOP 10 from 1978 to 2008
  27. 27. Application Specific Integrated Circuit ASIC Semi- specific specific Programmable FPGA Sea of gate Standard cell Full Custom SOC Image sensor MEMS
  28. 28. MEMS (MicroElectroMechanical Systems) <ul><li>Main Application : </li></ul><ul><li>Accelerometers in consumer electronics devices : </li></ul><ul><li>- Nintendo Wii, 3D (3-axis accelerometers ) </li></ul><ul><li>- Cell phones (Apple IPhone ) </li></ul><ul><li>- Number of Digital Cameras </li></ul><ul><li>Park the hard disk head when free-fall is detected. </li></ul><ul><li>Pressure, Temperature, Oxygen and speed sensors </li></ul><ul><li>Ink jet printerhead </li></ul><ul><li>Microphones for phones (70%, Reach one billion by 2011) </li></ul>
  29. 30. CMOS Image Sensors <ul><li>Electrons produced is a function of the wavelength and the intensity of light striking the semiconductor </li></ul><ul><li>Transferred to a metering register (CCD sensors) </li></ul><ul><li>Measure voltage or charge, through an analog-to-digital converter, </li></ul><ul><li>Forms a digital electronic representation of the scene imaged </li></ul>
  30. 31. Image Sensors (example) - 352 x 288 image array - 60 frames per second image capture - Advanced algorithms to : cancel Fixed Pattern Noise (FPN), Eliminate smearing, reduce blooming. - Programmable I2C : control, gamma, gain, white balance, color matrix, windowing, and image output in either 4-, 8- or 16 bit digital formats
  31. 32. Full Custom <ul><li>no libraries available </li></ul><ul><li>+ highest performance and smallest die size </li></ul><ul><li>- disadvantages of increased design time, complexity, design expense, and highest risk. </li></ul><ul><li>Application analog/digital/sensors </li></ul>
  32. 33. Sea of gates array <ul><li>Only the interconnect is customized </li></ul><ul><li>Only some (the top few) mask layers are customized the interconnect </li></ul><ul><li>The interconnect uses predefined spaces between rows of base cells </li></ul><ul><li>Manufacturing lead time is between two days and two weeks. </li></ul>
  33. 34. Advantages : => mixed system possible ( analog/digital) => internal flexibility => high density Disadvantages : => middle cost => technology transistors / standard cell imposed and fixed => complex to master the technology Sea of Gate or masked gate array (MGA)
  34. 35. Standard cell <ul><li>involves a complex library development process: cell layout • behavioral model • Verilog/VHDL model • timing model • test strategy • characterization • circuit extraction • process control monitors ( PCMs ) or drop-ins • cell schematic • cell icon • layout versus schematic ( LVS ) check • cell icon • logic synthesis • retargeting • wire-load model • routing model • phantom </li></ul><ul><li>• All mask layers are customized transistors and interconnect </li></ul><ul><li>• Custom blocks can be embedded </li></ul><ul><li>Manufacturing lead time is about eight weeks. </li></ul><ul><li>use a design kit ( from the ASIC vendor) </li></ul>
  35. 36. Advantages : => complete control of time parameters and electrical => mixed system possible ( analog/digital/memes ) => flexibility => very high density => Low Power, high speed techniques Disadvantages : => High cost ( $20M and up for chips designed at 90nm) => hard and complex to master the technology => few companies (low competition) => High volume Product ASIC Standard Cell
  36. 37. FPGA Ken Chapman (Xilinx UK) 2003 . Programmable Interconnect <ul><li>FPGA = Field Programmable Gate Array </li></ul><ul><li>FPGAs contain the same basic resources </li></ul><ul><ul><li>Slices (grouped into CLBs = Configurable Logic Blocs) </li></ul></ul><ul><ul><ul><li>Contain combinatorial logic and register resources </li></ul></ul></ul><ul><ul><li>IOBs (Input Output Blocs) </li></ul></ul><ul><ul><ul><li>Interface between the FPGA and the outside world </li></ul></ul></ul><ul><ul><li>Programmable interconnect </li></ul></ul><ul><ul><li>Other resources </li></ul></ul><ul><ul><ul><li>Memory </li></ul></ul></ul><ul><ul><ul><li>Multipliers </li></ul></ul></ul><ul><ul><ul><li>Digital Clock Managers </li></ul></ul></ul><ul><ul><ul><li>Global clock buffers </li></ul></ul></ul><ul><ul><ul><li>Boundary scan logic </li></ul></ul></ul>
  37. 38. Advantages: => Technology easy to master => Reduced development time => Reprogrammable for some (ideal for prototyping) => Low cost Disadvantages: => Non-optimized performance => Internal architecture completely frozen => Only digital (with some exceptions) FPGA Field Programmable Gate Array
  38. 39. The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. ( Technology Timeline
  39. 40. FPGA Vs ASIC high moderate/high moderate /high All interconnection Weeks /months Weeks /months Standard Cell Very high moderate low cost high moderate moderate speed high low Very low Density All interconnection none Masks manufactories All interconnection none Masks designs Weeks /months minutes/hours minutes/hours Modification time months /years Weeks /months days/weeks Development time Full Custom Sea of gate FPGA
  40. 41. FPGA Vs ASIC <ul><li>total product cost = fixed product cost + variable product cost *products sold </li></ul><ul><li>The total production costs verify the relations:   FPGA = $ 21,800 + ( $ 39 . Volume produced)   Mga = $ 86,000 + ( $ 10 . Volume produced)   Standard Cell = $ 146,000 + ( $ 8 . Volume produced) </li></ul><ul><li>Then we can calculate the following break-even volumes : </li></ul><ul><li> FPGA/MGA ~ 2000 parts </li></ul><ul><li> FPGA/CBIC ~ 4000 parts </li></ul><ul><li> MGA/CBIC ~ 20,000 parts </li></ul>
  41. 42. Examples of fixed costs: training cost for a new electronic design automation ( EDA ) system hardware and software cost • productivity • production test and design for test • programming costs for an FPGA • nonrecurring-engineering ( NRE ) • test vectors and test-program development cost • pass ( turn or spin ) • profit model represents the profit flow during the product lifetime • product velocity • second source
  42. 43. FPGA Vs ASIC A break-even analysis for an FPGA, a masked gate array (MGA) and a custom cell-based ASIC (CBIC). Cost parts Number of parts or volume $1.000.000 $100.000 $10.000 10 100 1000 10.000 100.000 break-even FPGA / CBIC break-even FPGA / MGA break-even MGA / CBIC CBIC MGA FPGA
  43. 44. FPGA Vs ASIC ASICs comprise three separate regions, each with its own complexity, performance and cost characteristics.
  44. 45. Staggering Chip Design Costs <ul><li>$1000M designs </li></ul><ul><li>Huge financial risk per design </li></ul><ul><li>IC vendors becoming application solution providers </li></ul><ul><li>- Intel paid 1-2B to develop Atom, </li></ul><ul><li>- Microsoft spend 3-4B to develop Windows mobile. </li></ul>
  45. 46. Software-Differentiated Hardware
  46. 47. FPGA (review) Ken Chapman (Xilinx UK) 2003 . Programmable Interconnect <ul><li>FPGA = Field Programmable Gate Array </li></ul><ul><li>FPGAs contain the same basic resources </li></ul><ul><ul><li>Slices (grouped into CLBs = Configurable Logic Blocs) </li></ul></ul><ul><ul><ul><li>Contain combinatorial logic and register resources </li></ul></ul></ul><ul><ul><li>IOBs (Input Output Blocs) </li></ul></ul><ul><ul><ul><li>Interface between the FPGA and the outside world </li></ul></ul></ul><ul><ul><li>Programmable interconnect </li></ul></ul><ul><ul><li>Other resources </li></ul></ul><ul><ul><ul><li>Memory </li></ul></ul></ul><ul><ul><ul><li>Multipliers </li></ul></ul></ul><ul><ul><ul><li>Digital Clock Managers </li></ul></ul></ul><ul><ul><ul><li>Global clock buffers </li></ul></ul></ul><ul><ul><ul><li>Boundary scan logic </li></ul></ul></ul>
  47. 48. Market Forecast 15% FPGA provide the customizability of an ASIC without theneed to design and fab new devices for each platform. Xilinx has more software engineers than hardware engineers; at Altera, the mix is roughly 50-50.
  48. 49. The Configurable Logic Blocks (CLBs) <ul><li>Constitute the main logic resource for implementing synchronous as well as combinatorial circuits. </li></ul><ul><li>-Provide logic, arithmetic, and ROM functions </li></ul><ul><li>- Programmable as either a D-type flip-flop </li></ul>
  49. 50. FPGA interconnect Logic Block Switch Block Wire Segment Programmable Switch a c b e d f a=0 b=0 c=1 d=0 e=1 f=0 0 0 1 0 1 0 Programmable FPGA Memory RAM/ROM c e
  50. 51. FPGA interconnect
  51. 52. Spartan-3/3E Family Smallest Device - XC3S50 - XC3S100E 192 CLB 240 CLB 4 BRAM (18 KB each) 4 Multipliers Largest device - XC3S5000 - XC3S1600E 8320 CLB 3688 CLB 104 BRAM (18 KB each) 36 BRAM 104 Multipliers 36 Multipliers
  52. 53. Spartan-3 Product Matrix
  53. 54. Spartan-3 : Global Clock Network <ul><li>- Clock generation and management </li></ul><ul><li>- Eight Global Clock inputs called </li></ul><ul><li>GCLK0 - GCLK7 </li></ul><ul><li>Eight Global Clock Multiplexers : BUFGMUX that accept signals from Global Clock inputs and route them to the internal clock network as well as DCMs. </li></ul>
  54. 55. Spartan-3 : Digital Clock Manager (DCM) <ul><li>Flexible, complete control overclock frequency, phase shift and skew </li></ul><ul><li>DCM employs a Delay-Locked Loop (DLL) </li></ul><ul><li>- Feedback to maintain clock signal characteristics with a </li></ul><ul><li>high degree of precision despite normal variations in operating </li></ul><ul><li>temperature and voltage. </li></ul>
  55. 56. Spartan-3 : RAM Block <ul><li>Embedded RAM block </li></ul><ul><ul><li>Single port </li></ul></ul><ul><ul><li>Ture dual port ( port A and B : Independent Access) </li></ul></ul>Write Enable Clock Enable Set/Reset Clock Data Output Bus Parity Data Output Address Bus Data Input Bus Parity Data Input
  56. 57. Embedded RAM Operation
  57. 58. Spartan-3 : Dedicated Multipliers -Embedded multipliers that accept two 18-bit words as inputs to produce a 36-bit product. - The input buses to the multiplier accept data in two’s-complement form (either 18-bit signed or 17-bit unsigned).
  58. 59. Additional cores in FPGA The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN 0750676043 Copyright © 2004 Mentor Graphics Corp. (
  59. 60. Additional cores in virtex FPGA Virtex-5Q FPGA Family Members Virtex-II
  60. 61. Mixed-signal FPGA – Actel - Fusion Family - <ul><li>Include analog blocks : </li></ul><ul><li>Integrated A/D Converter (ADC), with 32 MUX inputs and Analog I/O PLL/OSC </li></ul><ul><li>Analog Quad core ( analog multiplexer, prescaler circuit, Current Monitor Block, Gate Driver, Temperature Monitor ) </li></ul><ul><li>Charge Pumps </li></ul><ul><li>Flash Memory block </li></ul><ul><li>Dual Port SRAM Block </li></ul><ul><li>Sleep/Standby Low-Power Modes </li></ul>
  61. 62. EDA Tools 1) Functional Verification Duopoly - Synopsys Vera and Cadence SpecMan &quot;e&quot; 2) Formal Verification Alternatives - Jasper, Mentor 0-In, Synopsys Magellan, Cadence IFV, Real Intent 3) RTL Simulation Triopoloy - Mentor ModelSim, Cadence NC-Sim, Synopsys VCS 4) RTL Synthesis Monopoly - Synopsys Design Compiler Alternatives - Cadence RTL Compiler, Magma BlastRTL, OAsys 5) Equivalence Checking Duopoly - Cadence Verplex and Synopsys Formality
  62. 63. EDA Tools 6) Test/ATPG/Scan/BIST Duopoly - Mentor FastScan/DFT Advisor and Synopsys TetraMax Alternatives: LogicVision 7) Floorplanning Semi-monopoly - Cadence First Encounter Alternatives: Magma Hydra, Synopsys Jupiter, Atoptech Apogee 8) Place and Route Triopoloy - Synopsys ICC, Magma Talus, Cadence Encounter Alternatives - Atoptech, Mentor Sierra 9) RC Extraction Duopoly - Synopsys Star-RCXT and Cadence Fire&Ice Alternatives - Mentor Calibre-xRC, Magma QuartzRC, Sequence Columbus
  63. 64. EDA Tools 10) IR Analysis Semi-monopoly - Apache Redhawk Alternatives - Cadence VoltageStorm 11) DRC/LVS Monopoly - Mentor Calibre Alternatives - Synopsys Hercules, Magma Quartz 12) Static Timing Monopoly - Synopsys PrimeTime Alternatives - Cadence ETS, Extreme GoldTime, Incentia TimeCraft, CLK-DA Amber, Magma QuartzTime 13) Signal Integrity Duopoly - Synopsys PT-SI and Cadence CeltIC Alternatives - Extreme GoldTime, Incentia TimeCraft, CLK-DA Amber
  64. 65. EDA Tools 16) FPGA Duopoly - Mentor Exemplar and Synopsys Synplicity Alternatives - tools from Xilinx and Altera 14) SPICE Alternatives - Synopsys HSIM/HSPICE, Cadence Spectre, Magma FineSim, Mentor, Nascentric, Berkeley 15) Full Custom Monopoly - Cadence Virtuoso Alternatives - SpringSoft Laker, Magma Titan, Synopsys Orion 17) Emulators/Acceletors Monopoly - Cadence Palladium Alternatives - Mentor Veloce, EVE, Dini, Synopsys HAPS